Hal Communications ID-1A User manual
HAL COMMUNICATIONS
CORR
BOX
365
URBANA, ILLINOIS 61801
QUALITY COMMUNICATIONS EQUIPMENT
*************************************************
WARRANTY
HAL
Communications Corp. warrants
that
the
HAL
I
D-1
A
Re-
peater Identifier shall
be
free
of
defects in materials and work-
manship under normal
use
and service
for
a period
of
one year
from
the date
of
the original invoice. Should such defects
occur
within
the warranty period, the identifier
will
be
re-
paired at no charge except
for
transportation costs upon
re-
turn
of
the
unit
to
the factory. Units returned
for
warranty
service must
be
postmarked
within
one year
from
the begin-
ning
of
the warranty period.
This warranty
is
and shall
be
in lieu
of
all other warranties,
whether expressed
or
implied, and
of
all other obligations
or
liabilities on the part
of
HAL
Communications Corp. resulting
from
the installation
or
use
of
this identifier.
The foregoing warranty
is
completely void on all units which
have
been
repaired
by
individuals other than
HAL
Communi-
cations Corp. personnel, those which
have
been
damaged,
abused, modified, improperly installed,
or
tampered
with,
and
those which
have
been subjected
to
improper voltages
or
currents.
*************************************************
Copyright
@
1972
by
HAL
Communications Corp.,
Urbana, Illinois. Printed in the United States
of
America.
All
rights reserved. Contents
of
this publication may
not
be
reproduced in any
form
without
the
written
permission
of
the copyright owner.
CONTENTS
I. Description
.................
.
............
.
.........
1
.
....
3
II.
Installation
.................
. .
....
7
Ill.
Test Procedure
...........
.
.........
.
....
8
IV.
Programming the Memory
.............
.
V. Theory
of
Operation . . . . . . . . . . . . . . .
........
12
VI.
Parts List
................................................
18
TABLES AND ILLUSTRATIONS
................
.
.........
8
..........
9
Table 1: Character Codes
...............
.
Table 2: Coding the Memory
for
"DE
WB9XYZ"
................
Figure 1: ID-1A Circuit Board Layout
..................................
4
Figure 2: Coding Chart
for
"DE
WB9XYZ"
..............................
11
Figure 3: Blank Coding Chart
......................................
11
Figure 4: Generating a
Dot
........................................
15
Figure 5: Generating a
Dash
. . . . . . .
..............................
15
Figure 6:
ID-1A
Schematic Diagram
...................................
17
I. DESCRIPTION
The
HAL
Communications Corp. I
D-1
A repeater identifier
is
designed
to
help owners
of
repeater
stations meet
FCC
requirements
for
periodic station identification.
It
automatically transmits the
station call sign at the required intervals whenever the repeater
is
in
use.
The I
D-1
A offers
these
advanced features:
•
TTL
integrated circuits
for
high noise
immunity
and wide operating temperature range
• Reprogrammable diode-matrix read-only memory
for
storage
of
the station call
sign
• Accurate interval
timing
derived
from
the AC power line
• Interval
timing
source
for
emergency
or
portable operation
from
DC
power
• Transistor switch
for
direct
control
of
the repeater keying relay
•
Page
control
input
to
inhibit
identification during paging tones
• Adjustable code
speed
• Low-impedance audio
output
with
adjustments
for
pitch and volume
• Regulated 5
volt
DC
power supply
•
Rugged
G-10 epoxy-glass
circuit
board
Operation
The I
D-1
A identifier
is
completely automatic.
It
senses
when the repeater
has
been actuated
and
immediately transmits the station call sign
by
feeding a keyed audio tone
to
the repeater trans-
mitter.
After
this initial identification
has
been sent, a short
"guard"
period commences.
At
the
same
time,
a three-minute
timing
interval starts.1
If
the repeater
is
again
keyed up during the guard period,
but
remains inactive during the nominal three-minute
timing
interval,
only
the initial identification
is
transmitted. This feature prevents the unnecessary repetition
of
the call
sign
if
the repeater
is
trig-
gered
briefly
by a noise burst
or
by
a short call
to
which there
is
no response.
If,
however, the repeater
is
reactivated after the guard period
but
before the
end
of
the timing
interval, the identifier
will
repeat the call sign
at
the end
of
the longer interval. The identification
will
be
transmitted approximately every three minutes
as
long
as
the repeater
is
activated once
during
each
interval.
If
the repeater
is
held continuously activated, the I
D-1
A
will
identify
at three
minute intervals.
If
the repeater happens
to
be
off
the air
at
the moment the identification
is
to
be
transmitted, a keying transistor
in
the I
D-1
A actuates the repeater keying relay, returning the trans-
mitter
to
the air while the call sign
is
being sent.
Identification may
be
inhibited
by
grounding the
page
control input.
If
this line
is
grounded when
the
timing
interval ends, identification will be delayed
until
the control line
is
released.
Circuit
Description
The identification
message
is
stored in a diode-matrix read-only memory (ROM). This memory
has
been
specially designed
to
store code characters (dots,
dashes,
or
spaces)
using a
minimum
number
of
diodes. The memory capacity
is
sufficient
to
store the letters
"DE"
plus any amateur call
sign.
1Timing intervals
of
approximately 6, 12,
or
24
minutes may also
be
selected
by
changing the position
of
ajumper
on the
circuit
board,
as
shown in the schematic diagram. The guard period remains the
same.
1
r On the
average,
the number
of
diodes
needed·
to
store a given
message
is
equal
to
about
two
thirds
of
the number
of
characters the
message
contains. £
Unlike many commercially available ROM's, the memory
used
in the I
D-1
A may
be
reprogrammed
by the user. The stored
message
can
be
changed
by
rearranging the diodes in the matrix. Complete
instructions
for
reprogramming the memory
are
given in section
IV
of
this manual.
Timing
for
the identifier
is
derived
from
the AC power line frequency and
is
therefore very stable
and
needs
no adjustment. A
series
of
integrated-circuit flip-flops divide the power frequency by a
factor
of
10,240
to
provide a basic
timing
interval
of
2 minutes, 50.7, sufficiently close
to
the
desired three-minute
timing
interval. As described on
page
12, the timing interval may
be
changed
to
2, 4
or
8 times the basic
timing
interval
if
desired. A
60Hz
unijunction oscillator
is
also
provided
to
supply a
time
source during D.C. operation.
Each
time
the identification
message
is
transmitted, the memory
is
read
out, one character at a
time. The memory
output
is
supplied
to
a character generator, which reconstructs the code charac-
ters
with
precise weight and spacing. The code
speed
may
be
adjusted
by
a potentiometer mounted
on the
circuit
board.
The character generator keys the audio oscillator, which supplies the audio signal
to
the repeater's
microphone line and
to
an
internal
monitor
speaker.
A
rugged
transistor switch
is
built
into
the ID-1A
to
activate the transmitter control relay. The
transistor
is
rated
to
handle
±25
volts
at
500
rna.
A high-voltage transistor switch, rated
to
carry
150
rna.
at
+250
volts
or
-150 volts
is
available
as
an
option. The normal high-current switch
is
recommended
if
you plan
to
control the repeater's push-to-talk relay.
All
ID-1A
circuitry,
including the regulated 5
volt
power supply,
is
contained on a 3 x
6"
circuit
board. The power transformer, fuseholder, test switches, connectors and bypass capacitors
are
mounted external
to
the board.
The I
D-1
is
available assembled in
1~"
high
by
4"
deep rack-mounted
(19''
wide) cabinet, or
is
available
as
an
assembled, tested
circuit
board ready
for
mounting and shielding.
2
c
II.
INSTALLATION
OF
ASSEMBLED
CIRCUIT
BOARD
Mounting and Wiring ,
Since the
ID-1A
circuit
board
is
supplied wired and tested,
it
is
necessary
only
to
mount
the board
and
the
external components in a suitable enclosure, such
as
a
HAL
cabinet
or
a Bud
Minibox,
and
to
connect the
identifier
to
the
repeater transmitter.
Figure 1 shows the
circuit
board and
the
terminals
to
which the
following
external components
are
connected:
1.
Power transformer (including
primary
circuit
wiring)
2.
Fuseholder
3. Speaker
4.
Audio
output
connector (phono jack)
5. Keyed
output
jack (%" phone jack)
6.
Keyed
input
jack (phono jack)
7.
Page
control
jack (phono jack)
8.
DC
voltage
input
(phono jack)
9. Test switches A and B
The power transformer secondaries should
be
wired in parallel
to
provide 6.3 volts. The
two
pri-
maries should be connected
in
parallel
for
115 VAC operation,
or
in series
for
230 VAC operation.
Be
certain
to
observe the
polarity
of
the leads when connecting the windings in series
or
parallel. A
terminal strip
is
provided
for
the
wiring
of
the transformer primary
circuit,
which includes the trans-
former
leads, the fuseholder,
the
power cord, and the line bypass capacitors. Bypass each side
of
the
power line
to
the cabinet
with
the .001
ufd
capacitors provided. Connect the power cord ground
conductor securely
to,the
cabinet.
The two-inch speaker provided
for
monitoring
and testing the I
D-1
can
be
mounted most con-
veniently
by
simply gluing
it
to
one side
of
the cabinet. Scotch spray adhesive, Elmer's
white
glue,
or some similar cement
is
adequate.
The
input
and
output
jacks,
as
well
as
the
test switches, may be mounted
at
any convenient location
on
the
cabinet and connected
to
the
circuit
board
as
shown in Figure
1.
The keyed
input
jack
(a
phono connector) carries
the
signal
which
triggers
the
I
D-1
A whenever the repeater
goes
on
the
air.
Grounding
the
center contact
of
this jack activates the identifier. The jack may
be
connected
to
any
unused contacts which close when
the
repeater
is
keyed up. Connect a
0.1
ufd
capacitor across the
jack terminals
to
prevent noise pulses
from
activating
the
I
D-1
A.
Test switch B
is
also connected across
the
keyed
input
jack. Depressing this switch
has
the
same
effect
as
keying up
the
repeater.
It
is therefore useful in testing the identifier. Permenantly closing
this switch (grounding
the
keyed
input
jack)
will
cause
the I
D-1
A
to
identify
at
the end
of
each
timing
interval.
The keyed
output
jack
is
used
to
connect
an
external transmitter
control
relay
to
the transistor
switch in
the
I
D-1
A,
allowing
the
identifier
to
activate the transmitter when
an
identification
is
to
be
sent. When
the
switching transistor conducts,
it
grounds the center conductor
of
the jack. The
transistor can switch either positive
or
negative voltages, depending on
the
way the
output
jack
is
wired
to
the
circuit
board
(see
Figure 1). Bypass the jack terminals
with
the
.01
ufd
capacitor
supplied.
3
o::t
r- -
...
~
-
"'
Timer Length
Strap
Fig.l
Component
Layout
~
·
-Speaker
HAL Communications
10-lA
Identifier
The transistor switch
is
rated
at
±._25
volts and
500
rna., which
is
adequate
to
switch push-to-talk
relays operating from a 12 volt
DC
source. If
your
repeater uses a 6 volt relay, be sure
that
it draws
-less
than
500
rna. before connecting it
to
the
ID-1A.
Connect
the
clamping diode provided across
the
terminals
of
any
relay switched
by
the
I
D-1
A.
This
diode eliminates
the
switching spike generated when
the
relay
current
is
interrupted. Without
the
diode
the
spike voltage may damage
the
switching transistor. The diode should be connected with
its cathode toward
the
positive end
of
the
relay coil so
that
it
is
normally nonconducting.
The keyed audio
output
is
fed
to
the
transmitter through a phono connector. The relatively low
impedance
of
the
output
terminals permits driving
the
microphone lines
of
most transmitters
di-
rectly. Bypass
the
audio
output
terminals
at
the
jack with a
.01
ufd capacitor.
Test switch A
is
provided for bench testing
of
the
I
D-1
A. It causes
the
coded message
to
be gen-
erated each
time
it
is
pushed, whether
or
not
a complete timing interval has passed. Repeated clo-
sures
of
this switch (or
contact
bounce) may cause errors
in
the
transmitted message. Use
the
switch
for off-the-air testing only;
do
not
make
any
external connections
to
the
switch contacts.
The page control input can be used
to
ensure
that
no identification will be sent during a paging call.
If
the
end
of
the
timing interval
is
reached when
the
page control line
is
grounded,
the
identification
will be delayed until
the
line
is
released. The state
of
this control line does
not
affect
the
internal
timer. If
the
line
is
used, bypass it with a
.01
ufd capacitor.
Typical Installations
The ID-1A incorporates many features,
not
all
of
which need be used
in
a particular application.
To
help in planning an installation, here are
two
typical examples:
Situation
A:
An
amateur
-band repeater
is
to
be identified
at
the
required three-minute intervals.
The push-to-talk relay
in
the
transmitter
is
controlled
by
an
output
from
the
receiver. One end of
the
relay coil
is
connected
to
a +12v
DC
source capable
of
supplying
the
200
rna
needed
to
activate
the
relay.
The
identifier
is
to
be operated from a 12v
DC
source.
The
page control feature
is
not
needed.
Procedure:
1.
Set
the
timer for
the
three-minute interval
by
connecting
the
jumper
to
the
three-
minute position (3)
on
the
PC
board.
2. Strap
the
timer
input
to
the
internal clock (I).
3. Supply 12v
DC
to
the
unregulated supply input through a 15 ohm, 5
watt
resistor.
Leave
the
power transformer unconnected.
4. Locate an unused
contact
pair
on
the
receiver relay. Connect
the
keyed input line
to
one
contact; ground
the
other
contact.
5. Connect
the
emitter
of
the
transistor switch
to
ground. Connect
the
collector
to
the
low side
of
the
push-to-talk relay. Wire
the
damping diode across
the
relay coil, with
its cathode toward
the
positive end
of
the
coil.
6. Couple
the
audio signal
to
the
transmitter audio
input
circuitry.
7. Connect
the
speaker and
test
switches as described
in
the
preceding section.
8. Leave
the
page control input unconnected.
5
Situation 8: A commercial repeater for handling messages
is
to
be identified every
24
minutes
re-
gardless
of
how often
the
repeater
is
activated. However,
if
the
receiver
is
active and a message
is
C''
being sent, transmission
of
the
call sign
is
to
be delayed until
the
message has been completed. The
~
identifier
is
to
operate from a 120v
AC
power source. The transmitter
is
controlled by a 12v
DC,
200
rna
relay.
Procedure:
1.
Use
the
normal 120v Ac connections
to
supply power
to
the
I
D-1
A.
2.
To
provide continuous operation, ground
the
key line.
3. Set
the
timer for a 24-minute interval by inserting
the
jumper wire
in
the
proper
hole (24)
on
the
PC
board.
4. Strap
the
timer input
to
use
the
AC
line (L)
as
its timing source.
5. Connect
the
transmitter relay as described
in
step 5
of
the
previous example.
6.
In
the
receiver, locate
the
relay which closes when messages are being received. Con-
nect
the
page control line
to
an unused contact; ground
the
other
contact
of
the
pair
so
that
the
page control line will be grounded when
the
relay
is
closed.
7. Connect
the
speaker, audio
output,
and test switches as described previously.
Adjustments
The ID-1A requires only three simple adjustments before it
is
put
into operation.
The code speed
is
adjusted by
the
speed control. For checking
the
speed,
press switch A
to
start
the
coded message.
~
The audio
level
is
controlled by
the
volume adjust pot.
The
tone
control adjusts
the
oscillator pitch.
Again, test switch A
is
convenient for checking
the
settings.
The power supply voltage and
the
internal timing oscillator are set prior
to
shipment, and should
not
require adjustment.
If
adjustment becomes necessary, refer
to
the component layout for
the
location
of
the
controls and measurement points.
6
~
Ill.
TEST
PROCEDURE
•
If
you should
have
difficulty
with
your
ID-1A, you
can
check its performance
by
conducting the
following tests:
1.
Apply
AC
power
to
the identifier and check the regulated
DC
voltage at the emit-
ter
of
the regulator
pass
transistor (the
MJ
E521).
It
should
be
between +4.7 and
+5.1 volts.
If
it
is
not, adjust the power supply voltage control.
If
you cannot bring
the voltage
within
these limits, check
for
defective components in the power supply.
2.
If
the power supply voltage
is
correct,
push
test switch A. The speaker should emit
the coded identification
message
immediately.
It
should
be
possible
to
adjust the
code
speed,
the audio tone, and the volume
with
the appropriate controls.
If
the
identifier emits a very short, fast burst
of
code characters, check the 47 ufd capaci-
tor
in the master clock circuit.
3.
If
the above steps
have
not
isolated the problem,
press
test switch A again.
After
the
coded
message
has
been
emitted, wait
until
about half
of
the time interval
has
elapsed. Then push test switch
B.
After
the timing interval
has
been
completed, the
identifier should repeat the coded
message.
4.
If
the identifier
has
performed properly in step 3,
wait
until
one more timer interval
has
elapsed. The identifier should
not
repeat the coded
message.
5.
After
step 4
has
been
completed, push test switch 8 again. The identifier should
emit the coded
message
immediately.
If
the identifier
has
successfully
passed
these five tests
it
is
working properly. Check all connections
between the I
D-1
A and the repeater transmitter
for
loose
joints
and
wiring errors during final in-
stallation.
7
IV. PROGRAMMING THE MEMORY
The
ID-1A read-only memory (ROM), which stores
the
identification message
to
be
transmitted,
is
of
the
diode matrix
type.
It
is
designed so
that
a minimum
number
of
diodes
is
required
to
store
a
given message.
Although
the
I
D-1
A
is
normally supplied with
the
desired message precoded into
the
memory,
the
user can change
the
stored message
by
altering
the
arrangement
of
the
diodes
in
the
matrices.
The
process, a relatively simple
one,
will be explained
in
the
following paragraphs.
Memory
Format
The
memory
is
capable
of
storing
forty
code
"characters"
(dots, dashes,
or
spaces). Each character
is
composed
of
two
logic
"bits".
The
memory
is
made up
of
two
separate matrices,
one
called
the
"dash"
matrix
and
the
other
the
"space"
matrix. Each stores
one
of
the
two
bits
that
make up a
given character.
As
the
message
is
transmitted,
the
contents
of
the
memory
are read
out
sequentially,
one
character
(two
bits)
at
a time. The
output
signals are fed
to
the
keyer
circuitry, where
they
cause
the
keyer
to
reproduce
the
stored
character.
Since each character consists
of
two
bits,
any
one
of
four
possible
combinations
(and
therefore
any
of
four
different
characters) may
be
stored
at
each
memory
location:
Character
Dot
Dash
Space
End
TABLE 1: Character Codes
Space Matrix
0
0
1
1
Dash Matrix
0
1
0
1
(1
indicates
the
presence
of
a diode,
0 indicates
the
absence
of
a diode)
Note
that
the
keyer
automatically
produces
a
short
space, equal in length
to
a
dot,
after
each
dot
or
dash. No separate
code
character
is
needed
to
generate this intercharacter space.
The
"space"
char-
acter
therefore
is
used only
to
generate
the
longer spaces required
between
complete
letters
or
be-
tween words. It
is
equal
in
length
to
two
dots.
The
"end"
character
is
always used as
the
last char-
acter
in
the
coded
message;
it
tells
the
keyer
circuitry
that
the
message is
completed.
Coding
the
Memory
To
code
the
memory,
all you need
to
do
is
connect
diodes
at
the
appropriate
places
in
the
matrices.
For
example, if
the
first
character
to
be
transmitted
is
a dash, a
diode
is
connected
at
location 1
in
the
dash matrix,
but
location 1
of
the
space matrix
is
left vacant.
Figure 2 shows
the
physical arrangement
of
the
matrix circuit board. viewed from
the
top,
with
the
memory
coded
to
transmit
the
message
"DE
WB9XYZ".
To
illustrate
how
the
coding
is
done,
we
will follow
the
process used
to
store
this message.
The
first step
is
to
break
the
message
down into
a series
of
dots. dashes. and spaces, as shown
in
Table 2
on
the
following page.
The
dash
and
space matrix
columns
are
then
filled
in
by
using
the
code
patterns
given in Table 1.
One
space character
is
used
between
each letter
or
number
in
the
message;
three
are used
to
form
the
longer spaces between words. An
end_
character
must
be
in-
cluded as
the
last
character
in
the
message.
8
...
TABLE
2: Coding the Memory
for
"DE
WB9XYZ"
Memory
Location
1
2
3
4
5
0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Letter
D
E
w
B
9
X
y
z
Character
Space
Space
Dash
Dot
Dot
Space
Dot
Space
Space
Space
Dot
Dash
Dash
Space
Dash
Dot
Dot
Dot
Space
Dash
Dash
Dash
Dash
Dot
Space
Dash
Dot
Dot
Dash
Space
Dash
Dot
Dash
Dash
Space
Dash
Dash
Dot
Dot
End
9
Space
Matrix
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Dash
Matrix
0
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
0
1
If
the
message
to
be ·coded (including
the
end character) does
not
require
the
use
of
all
40
memory
locations, it
is
well
to
insert extra space characters
at
the
beginning
of
the
message. These will delay . 0
the
beginning
of
the
message, allowing time for control relays
to
activate
the
transmitter before
the
first character
is
sent.
In
our
example,
the
message plus
the
end character require only
38
memory
locations, so we insert
two
space characters ahead
of
the
first message character.
Once
the
table has been constructed, we may use
the
coding chart
in
Figure 2
to
mark
the
locations
in
the
matrix where diodes must be inserted.
In
the
drawing,
the
diode locations
in
both
the dash
and
the
space matrices are numbered from one
to
40. Starting with
the
space-matrix column
in
the
table, we mark a diode
at
locations
one
and two of
the
space matrix, since
the
space-matrix column ,
contains ones for these locations.
We
leave locations three through five empty, however, since
the
l
space-matrix column contains zeroes. The process
is
continued for all forty locations
in
the
space
matrix. The diodes
in
the
dash matrix are then marked
in
the same way, using
the
contents
in
the
·
dash-matrix column
in
the
table. "
Figure 3 provides a spare coding chart
to
use
in
programming
your
own message. Once
the
table of
characters has been constructed and
the
chart properly marked, diodes are inserted
in
the
board
at
the
required locations and are soldered.
Be
sure
that
the
diode cathodes connect
to
the
printed
conductors on
the
bottom
of
the
circuit board. It pays
to
carefully recheck
your
work
at
each stage
of
the
process
to
guard against wiring errors.
When soldering
the
diodes
in
place, use a low-voltage, pencil-tip soldering iron. Use only enough
heat
to
obtain a good connection. Overheating
the
joints may damage
the
circuit board or
the
diodes. Use a limited
amount
of
solder and check
to
make sure
that
excess solder does
not
bridge
across adjacent conductors.
Changing
the
Stored Message
If you are recoding a memory
to
change
the
stored message, it often saves time
to
construct a table
for
both
the
old and new messages.
By
comparing
the
tables you may find it
is
not
necessary
to
remove all
of
the
existing diodes-some may already be
in
the
correct position for
the
new message.
Remove unneeded diodes from
the
board by snipping
the
diode leads with a pair of wire cutters. It
is
safer
t,o
snip
the
diodes
out
than
to
risk damage
to
the
circuit board by trying
to
unsolder them.
Carefully remove
the
leads from
the
holes with a soldering iron and needle-nosed pliers. Clean each
hole
to
ease
the
reassembly process.
Germanium signal diodes such as
the
1N270 make suitable replacement diodes.
To
save
the
trouble
of locating and replacing defective diodes after
the
board has been completed and tested, check
each diode (whether new
or
used) with an ohmmeter before installing it.
Factory Recoding
HAL Communications Corp. will recode
your
identifier's memory
for
a $5J)0 service charge plus
shipping costs. Please notify
the
factory before returning your keyer for recoding.
10
Fig.2:
Coding Chartfor
DE
WB9XYZ
I
l
0 0 0 0 0 0 0 0 0 0
Fig.
3:
Blank Coding Chart
11
V.
THEORY
OF
OPERATION
The
ID-lA
circuitry
is
composed
of
four
basic parts: the
timing
and control circuits, the memory,
~
the character generator, and the power supply. With the exception
of
the relay drivers and the
power supply regulator, all circuits
are
made up
of
TTL
logic devices.
The
following
is
a detailed explanation
of
how
each
portion
of
the
circuitry
operates. For a review
of
the basic
circuit
functions, refer
to
Section I
of
this manual.
Timing and Control
Circuitry
The control
circuitry
in the I
D-1
A
senses
when the repeater transmitter
goes
on the air, triggers the
transmission
of
the coded identification
message,
starts and stops the
timer
circuitry
at the appro-
priate moments, and actuates the transistor keying switch. The
timer
circuits establish the duration
of
the basic
timing
intervals and
of
the guard period.
The identifier control circuits are connected
to
the repeater via the keyed
input
jack. Whenever the
repeater
is
activated, the identifier
input
bus
is
grounded, setting the INPUT SENSE
flip-flop
and
driving its
output
high. Assume
for
the moment
that
the
output
of
the
TIMER
END
flip-flop
is
also
high. The signals
from
these latter
two
flip-flops
are
fed
to
a
NAND
gate along
with
the
page
control
input. Its output--the
START
line--then
goes
low. The
START
line may also
be
driven
low
for
test
purposes
by
closing test switch A.
The signal on the
START
line
is
inverted, and
used
to
reset the row and column address registers
of
the memory circuit. The RUN line
goes
high, allowing the master clock oscillator
to
start. When the
RUN lines
goes
high, the
TIMER
END
flip
flop
is
reset and the
START
line allowed
to
go
high. The
coded
message
is
then transmitted,
as
will
be described in a later section.
The
timer
chain, which establishes the
time
interval between
successive
transmissions
of
the coded
~
message,
consists
of
a chain
of
frequency dividers. The
60Hz
power line waveform, taken
from
the
low-voltage side
of
the
power transformer,
is
converted
to
a squarewave by a
Schmitt
trigger
and
fed
to
the
first
divider in
the
chain.
The
timer
chain divides the line frequency
by
a factor
of
10·21
0,
or
10,240.1 Thus,
with
a
60Hz
input
frequency the
timer
emits
an
output
pulse every 2 minutes and
51
seconds, very close
to
the
desired three-minute
time
interval.
A
unijunction
oscillator
is
provided
to
drive the
timer
chain when operating
from
DC
voltage. The
reset terminal
of
the
first
divider in the chain
is
driven
by
the
output
of
the
TIMER
END
flip-flop.
When the identifier
is
inactive, this reset terminal
is
held in the high state, preventing the chain
from
dividing the line frequency.
When
the
identifier
is
activated and the initial identification
message
transmitted, however, the RUN line (the
output
from
pin 6
of
IC-1
B)
goes
high resetting the INPUT
SENSE and
TIMER
END
flip
flops. The
timer
chain reset terminal
goes
low,
allowing the
timer
to
divide.
After
the
timer
chain
reaches
its maximum number
of
counts, its
output
goes high; this signal
is
fed
to
the set terminal
of
the
TIMER
END
flip-flop,
changing the
flip-flop
back
to
the set condition. Its
output
returns
to
the
high state, resetting the
first
divider in the
timer
chain and holding the chain
inactive. During the
time
that
the RUN line
is
high, and
for
a short
guard
period after
it
goes
low,
the INPUT SENSE
flip-flop
is
held cleared and
input
keying
is
ignored.
For
this reason, a noise
pulse
or
short transmission
will
cause
only
one identification
to
occur.
1Timer intervals
of
approximately 6, 12, or 24 minutes may be selected by changing a jumper wire on
the
circuit ' .
·.
board,
as
shown
in
the
schematic diagram.
~
12
If, however,
the
repeater.
is
activated after
the
guard period
but
before
the
end
of
the
three-
minute timing cycle,
the
INPUT SENSE flip-flop
is
driven
to
the
set state again, and its
output
goes
high. When
the
end
of
the
timing cycle occurs and
the
TIMER END flip-flop
is
set,
the
START line
is
driven low once more.
Another
identification message
is
transmitted,
the
timer
chain
is
allowed
to
start dividing, and
the
entire
cycle
is
repeated.
If
the
repeater transmitter happens
to
be
off
the
air
at
the
moment
when an identification
is
to
be
transmitted, it
is
keyed up
for
the
duration
of
the
message
by
the
relay driver circuitry, which
is
connected
to
the
RUN
line. The relay driver uses a common-base amplifier stage (an MPS3703),
to
drive
the
MJE521 keying transistor. A keying relay
in
the
repeater
is
grounded through this tran-
sistor
to
put
the
repeater
on
the
air.
Memory
The identification message
is
stored
in
a diode-matrix read-only memory. It can store
up
to
39
characters (dots, dashes,
or
spaces) plus an
end
character which marks
the
end
of
the
stored mes-
sage. Each character consists
of
two
"bits";
each
bit
may have
one
of
two
logic states: 0
or
1 (low
or
high, respectively).
The
memory
is
divided into
two
matrices. One
is
designated
the
dash matrix
and
the
other
the
space matrix. Each stores
one
of
the
two
bits which make up a given character.
By
using all possible combinations
of
the
two
bits, we may define
any
of four different characters,
as
shown in Table 1
on
page
8.
When
the
contents
of
the
memory are read
out
sequentially, one
character (two bits)
at
a time,
the
character generator recreates
the
stored code characters.
Each memory matrix
is
composed
of
ten
columns and
four
rows, as shown
in
the
schematic dia-
gram. A
bit
is
stored
at
each intersection
of
a row and a column.
Thus
each matrix contains 40
memory locations. When a diode
is
connected between
the
row and column lines
at
a given location,
the
bit for
that
location
is
read
out
as a 1. If no diode
is
present,
the
bit
is
read
out
as a 0.
The memory readout process
is
controlled by
the
column and row address registers. These are
simply counters which
"address"
each memory location
in
sequence, causing its
contents
to
appear
at
the
matrix
output.
When
the
START line
is
activated,
the
address registers are reset
to
zero and
the
contents
of
the
first memory location
in
each matrix are read
out.
The column address register takes its driving pulse from
the
output
of
the
character generator. Each
time
a character
is
completed this register increments by one. Although
the
register
counts
in
binary-coded-decimal (BCD) code, its
outputs
are transformed into decimal code
by
a decoder cir-
cuit. As
the
count
progresses
the
ten
memory column lines are driven low,
one
at
a time.
The
others
remain high.
The row address register drives
the
memory row lines
in
both
matrices through a decoder circuit.
After it has been reset, all row lines
except
the
first
one
in
each matrix are held low. Since it takes
its driving pulse from
the
output
of
the
column address register, it increments
to
the
next
row only
after
all
ten
columns
of
a given row have been scanned.
At
the
output
of
each matrix,
the
row lines are connected
to
the
four inputs
of
a NOR gate.
If
all
the
row lines
in
a given matrix are low,
the
NOR gate
output
will be high, indicating a 1 bit. If any
of
the
row lines
is
high,
the
output
will be low, indicating a zero bit.
Suppose
that
the
address registers have
just
been reset.
The
first column line
in
each matrix will be
low;·
the
first row line will be high. Memory location 1
is
therefore being examined.
If
a diode
is
connected
at
location 1 in
the
dash matrix,
the
low voltage
on
the
column line will pull
the
row line
low. Since
the
other
row lines are held low
by
the
row address register,
all
four
row lines will be
low.
The
output
of
the
NOR gate
for
this matrix will be high, indicating
the
presence
of
a diode--a 1
bit.
13
If
no diode were present, the
first
row
line
would
be
high. The
output
of
the NOR gate would
be
driven
low,
indicating a 0
bit.
Notice
that
diodes
at
other columns along the
first
row
do
not
affect
the
output,
since all
of
the other column lines
are
high. 6
At
the
same
time
that
location 1
of
the
dash
matrix
is
being examined, the
bit
stored at location 1
in the
space
matrix
is
read
out
into
a separate NOR gate. The outputs
of
both NOR
gates
are
de-
coded and fed
to
the character generator which then produces the appropriate character.
After
the
first
character
has
been
generated, the column address register increments
by
one and the
contents
of
the second memory location in
both
matrices are
read
out. The process
is
repeated
until
all ten columns
of
the
first
row
have
been examined. The column address register returns
to
zero,
the
row
address register increments, and the memory locations in the second
row
are
examined. The
readout continues
until
an
"end"
character
(two
1 bits)
is
encountered. The decoding circuits then
instruct
the
character generator
to
stop, and the RUN line
goes
low.
Character Generator
The memory outputs are decoded
by
the character generator circuit, which reproduces the stored
code characters. The heart
of
this
circuit
is
the master clock oscillator.
It
determines the
speed
at
which the code stream
is
transmitted. The oscillator frequency, and therefore the code
speed,
is
adjusted
by
the 500-ohm
speed
control
potentiometer.
The clock's operation
is
controlled
by
a
NAND
gate; when the
input
of
this gate
is
high, the oscil-
lator
is
allowed
to
run. This
control
gate
is
driven
from
the RUN line, which in
turn
is
controlled
by
the NOR
gates
at the memory
output.
When either
or
both
of
the NOR gate outputs
are
low,
the
output
of
NAND
gate 1B
is
high and the clock runs. Both memory outputs
are
high
only
when
an
end
character
is
encountered. The clock then stops.
The master clock drives
two
flip-flops, which divide the clock frequency
by
two
or
four,
depending
~
on the state
of
the memory outputs. When
both
memory bits
are
zeroes, the second
flip-flop
is
inhibited
from
toggling
by
the
low
input
at its clear terminal. Its
output
remains high. The
first
flip-flop,
however, toggles
at
half the clock frequency, producing a symmetrical
dot
and
space,
as
shown in Figure 4. (This intercharacter
space
is
equal in length
to
a
dot.
It
should
not
be
confused
with
the longer
space
generated
by
coding a
space
character
into
the memory). The waveform at the
output
of
the
first
flip-flop
passes
through a
NAND
gate, which inverts
it
and
applies
it
to
the
KEYING
line.
If
the
output
of
the
dash
matrix
is
high
(a
1
bit)
and
that
from
the
space
matrix
low
(a
0
bit),
indicating a dash, the second
flip-flop
is
no longer inhibited
from
toggling.
It
changes state every
time
the
output
of
the
first
flip-flop
goes
high. When the outputs
of
the
two
flip-flops
are
added in
the
NAND
gate
the
desired
dash
waveform, shown in Figure 5,
is
produced.
To produce a
space
character, equal in length
to
a
dot
plus
an
intercharacter
space,
the
space
matrix
output
must
be
high and the
dash
matrix
output
low. Since the second
flip-flop
is
inhibited, a
dot
would normally be produced. The
output
of
the
space
matrix, however,
is
fed through
an
inverter
to
a gate which controls the audio oscillator. When the
space
matrix
is
high, the
input
to
the oscil-
lator control gate
is
held low, preventing the oscillator
from
running.
As
the memory address registers
scan
the contents
of
the memory, the character generator produces
each
character in sequence.
When
an
end character
is
detected
both
memory bits
are
high; the RUN
line, driven
by
the
output
of
a
NAND
gate
goes
low,
stopping the master clock, resetting the
TIMER
END and
INPUT
SENSE flip-flops, and releasing the transmitter keying relay. The
timing
sequence then begins,
as
described previously.
14
I I I
I I I
Ln_
I I I
I I I
I I I
I I I
Il_f
I I I
I I I
Flip-flop
A output
(pin
5, ckt 10)
NAND
gate
output
(pin
6,
ckt
9)
Fig.4:
Generating
a Dot
Flip
-flop
A output
(pin
5, ckt 10)
Flip-flop
B
output
(pin
9, ckt
10)
NAND
gate
output
(pin
6,
ckt
9)
Fig.
5:
Generating a Dash
15
r
l
I
I
Audio
Oscillator
The audio
output
of
the identifier
is
produced
by
an
integrated
circuit
oscillator. A
NAND
gate
~
permits
the
oscillator
to
run whenever "its inputs
are
high. One pin
is
normally held high
by
the •
output
of
the
space
matrix
(unless a
space
character
is
being transmitted). The
output
of
the char-
acter generator
is
supplied
to
the
other
input
via the
KEYING
line. Whenever the line
goes
high the
oscillator produces a tone. The
pitch
may be adjusted
by
the 500-ohm tone potentiometer.
An
inverting amplifier
is
used
to
isolate the oscillator
from
its load. The amplifier drives the speaker
and, via the audio
output
jack, the transmitter audio circuits. The audio
output
level
is
adjusted
by
the volume control.
Power Supply
DC
power
for
the identifier
circuitry
is
provided
by
a power transformer and full-wave rectifier
circuit. The power supply
output
is
regulated at
+5.0
volts by a conventional
series
regulator circuit.
The supply voltage
is
adjusted
by
the 500-ohm sampling potentiometer. A
0.1
amp time-delay fuse
in the transformer primary
lead
protects the power supply
from
overloads.
16
e
,.
.....
'-I
~
Fig.6:
lO-lA
Identifier
Test
Switch
A
# Type
Gnd
+5
1
7493
10 5
2
7493
10 5
3
7493
10 5
4
7473
11
4
5
7490
10 5
6
7473
11
4
7
7490
10 5
8
7442
8 16
9
7400
7
14
10
7474
7
14
11
7400
7
14
12
7405
7
14
13
7410
7
14
14
7404
7
14
15
7405
7
14
16
7405
7
14
17
7402
7
14
____
'T"
______
--
-----------
,.
o (
.26
sec., the
timer
will hove finished by the
time
the
identification
has f.inished.)
toTX
Relay
~
l~~~~~:~~)
.N.2.!.!L
1. All
resistors
l/4W±lQ"'o.
2.
All
capacitors
in JA-fd/voltoge
rating.
3. All diodes
1N270
orequiv.
4.
All
unmarked arrows ore
+5.0
V.
5.
Transformer
primary
may be
wired
1n
series
for
230v
operation
r:F-1--:---,
I l
I z I
1
1 Alternative output I
switch
connections I
L~~l~~J:J
DitllCOMMUNICATIONS
CORP.
[lt]lj
BOX
365
1 URBANA ILLINOIS161801
Rev.
1 - Sept.
6,
1974
ID-lA
Identifier
OAH
June 15, 1972 SCALE
No.ID-lA
APPROVED
P.
Tuclrer
Table of contents
