Himedia HM-LC43R15J User manual

Prepared CheckedⅠCheckedⅡApproved
Sep. 10. 2019
PANEL Specification
HM-LC43R15J
NOTE Specification is subject to change without notice. Conseuently it is better to contact to our company
before proceeding with the design of your product incorporating this Panel.
HIMEDIA Company #507, ACE-Gunpo, 52, Gongdan-ro 140 beon-gil, Gunpo-si, Gyeonggi-do, Korea
T +82. 31. 478. 8182 F +82. 31. 696. 6537 E [e-mail] H www.hi-media.co.kr
Rev. 1.0
Sep. 10. 2019

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Rev. 1.0
PANEL HM-LC43R15J
1. Revision Recode
Rev.
ECN No.
Description of Changes
Date
Prepared
1.0
Initial Release
2019/09/10

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Rev. 1.0
PANEL HM-LC43R15J
2. General Description and Features
This specification applies to the 43 inch Color TFT-LCD SKD model HM-LC43R15J. This Open Unit
has a TFT active matrix type liquid crystal panel with 3840 x 2160 pixels and V by one interface;
which can display up to 1.07 billion colors.
Item
Specification
Unit
Note
Active Screen Size
43
Inch
Display Area
941.184 (H) x 529.416 (V)
mm
Outline Dimension
953 (H) x 577.99 (V)
mm
Cell Dimension
953 (H) x 543 (V) x 1.4 (D)
mm
D: cell thickness
Driver Element
a-Si TFT active matrix
Bezel Opening
-
Mm
Recommend
Display Colors
10bit (8bit + FRC)
Colors
Number of Pixels
3,840 x 2,160
Pixel
Pixel Pitch
0.2451 (H) x 0.2451 (W)
mm
Pixel Arrangement
RGB vertical stripe
Display Operation Mode
Normally Black
Surface Treatment
Anti-Glare, 3H
Haze=2%
Transmittance (with Polarizer)
4.3%
Typical value
Weight
1530
g
Typical value
Display Orientation
Signal input with “ABC”
Note 1
Note 1. LCD display as below illustrated when signal input with “ABC”.
Front side
ABC
Source PCB

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PANEL HM-LC43R15J
3. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to
the unit or the unrecoverable damage on the device.
Item
Symbol
Value
Unit
Note
Min.
Max.
Logic/LCD drive Voltage
VDD
-0.3
14
[Volt] DC
Note 2
Input Voltage of Signal
Vin
-0.3
4
[Volt] DC
Note 2
Operating Temperature
TOP
0
+50
[℃]
Note 3
Operating Humidity
HOP
10
90
[%RH]
Note 3
Storage Temperature
TST
-20
+60
[℃]
Note 3
Storage Humidity
HST
10
90
[%RH]
Note 3
Panel Surface Temperature
PST
65
[℃]
Note 4
Note 2. Duration: 50 msec.
Note 3. Maximum Wet-Bulb should be 39℃ and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40℃ or less. At temperatures
greater than 40℃, the wet bulb temperature must not exceed 39℃.
Note 4. Surface temperature is measured at 50℃ Dry condition.

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PANEL HM-LC43R15J
4. Optical Specification
Optical characteristics are determined after the unit has been ‘ON’ and stable for approximately 45
minutes in a dark environment at 25℃. The values specified are measured on the center of active
area and at an approximate distance 500mm from the LCD surface at a viewing angle of φ and θ
equal to 0°.
Fig. 1 presents additional information concerning the measurement equipment and method.
Parameter
Symbol
Condition
Values
Unit
Note
Min.
Typ.
Max.
Contrast Ratio
CR
SR3, TRD-100
3200
4000
-
Note 5,6
Response Time (G to G)
Tγ
-
8
16
ms
Note 7
Color Chromaticity
Note 8
Color
Red
RX
With SR3
Standard light
source “C”
Typ.
-0.03
0.667
Typ.
+0.03
RY
0.324
Green
GX
0.271
GY
0.595
Blue
BX
0.138
BY
0.104
White
WX
0.289
WY
0.339
Viewing Angle
SR3
Note 5,9
x axis, right(φ=0°)
θr
-
89
-
degree
x axis, left(φ=180°)
θl
-
89
-
degree
x axis, up(φ=90°)
θu
-
89
-
degree
x axis,
down(φ=270°)
θd
-
89
-
degree

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PANEL HM-LC43R15J
Note 5. Light source here is the BLU of us module (film structure: two diffuser sheets).
Note 6. Contrast Ratio (CR) is defined mathematically as:
Surface Luminance at center location of all white pixels
Contrast Ratio = -------------------------------------------------------------------------------
Surface Luminance at center location of all black pixels
Note 7. Response time Tγ is the average time required for display transition by switching the input signal
for five luminance ratio (0%, 25%, 50%, 75%, 100% brightness matrix) and is based on Frame rate = 60Hz to
optimize.
Measured
Response Time
Target
0%
25%
50%
75%
100%
Start
0%
0% to 25%
0% to 50%
0% to 75%
0% to 100%
25%
25% to 0%
25% to 50%
25% to 75%
25% to
100%
50%
50% to 0%
50% to 25%
50% to 75%
50% to
100%
75%
75% to 0%
75% to 25%
75% to 50%
75% to
100%
100%
100% to 0%
100% to 25%
100% to 50%
100% to 75%
Tγ is determined by 10% to 90% brightness difference of rising or falling period. (AS illustrated)
The response time is defined as the following figure and shall be measured by switching the input
signal for “any level of gray(bright)” and “any level of gray(dark)”.
Fig. 3 Response Time
Note 8. Light source here is the standard light source “C” which is defined by CIE and driving voltages
are based on suitable gamma voltages. The calculating method is as following :
A. Measure the “Module” and “BLU” optical spectrums (W, R, G, B).

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PANEL HM-LC43R15J
Note 8. Light source here is the standard light source “C” which is defined by CIE and driving voltages are
based on suitable gamma voltages. The calculating method is as following :
A. Measure the “Module” and “BLU” optical spectrums (W, R, G, B)
B. Calculate cell spectrum from “Module” and “BLU” spectrums.
C. Calculate color chromaticity by using cell spectrum and the spectrum of standard light source
“C”.
Note 9. Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are
determined for the horizontal or x axis and the vertical or y axis with respect to the z axis which is
normal to the LCD surface. For more information see FIG4.
Fig. 4 Viewing Angle

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PANEL HM-LC43R15J
5. Interface Specification
5.1 Input power
This HM-LC43R15J Open Cell Unit requires power input which is employed to power the LCD electronics and
to drive the TFT array and liquid crystal.
Item
Symbol
Value
Unit
Note
Min.
Typ.
Max.
Power Supply Voltage
VDD
10.8
12
13.2
V
Note 10
Power Supply
Input Current
Black pattern
IDD
-
0.84
1.01
A
Note 11
White pattern
-
1.83
2.2
A
H-Strip pattern
-
1.54
1.85
A
Power
Consumption
Black pattern
PC
-
10.08
12.12
Watt
White pattern
-
21.96
26.4
Watt
H-Strip pattern
-
18.45
22.2
Watt
Inrush Current
IRUSH
-
-
5
A
Note 12
Note 10. The ripple voltage should be fewer than 5% of VDD.
Note 11. Test Condition:
(1) VDD = 12.0V, (2) Fv = 60Hz, (3) Fclk = 74.25MHz, (4) Temperature = 25℃
(5) Power dissipation check pattern. (Only for power design)
a. Black pattern b. White pattern
c. H-Strip pattern
R
G
B
R
G
R
G
B
R
G
R
G
B
R
G
R
G
B
R
G

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PANEL HM-LC43R15J
Note 12. Measurement condition : Rising time = 400us
5.2 Input Connection
LCD Connector: JAE FI-RTE51SZ-HF
Pin
Symbol
Description
Pin
Symbol
Description
1
VDD
Power Supply Input Voltage
26
LOCKN
Vx1 LOCK
2
VDD
Power Supply Input Voltage
27
GND
Ground
3
VDD
Power Supply Input Voltage
28
RX0N
Vx1 lane 0
4
VDD
Power Supply Input Voltage
29
RX0P
Vx1 lane 0
5
VDD
Power Supply Input Voltage
30
GND
Ground
6
VDD
Power Supply Input Voltage
31
RX 1N
Vx1 lane 1
7
VDD
Power Supply Input Voltage
32
RX 1P
Vx1 lane 1
8
VDD
Power Supply Input Voltage
33
GND
Ground
9
N.C.
No Connection
(for us test only. Do not connect)
34
RX2N
Vx1 lane 2
10
GND
Ground
35
RX2P
Vx1 lane 2
11
GND
Ground
36
GND
Ground
12
GND
Ground
37
RX3N
Vx1 lane 3
13
GND
Ground
38
RX3P
Vx1 lane 3
14
GND or N. C.
Ground or No Connection
(for us test only. Do not connect)
39
GND
Ground
15
N.C.
No Connection
(for us test only. Do not connect)
40
RX4N
Vx1 lane 4
16
N.C.
No Connection
(for us test only. Do not connect)
41
RX4P
Vx1 lane 4
17
N.C.
No Connection
(for us test only. Do not connect)
42
GND
Ground
18
SDA
SDA-12C Serial Data
Open : High (3.3V)
43
RX5N
Vx1 lane 5
19
SCL
SCL-12C Serial Clock
Open : High (3.3V)
44
RX5P
Vx1 lane 5
20
WP
EEPROM Write Protection
High (3.3V) for Writable,
Open/Low (GND) for Protection
45
GND
Ground
21
N.C.
No Connection
(for us test only. Do not connect)
46
RX6N
Vx1 lane 6
22
GND or N. C.
Ground or No Connection
(for us test only. Do not connect)
47
RX6P
Vx1 lane 6
23
N.C.
No Connection
(for us test only. Do not connect)
48
GND
Ground
24
GND
Ground
49
RX7N
Vx1 lane 7
25
HTPDN
Vx1 HTPDN
50
RX7P
Vx1 lane 7
51
GND
Ground

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Rev. 1.0
PANEL HM-LC43R15J
Note 13. Pin number start from the left side as the following figure
Note 14. Please leave this pin unoccupied. It can not be connected by any signal (Low / GND / High).
Note 15. Input control signal threshold voltage definition
Item
Symbol
Value
Unit
Note
Min.
Typ.
Max.
Input High Threshold Voltage
VIH
2.7
-
3.6
V
Input Low Threshold Voltage
VIL
0
-
0.6
V
Note 16. 12C Data and Clock
12C Data and Clock timing
Parameter
Symbol
Value
Unit
Note
Min.
Typ.
Max.
12C
SCL clock frequency
fSCL
-
-
1
MHz
Clock Pulse Width Low
tLOW
0.72
-
-
us
Clock Pulse Width High
tHIGH
0.29
-
-
us
Clock Low to Data Output Valid
tAA
-
-
0.62
us
Start Setup Time
tSTASU
0.26
-
-
us
Start Hold Time
tSTAHD
0.26
-
-
us
Stop Setup Time
tSTOSU
0.26
-
-
us
Data In Setup Time
tDSU
0.1
-
-
us
Data In Hold Time
tDHD
0
-
-
us
SCL / SDA Rise Time
tR
-
-
0.12
us
SCL / SDA Fall Time
tF
-
-
0.12
us

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Rev. 1.0
PANEL HM-LC43R15J
Input equivalent impedance of SDA / SCL pin
Note 17. Write Protection
Mode selection
WP
Note
L or OPEN
Protection
H
Writable
Input equivalent impedance of WP pin

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Rev. 1.0
PANEL HM-LC43R15J
5.3 Input Data Format
5.3.1 V by one color data mapping
Mode
Packer input & Unpacker output
30bpp RGB / YCbCr444 (10bit)
4Byte Mode
Byte0
D [0]
R/Cr [2]
D [1]
R/Cr [3]
D [2]
R/Cr [4]
D [3]
R/Cr [5]
D [4]
R/Cr [6]
D [5]
R/Cr [7]
D [6]
R/Cr [8]
D [7]
R/Cr [9]
Byte1
D [8]
G/Y [2]
D [9]
G/Y [3]
D [10]
G/Y [4]
D [11]
G/Y [5]
D [12]
G/Y [6]
D [13]
G/Y [7]
D [14]
G/Y [8]
D [15]
G/Y [9]
Byte2
D [16]
B/Cb [2]
D [17]
B/Cb [3]
D [18]
B/Cb [4]
D [19]
B/Cb [5]
D [20]
B/Cb [6]
D [21]
B/Cb [7]
D [22]
B/Cb [8]
D [23]
B/Cb [9]
Byte3
D [24]
-
D [25]
-
D [26]
B/Cb [0]
D [27]
B/Cb [1]
D [28]
G/Y [0]
D [29]
G/Y [1]
D [30]
R/Cr [0]
D [31]
R/Cr [1]

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Rev. 1.0
PANEL HM-LC43R15J
5.3.2 Color Input Data Reference
The brightness of each primary color(red, green and blue) is based on the 10 bit(8 bit + FRC)
gray scale data input for the color; the higher the binary input, the brighter the color. The table
below provides a reference for color versus data input.
COLOR DATA REFERENCE
Color
Input Color Data
RED
GRREN
BLUE
MSB LSB
MSB LSB
MSB LSB
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
G
9
G
8
G
7
G
6
G
5
G
4
G
3
G
2
G
1
G
0
B
9
G
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
Basic
Colors
Black
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Red(1023)
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Green(1023)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
Blue(1023)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Cyan
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Magenta
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Yellow
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
White
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RED
Red(000)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Red(001)
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
---
Red(1022)
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Red(1023)
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GREE
N
GREEN(000
)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GREEN(001
)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
---
GREEN
(1022)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
GREEN
(1023)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
BLUE
BLUE(000)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLUE (001)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
---
BLUE
(1022)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
BLUE
(1023)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

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PANEL HM-LC43R15J
6. Signal Timing Specification
6.1 Input Timing
This is the signal timing required at the input of the user connector. All of the interface signal timing
should be satisfied with the following specifications for its proper operation.
Timing Table (DE only Mode)
For 2D application
Signal
Item
Symbol
Value
Unit
Min.
Typ.
Max.
Vertical Section
Period
Tv
2200
2250
2715
Th
Active
Tdisp (V)
2160
Blanking
Tblk (V)
40
90
555
Th
Horizontal Section
Period
Th
530
550
600
Tclk
Active
Tdisp (V)
480
Blanking
Tblk (V)
50
70
120
Tclk
Clock
Frequency
Fclk=1/Tclk
66
74.25
77
MHz
Vertical Frequency
Frequency
Fv
47
60
63
Hz
Horizontal Frequency
Frequency
Fh
120
135
139.2
KHz

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Rev. 1.0
PANEL HM-LC43R15J
The timing diagrams of the input timing
(Lane 1~8 V-by one data : 1, 2, 3, 4, 1921, 1922, 1923, 1924)

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PANEL HM-LC43R15J
6. 2 V by one spec
Item
Symbol
Value
Unit
Note
Min.
Typ.
Max.
V-by-one
Interface
VRXINP / N input each bit Period
TRRIP (UI)
310
-
379
ps
10bit
Note 17
Receiver Clock : Spread Spectrum
Modulation range
Fclk_ss
Fclk
-0.5%
-
Fclk
+0.5%
MHz
Note 18
Receiver Clock : Spread Spectrum
Modulation frequency
Fss
30
KHz
Note 18
CDR training pattern time
TLOCK
-
500
-
us
Note 17
Latency from LOCKN ‘HIGH’ to
clock training pattern
L1
0
-
-
us
Note 17
Latency from LOCKN ‘LOW’ to
normal 8b10b data
L2
-
-
70
us
Note 17
CML Differential Input High
Threshold
VRTH
+50
-
-
mVDC
CML Differential Input Low
Threshold
VRTL
-
-
-50
mVDC
CML Common mode Bias Voltage
VRCT
0.8
0.9
1.0
VDC
Intra-pair skew
TINTRA
-
-
0.3
UI
Note 19
Inter-pair skew
TINTER
-
-
5
UI
Note 20
Eye diagram at receiver
A_X
-
0.25
-
UI
Note 21
A_Y
-
0
-
mV
B_X
-
0.3
-
UI
B_Y
-
50
-
mV
C_X
-
0.7
-
UI
C_Y
-
50
-
mV
D_X
0.75
-
UI
D_Y
0
-
mV
E_X
0.7
-
UI
E_Y
-50
-
mV
F_X
0.3
-
UI
F_Y
-50
-
mV

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Rev. 1.0
PANEL HM-LC43R15J
Note 17. V-by-one Signal diagram
Note 18. Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures.
Note 19. V-by-one Intra-pair Skew

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Rev. 1.0
PANEL HM-LC43R15J
Note 20. V-by-one Inter-pair Skew
Note 21. Eye diagram at receiver
Eye Mask
Example of Eye diagram