HOLT AN-6130PCIe MIL-STD 1553 User manual

HOLT INTEGRATED CIRCUITS
AN-6130PCIe Rev. B 1
March 4, 2015
AN-6130PCIe
MIL-STD 1553 PCIe Card
Evaluation Card Users Guide
Introduction:
The Holt HI-6130 PCIe MIL-STD-1553 is a PC interface card designed to interface the Holt HI-6130 MIL-
STD-1553 multi-terminal to a single lane x1, x4/8 or x16 PCI Express (PCIe) 1.1 slot on a PC running
Windows 7. The HI-6130 is a single supply 3.3V rail BC/MT/RT1/RT2 Multi-Terminal device for MIL-STD-
1553 dual redundant bus communications. The card is bundled with the Holt high-level API software
library and two demo programs. The two demo projects provided on the included CD-ROM demonstrate
the basic features of the HI-6130 and the Holt API software library. The demo card and software can be
used as starting point for any new custom design.

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Evaluation Kit Contents
•This Application Note, AN-6130PCIe User’s Guide.
•Holt API library software and user manual.
•ANSI C HI-6130PCIe test demo project.
•ANSI C HI-6130 PCIe API demo project.
•9 Pin-D to MIL-STD-1553 BNC breakout cable.
•Full size PCI card optional bracket.
•CPLD Verilog project files.
•CD-ROM containing supporting documentation and software.
Topics:
•Introduction
•Quick Start Guide
•Hardware
•Programming Reference
•Software
•Customization
•Summary
•Schematics and BOM
Board Default Setup:
Set SW2 position 6 set to Off (up) position. This sets the HI-6130 input pin AUTOEN low which is
required for the demos to work properly. See the picture below.
JP6 and JP7 will be open. Optionally jumper these when necessary to have the negative side of the bus
transformers (nXBUS) grounded for testing purposes.
JP2-JP5 are not used or installed. See the PLX PEX8311 PCI Express documentation for usage.

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Quick Start Guide
This board communicates with a PC using a PCIe bridge chip made by PLX Technology (plxtech.com).
Install the PLX SDK by following the instructions in the Software section “PLX SDK installation” of this
guide on page 13. A prebuilt Windows 7 compatible executable demo program is included on the CD-
ROM in the folder “Holt HI-6130 PCIe Demo”. Copy this folder to the desktop.
Confirm the factory default DIP switch settings: (logic-0 is down, logic-1 is up)
RT1 address = 3. SW3 1-3 set Off, 4-6 set On.
RT2 address = 4. SW4 all set On except position 4 which is set Off.
SW2 Positions 1-5 are user defined. These may be used by the demo program in future releases.
Default DIP switch settings
Metal brackets are provided for both full-height and low profile PCIe cards. Use the correct bracket for
your PC slot.
With the PC unpowered, plug the card into a PCIe x1, x4/8 or x16 card slot and fasten the card with the
bracket screw so the card is secure. After powering up the PC, Windows automatically detects the new
hardware and uses the driver installed by the PLX SDK installation.
After the driver is installed, launch the PCIe6130Test application (.exe) by double clicking on the file
located in the Holt HI-6130 Demo folder (on the desktop). A menu will be displayed showing sets of
numbers 1 though x. The Holt card typically appears as the first item #1 with “9056 10b5” [b:xx s:xx
f:xx]. Enter “1” and press Enter.

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The main menu of commands will appear below.
Press “1” to perform a HI-6130 register memory dump. This displays all the HI-6130 system registers
from 0x0000 to 0x0047 which initialize to default values after a master reset. Default values are
specified in the HI-6130 data sheet. Notice the word at address 0x0001 contains 0x8000. This is the
Master Status and Reset Register (0x0001) in the HI-6130. The MSB bit-15 high indicates the HI-6130
READY is high which means the device is ready for the host to access the memory and registers in the
device. See the HI-6130 data sheet for more details on registers and status bit definitions.
The HI-6130 bus controller is initialized with several predefined messages.
Press “5” to command the BC to transmit three (commands) messages to RT address 3. Message 1 is a
Receive command with 32 data words to subaddress SA1 on Bus A, Message 2 is a Transmit command
with 32 data words to SA1 on Bus B and Message 3 is a Receive command with 32 data words to SA1 on
Bus A.

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If a separate RT terminal or other RT-capable MIL STD 1553 test equipment is set for RT address 3 and
connected to the bus through a suitable bus coupler, the message responses can be monitored. The
program outputs BC data blocks, BC instruction lists and HI-6130 system registers to the console after
each transmission. To view the transmissions on an oscilloscope, trigger rising edge on the ACTIVE test
point on the top left side of the card; put another scope probe on the ABBUS test point. Use a small clip
lead to bring this signal up to make it accessible to the scope probe. If no external RT or test equipment
is connected to the bus then use a 70 ohm termination resistor on the cable output or the signal will be
distorted when viewed with the oscilloscope.
Press”8” to command the BC to transmit three messages repeatedly to RT address = 3. Messages 1 and
3 are routed to the Bus A connector and message 2 is routed to the Bus B connector.
During transmissions LEDs 10 and 11 on the top edge of the card count in a binary fashion according to
the message sent. Two other LEDs flash when the HI-6130 is read or written by the program to provide a
visual aid during software development. LED 8 flashes when a read occurs and LED 9 flashes when a
write occurs.
Press “q” to quit.
This is the end of the Quick Start Guide section.

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Hardware
The Holt HI-6130 PCIe interface card consists of three main IC components shown below in the Block
Diagram. The PEX 8311 is a PCI Express-to-Generic Local Bus bridge and provides the interface between
the PCIe slot and the local bus (LB). A CPLD translates the LB signals into CSn, RDn and WRn strobe
signals for the HI-6130 timings. The CPLD also provides other GPIO and glue logic. A shared single
50MHz oscillator module provides the clock for the PEX8311 local bus, CPLD and the HI-6130. The HI-
6130 must be clocked at 50MHz.
HI-6130 PCIe Card Block Diagram

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The PEX8300 is used in “EndPoint” mode which operates in slave mode relative to the host PC. A full
SDK and RDK reference board design including drivers, documentation and demo software is available
from PLX. This PLX RDK was used as the basis for the Holt card. An EEPROM (U6) contains configuration
data which the PEX8311 latches in at power up to configure the LB for the target hardware base address
space, data bus width, and the number of wait states. The data bus width is configured for 16-bits to
match the width of the HI-6130. A second EEPROM is also connected to the PEX8311 for optional
parameters to enable special configurations mainly for the PCIe side. A second EEPROM (U2) is installed
for optional PCIe bus configuration but it may or may not be used. PLX recommends installing this
EEPROM just in case of future needs. These EEPROMs can be examined and programmed using the
PlxMon utility. The PLX utility program “PlxMon.exe” is located in the\Plx\ …\Bin folder after the SDK is
installed. Information on how to use this utility is located in the PlxSdkUsersManual document in section
4 “PLX Debug Utilities”. Holt uses this utility to program the two EEPROMs.
The HI-6130 uses a 16-bit data bus, 16-bit address bus and three more lines to select the device during
reads and writes. The CS0n, WRn and RDn are decoded by the CPLD and routed to the HI-6130. Only the
upper address lines (LA31:LA26) of the LB are decoded by the CPLD for the chip selects. The LB address
and data lines connect directly from the PEX8311 to the HI-6130. In addition to these lines are several
dedicated inputs and outputs listed below going to the HI-6130 from the CPLD. For a complete
description of the HI-6130, refer to the Holt data sheet and application notes that are included on the
CD-ROM.
The functions provided by the CPLD:
•HI-6130 interface signals CSn, RDn and WRn meeting the HI-6130 timings.
•HI-6130 write and read access LED’s.
•Output latches with read-back for control signals to the HI-6130 and LEDs.
•HI-6130 status and DIP switch inputs.
•Interrupt source pin. The CPLD logically OR’s the HI-6130 IRQ, RT1MC8 and RT2MC8 signals into
a single signal that is connected to the interrupt pin of the PLX8311. See the software section for
information how PLX API’s handles interrupts. PLX includes a demo project “LocalToPciInt” to
demonstrate how interrupts are handled. The technique used in “LocalToPciInt” was used in the
Holt demos.

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Programming Reference (LB decoded addresses)
HI-6130 chip select (R/W) – 0x2000-0000 – 0x2000-07FFF (32K Words).
Main Output Control Latches (R/W) – 0x2400-0000
BIT 15 14 13 12 11 10 9 8
FIELD
TEST
EECOPY
“K3”
LED2
LED1
RT2ENA
RT1ENA
BCENA
RESET 0 0 0 1 0 0 0 0
BIT
7
6
5
4
3
2
1
0
FIELD MR MTRUN TXINHA TXINHB RAMDEC TP31 ACKIRQ BCTRING
RESET 0 0 1 1 0 0 0 0
DO BCTRIG HI-6130 input. Rising edge triggers the BC to execute next Opcode instruction.
Usually used to start BC transmissions.
D1 ACKIRQ HI-6130 input.
D2 TP31 CPLD spare pin.
D3 RAMEDC HI-6130 Error detection/correction input. Set Low for this program.
D4 TXINHB HI-6130 Bus B inhibit input.
D5 TXINHA HI-6130 Bus A inhibit input.
D6 MTRUN HI-6130 MT enable input.
D7 /MR HI-6130 Master Reset input.
D8 BCENA HI-6130 BC enable input.
D9 RT1ENA HI-6130 RT1 enable input.
D10 RT2ENA HI-6130 RT2 enable input.
D11 /LED1 General purpose LED (LED10 on board). On (low) at power up.
D12
/LED2
General purpose LED (LED11 on board). Off (high) at power up.
D13
“K3”
Not used but brought out to a pad on the PCB from the CPLD.
D14
EECOPY
HI-6130 EECOPY input.
D15
TEST
HI-6130 TEST input. Must be set Low for normal operation. See data sheet for Test
Mode details.

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Status Inputs (R only) - 0x2800-0000
BIT
15
14
13
12
11
10
9
8
FIELD “A4” SW2-5 SW2-4 SW2-3 SW2-2 SW2-1 “D5” AUTOEN
BIT 7 6 5 4 3 2 1 0
FIELD N/A IRQ RT2MC8 RT1MC8 WAIT READY MTPKTRDY ACTIVE
DO
ACTIVE
HI-6130 outputs a high when the BC or RT is processing a 1553 message.
D1
MTPKTRDY
HI-6130 output. Monitor Packet active high when message complete.
D2
READY
HI-6130 output. Set high when the host can configure the device.
D3
WAIT
HI-6130 output. Not used by this design.
D4
/RT1MC8
HI-6130 output. Outputs a pulse when a Mode Code 8 is received.
D5 /RT2MC8 HI-6130 output. Outputs a pulse when a Mode Code 8 is received.
D6 /IRQ (6130) HI-6130 interrupt output.
D7 N/A Not defined.
D8 AUTOEN Set by the SW2 DIP switch 6. Input to HI-6130 for auto initialization from
EEPROM.
D9
“D5”
Not used by connected to a pad on the PCB from “D5” to the CPLD.
D10
SW2-1
DIP SWITCH user defined.
D11
SW2-2
DIP SWITCH user defined.
D12 SW2-3 DIP SWITCH user defined.
D13 SW2-4 DIP SWITCH user defined.
D14 SW2-5 DIP SWITCH user defined.
D15 “A4” Not used but is connected to a pad from “A4” to the CPLD.
Secondary Output Latches R/W – 0x2C00-0000
BIT 15-D5 4 3 2 1 0
FIELD
N/A
RT2LOCK
RT2SSF
MTSTOFF
RT1LOCK
RT1SSF
RESET N/A 0 0 0 0 0
DO
RT1SSF
RT1 Subsystem Fail input.
D1
RT1LOCK
RT1 RT address input lock input.
D2
MTSTOFF
HI-6130 memory test disable. Set low by internal pull-down resistor.
D3
RT2SSF
RT2 Subsystem Fail input.
D4 RT2LOCK RT2 RT address input lock input.
D5:D15 N/A Not defined.

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The CPLD is a Lattice LCMX01200 256 BGA device and is programmed through a JTAG port on J2. The
Verilog source code listing is included in this document and the actual Verilog source and constraint files
are included in the Lattice “Diamond” tool project included on the CD-ROM. The CPLD block diagram is
shown below. The CPLD has an internal reset and RC clock generator which is used in Verilog design.
Up to 16 wait states can be programmed in the LB timing controlled by the PEX8311 for the HI-6130,
output latches and input buffers in the CPLD. The value of 14 (0xD) is programmed in the LB EEPROM
(U6). At 50MHz the access time is 1+14 or 1/50MHz * 15 = 300ns. This meets the worst case 240ns
timing requirement of the HI-6130 for non-sequential read cycles with 60ns of margin. The LB BLASTn
signal is used by the CPLD to time when to de-assert the CSn, RWn or WRn signals to the HI-6130 and
the internal latches and input buffers. The ADSn signal from the LB is used by the CPLD to start the bus
cycle. A faster access time could have been used for the GPIO but was kept the same to simplify the
design. See the PEX8311 data book for the LB signal descriptions and timings.
A large portion of the CPLD is unused with sufficient room for custom expansion. A Lattice USB
programming cable PN: PN-USBN-2A is required to reprogram the CPLD but is NOT provided by Holt.
This is only needed if the end user wishes to alter the Verilog code and reprogram the CPLD. Using the
Lattice Diamond CPLD development software is beyond the scope of this document but many tutorials
are built into Lattice Diamond software which is available for download from their website. When the
board powers up, only LED10 is On. This is a convenient way to determine if the CPLD has been
programmed.
The next page shows a block diagram of the CPLD

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CPLD Functional Block Diagram

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HI-6130 Functional Block Diagram
RT1
Message
Processor
BC
Message
Processor
MT
Message
Processor
RT2
Message
Processor
BusB
Manchester
Encoder
BusB
Manchester
Decoder
BusA
Manchester
Encoder
BusA
Manchester
Decoder
Reset&
Initialization
Logic
Memory
and
Register
Access
Control
Address
Data
Control
Discrete
Signal
Inputs
Configuration
Option
Logic
Test
Logic
BUS
BUSB
BUSB
TXINHB
TXINHA
VCCP
MCLK
TTCLK
INTERNAL
CLOCKS
GND
VCC
LOGIC POWER
TRANSCEIVER
POWER
TEST
MODE
RT2SSF
ACKIRQ
RT1SSF
MR
RT2A4-0
AUTOEN
RT2AP
EECOPY
BENDI
RAMEDC
RT1LOCK
MTTCLK
RT1A4-0
RT1AP
MTSTOFF
RT2LOCK
RT1ENA
RT2ENA
BCENA
MTENA
Host Bus
Interface
HI-6130
Only
IRQ
MTPKRDY
READY
ACTIVE
CE
R/ orWWE
STR OEor
A0 /LB
WAIT or WAIT
D15:0
A15:1
BTYPE
BWID
WPOL
RT1MC8
RT2MC8
Discrete
Signal
Outputs
Host
Interface
SPI
HI-6131
Only
SCK
SI
SO
CE
Address
Data
Control
Address
Data
Control
StaticRAM
and
Registers
Address
Data
Control
Serial
Peripheral
Interface
(SPI)to
EEPROM
OPTIONAL
SERIAL EEPROM
(AUTO-CONFIG)
ECS
ESCK
MOSI
MISO
Address
Data
Control
Tx1553 Words
Rx 1553 Words
Address&Control
Words
BCTRIG
BUS
BUSA
BUSA
HI-6130 Only
HI-6131 Only

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Software
Two Holt demo programs are provided on the CD-ROM. PCIe6130 test contains a menu of commands to
demonstrate reading and writing to the latched I/O’s, read and write to HI-6130 memory space and
initialize the HI-6130 for BC transmissions. The simple BC demo periodically transmits 3 types of
messages. This demo was demonstrated in the Quick Start Guide section.
The HI-6130 API demo is more complex. The main purpose of this demo is to demonstrate Holt’s API
library. This demo program demonstrates how to use Holt’s API library to initialize the HI-6130 for BC,
RT or MT operations. Both demo projects are built using Microsoft Visual Studio 2012. For other
compilers, the user needs to port the software project. All the API’s and low-level drivers supporting the
HI-6130 and GPIOs are contained in module HI6130.c with accompanying header file HI6130.h.
To rebuild these projects the following three items are needed:
•Holt demo projects contained on the CD-ROM.
•Microsoft Visual Studio 2012. (Not Provided)
•PLX SDK 7.00. (On PLX website)
The 4 layer demo software is shown below.
PLX SDK installation
To modify the demo programs the PLX SDK must first be installed so that the Holt projects can be added
to the SDK samples folder. To develop custom software applications for this card, the SDK from PLX is
required. Download the SDK from the link below. PLX requires user registration to download their SDK
by filling out their online registration and obtaining a login and password. Holt is not authorized to
provide the PLX SDK package directly to customers. At the time this document was written, Windows 7
is supported and future OS versions including Linux are planned. After the SDK is installed, the PC may
require a few moments or a reboot for the new drivers to take effect which are also installed by the SDK
installation.
http://www.plxtech.com/products/sdk/pde

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The PLX SDK installs a “Plx” folder on the root drive with several sub folders. The “PlxSdkUserManual” is
located in the C:\Plx\PlxSdk\Documentation folder. This is an important document for information on
installation, drivers, utilities and PLX API’s for the PEX8311 PCIe interface.
Follow these steps to install the demo project into the PLX SDK Samples folder:
Install the PLX SDK.
Locate the zipped Holt demo project “PCIe 6130 test.zip” on the CD-ROM and unzip this project folder
into the C:\Plx\PlxSdk\Samples folder. Use this directory structure because some PLX files reference
other files in these directories.
Launch Microsoft Visual Studio and open the project using Open Project from the File menu, or from the
Open Project short cut that may appear on the Start Page. Alternately, double-click on the PCIe6130Test
project file in the PCIe6130 test project folder.
1. The Solution Explorer with the source files is shown on the left side. If this is not seen, then open the
Solution Explorer from the View menu at the top.
2. To run the program with the Visual Studio debugger, verify that the “Debug” configuration is
selected at the top. Build the solution from the Build menu using Build Solution or just press F7.
There should be no errors produced in the Output window.
3. Press the green arrow labeled “Local Windows Debugger” to run the program. The console output
should be displayed like the one shown in the Quick Start Guide.
4. To build an executable version of the demo code, select the “Release” configuration instead of
“Debug” and rebuild the project. The executable file is put into the “Release” sub folder of the
project folder. Use the “Debug” configuration for software development so that source level
debugging features are operational.
Note: When the SDK is installed a driver is installed for the PEX8311.

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To understand the software and operation of the card for any development work or modifications, it is
important to read the following documents.
•PLX SDK Users Manual which is installed when the SDK is installed.
•PLX PEX8311 RDK Hardware Reference Manual and the PLX PEX8311 data book. Latest versions
are available from the PLX website. These are not included in the SDK.
•Holt HI-6130 data sheet. Provided on the CD-ROM.
•Holt high-level API software users manual. Provided on the CD-ROM.
Other useful documents:
•AN-6130_x.pdf
•AN-6130DG_x.pdf
•AN-550.pdf (for IC capacitor decoupling and transformer PCB routing)

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PLX API’s
PLX API’s use a unique input parameter (BAR) to specify which LB memory space to read and write from.
BAR stands for Base Address Register. BAR 0 and BAR 1 are reserved for the upstream PCIe. BAR 2 and
BAR 3 are used to provide separate memory spaces on the LB side. Bar 2 uses Space 0 and BAR 3 uses
Space 1. The Space 0 and Space 1 PEX8311 registers are loaded with the desired starting BAR addresses
at power up from the contents of the U6 EEPROM. Space 0 is reserved exclusively for the HI-6130 64KB
memory space and is set to starting address 0x2000-0000. Space 1 is shared and modified on-the-fly in
the API function calls to read/write to the output latches and reading the input status buffers. The
latches are used to set the state of various inputs to the HI-6130 and the inputs are used to read HI-6130
status and DIP switches. The Holt demo code includes several functions to read and write to the HI-6130
memory space, latches and input status buffers. The API functions are located in HI6130.c. These
functions use a PLX API to access the LB with either “PlxPci_PciBarSpaceRead(…)” or
“PlxPci_PciBarSpaceWrite(…). One of the input parameters to these API’s is “bOffsetAsLocalAddr” this
parameter controls how the API uses the U32 offset address. If “OffsetAsLocalAddr” is FALSE the input
address is an offset address from the Space x value. If this parameter is TRUE the input address is the full
address. See the PLX API user’s manual for descriptions and usage of the API’s, BAR spaces and other
input parameters associated with the PEX8311 and SDK API’s.
Device BAR Space Address Notes
HI-6130 2 0 0x2000-0000 32K word range
Output Latches 3 1 0x2400-0000 First location used
Inputs
3
1
0x2800-0000
First location used
Output Latches-2
3
1
0x2C00-0000
First location used
The U6 EEPROM contains configuration data the PEX8311 uses to configure the LB at power up. The LB
is configured for a 16-bit data bus, 14 wait states, Space0 and Space1 starting addresses/ranges, and
disables the TA/Ready input. The PCI PLX sub-ID 3566 is also programmed into this EEPROM. This sub-ID
is assigned by PLX exclusively for the Holt demo board.
The PlxMon utility is launched from the Windows start menu or by double-clicking on the application
found in the /Plx/…/Bin folder. The PlxMon utility opening screen is shown below:

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Select the Holt PCIe card from the Command menu (or press the green icon button on the left) and
select the device with Dev ID = 9056 and Ven ID = 10B5. The PEX8311 consists internally of a PEX8111
and a PCI9056.

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After selecting the Holt card, select the LCR button (top left) to see the Main Control Registers. Changes
to the LB configuration can be dynamically changed by entering new values from this menu. Alternately,
press the EEPROM button to see the 9056 EEPROM values shown below. Notice the Vendor ID is 10B5.
This is PLX’s vendor ID and must be used with the sub-ID 3566 that is assigned to Holt. A new end
product would require a unique Vendor ID from PCI-SIG (obtained by becoming a PCI-SIG member) or a
sub-ID obtained from PLX. For detailed information on these parameters and the PLX API’s refer to the
PLX SDK user’s guide and data sheet on the PEX8311. For the Holt card, there is no need to alter any of
these values.
On the bottom of the PlxMon screen is a console window where a menu of commands allow reading
and writing to LB memory spaces. These are useful during initial hardware checkout to confirm LB
configurations. Pressing “?” followed by a Return in this window lists a Help page of the commands. The
commands are also documented in the PLX API user manual and some examples are provided in the PLX
PEX8311 RDK Hardware Reference Manual.

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Holt HI-6130 PCIe API Demo using Holt’s high-level API library.
The HI-6130 PCie API demo program demonstrates Holt’s high-level API software library. The demo
consists of menu commands prompted on the console for demonstrating the BC, RT1, RT2, SMT and
IMT.
Copy the zipped project folder from the CD-ROM to the desktop and unzip the folder there. Copy the
unzipped project folder to the PLX SDK samples folder: Plx\PlxSdk\Samples. The _HI-6130 PCIe API demo
will typically have a version number at the end of the folder name to indicated program revision.
The folders should appear like the following screen shot. The Holt demo project folders are added in the
PLX Samples folder. Many of the PLX API examples used in Dslave and LocalToPciInt were used in the
Holt projects. It’s a good idea to review these two projects when first becoming familiar with the PLX
API’s. These PLX projects do not run on the Holt PCIe card because the LB memory spaces are defined
differently.
Plx\PlxSdk\Samples folder
Launch the program by either double-clicking the executable application “PCIeHolt” contained in the
Visual Studio project “Release” sub folder or launch Visual Studio and open the project to run the
program in debug mode. To run the project in debug mode make sure the debug configuration is
selected at the top. Sometimes it may be necessary to perform a project clean by selecting “Clean
PCIe6130Holt” from the BUILD pull down menu. After rebuilding the project, some warnings may appear
in the Output window which can be ignored but there should be no critical errors preventing the
debugger from running the project.
A menu will be displayed showing sets of numbers 1 though x. The Holt card typically appears as the first
item, #1 with “9056 10b5” [b:xx s:xx f:xx]. Enter “1” and press Enter.

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The main menu will appear below.
Press D to display the HI-6130 system registers with labels followed by the same registers values
formatted by beginning and end addressed rows followed by eight register values.