i-See IGEP v2 Quick user guide
Document : MAN-PR-IGEP0020-RCx
Revision: 2.0
Date: Febru ar y 6, 2013
IGEP TM v2
HARDWARE REFERENCE
MANUAL
IGEPTM v2 Hardware Reference Manual
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DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx
2
Table of contents
Table of contents .................................................................................................................2
1 COPYRIGHT NOTICE ...................................................................................................4
2 WARRANTY ...............................................................................................................4
3 ORDERING INFORMATION .........................................................................................5
4 OVERVIEW ................................................................................................................6
4.1 ABOUT THIS MANUAL ............................................................................................6
4.2 IGEP™v2 DESCRIPTION ...........................................................................................6
4.3 IGEPTM v2 FEATURES ..............................................................................................8
4.4 IGEP™ v2 BLOCK DIAGRAM ...................................................................................11
4.5 GENERAL VIEW ....................................................................................................12
5 ON-BOARD DEVICES & INTERFACES ..........................................................................14
5.1 SUMMARY ..........................................................................................................14
5.2 IGEP™ v2 CONNECTORS MAP ................................................................................15
5.3 OMAP PROCESSOR ..............................................................................................16
5.4 MEMORY ............................................................................................................16
5.5 POWER MANAGEMENT .......................................................................................16
5.6 WIFI/BLUETOOTH INTERFACE ...............................................................................17
5.6.1 BLOCK DIAGRAM ..........................................................................................17
5.6.2 INTERFACES .................................................................................................17
5.6.3 POWER-ON RESET SEQUENCE FOR WLAN ......................................................18
5.6.4 WLAN RESET/PDN PINS.................................................................................19
5.6.5 BLUETOOTH RESET PINS ...............................................................................19
5.6.6 PCM INTERFACE ...........................................................................................20
5.6.7 IGEP™ v2 ANTENNAS (INTERNAL/EXTERNAL - UD11, JD21, JD22) .....................20
5.7 MAIN 5Vdc POWER: J200 ....................................................................................24
5.8 JTAG DEBUG: J400 ..............................................................................................24
5.9 RS485: J940 ........................................................................................................26
5.10 SERIAL PORT DEBUG (+ EXTRA RS232) J960 ...........................................................28
5.10.1 DEBUG CABLE MODIFICATIONS (ONLY REV C) ................................................29
5.10.2 NEW FEATURES ON REV C .............................................................................30
5.10.3 HOW TO USE UART 1 ....................................................................................31
5.11 KEYBOARD MATRIX 4x4: J970 ...............................................................................32
5.12 TFT INTERFACE CONNECTORS: JA41 & JA42...........................................................34
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5.12.1 CONNECTOR JA41 ........................................................................................34
5.12.2 CONNECTOR JA42 ........................................................................................37
5.12.3 CONNECTORs JA41-JA42 COUNTERPARTs ......................................................38
5.13 ANALOG TO DIGITAL CONVERTER: JC20 & JC21 .....................................................39
5.14 CAMERA INTERFACE: JC30....................................................................................41
5.15 S-VIDEO SIGNALS: TP400 & TP401 ........................................................................43
5.16 RTC BACKUP BATTERY..........................................................................................44
5.17 USB 2.0 OTG: J830 ...............................................................................................47
5.18 USB 2.0 HOST: J800..............................................................................................48
5.19 ETHERNET: JB01 ..................................................................................................49
5.20 AUDIO: J650 & J640 .............................................................................................50
5.21 DVI-D INTERFACE: JA01 ........................................................................................53
5.22 MICRO-SD: J900...................................................................................................54
5.23 LED INDICATORS: D240 & D440 ............................................................................54
6 EXPANSION CONNECTOR J990: GPIO ........................................................................55
6.1 PINOUT TABLE OF EXPANSION CONNECTOR..........................................................58
7 EXPANDING IGEP™ v2 CAPABILITIES ..........................................................................59
7.1 IGEP™ v2 EXPANSION BOARD ................................................................................59
7.2 IGEP™ RADAR LAMBDA.........................................................................................60
8 MECHANICAL SPECIFICATIONS .................................................................................61
9 ELECTRICAL CHARACTERISTICS .................................................................................62
10 LIST OF TABLES........................................................................................................64
11 LIST OF FIGURES ......................................................................................................64
12 KNOWN ISSUES .......................................................................................................66
13 TROUBLESHOOTING ................................................................................................66
14 CHANGE HISTORY ....................................................................................................66
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1COPYRIGHT NOTICE
This document is copyrighted, 2011, by ISEE 2007 SL. All rights are reserved. ISEE reserves the
right to make improvements to the products described in this manual at any time without
notice. No part of this manual may be reproduced, copied, translated or transmitted in any
form or by any means without the prior written permission of the original manufacturer.
Information provided in this manual is intended to be accurate and reliable. However, the
original manufacturer assumes no responsibility for its use, nor for any infringements upon the
rights of third parties which may result from its use.
2WARRANTY
THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND
IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING
ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods.
Further, the user indemnifies ISEE 2007 SL from all claims arising from the handling or use of
the goods. Due to the open construction of theproduct,itistheuser’sresponsibilitytotake
any and all appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE
LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
ISEE 2007 SL currently deals with a variety of customers for products, and therefore our
arrangement with the user is not exclusive. ISEE assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read specifically, the Warnings and Restrictions notice in this manual prior to handling
the product. This notice contains important safety information about temperatures and
voltages. For additional information on IGEP™ environmental and/or safety programs, please
contact with ISEE (support@iseebcn.com).
No license is granted under any patent right or other intellectual property right of ISEE
covering or relating to any machine, process, or combination in which such ISEE products or
services might be or are used.
NOTE: It could be found a detailed warranty and sales conditions of IGEP™ on ISEE website:
http://www.isee.biz
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3ORDERING INFORMATION
IGEP™ Device
Orderable #PN
Marking
IGEP™ v2
IGEP0020-RCx
Datamatrixcodelabelwith“IGEP0020-RCx”
Table 1 Ordering information
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4OVERVIEW
4.1 ABOUT THIS MANUAL
This manual describes IGEP™ v2 hardware features. IGEP™ v2 is an IGEP™ technol ogy device
from ISEE. You can find additional information at our website www.iseebcn.com
The “4 OVERVIEW”chapter describes general features of this base board and show the block
diagram. The “5 ON-BOARD DEVICES & INTERFACES” chapter describes in more detail each
device and interface connectors included on this product. “6 EXPANSION CONNECTOR J990:
GPIO”chapter describes in detail the function of each pin of the expansion connector included
on the board. 8 MECHANICAL SPECIFICATIONS chapter describes the mechanical
characteristics of the product and finally chapter 9 ELECTRICAL CHARACTERISTICS show a table
with the electrical specifications of the product.
At the end of this document you will find a list of tables, figures and change log. You will find
theseelementsinchapters:“10 LIST OF TABLES”, “11 LIST OF FIGURES”, ”12 KNOWN ISSUES”,
”13 TROUBLESHOOTING”and“14 CHANGE HISTORY”.
4.2 IGEP™ v2 DESCRIPTION
IGEP™ v2 is an embedded processor development board based on Texas Instruments
OMAP3530/DM3730 processor.
Texas Instruments OMAP3530/DM3730 processor @720MHz/1GHz
oDSP TMS320DM-C64+ 500 MHz / 800 MHz
oNEON SIMD Coprocessor
oVideo Acceleration
oCamera Interface
RAM 512 MBytes LPDDR SDRAM – 200 MHz
NAND Flash 512 Mbytes
On board micro-SD socket
Debug RS232 & JTAG
Connection to single +5V power supply.
Designed for industrial and commercial purposes.
USB OTG 2.0 on mini AB connector
USB HOST 2.0 HS
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Ethernet 10/100 Mb Base T on RJ45 Ports (x2)
Audio Stereo Input Jack & Output Jack
Wi-Fi & Bluetooth
DVI Video Output
TFT Interface 24 bit
Optional RTC Battery Backup for TPS65950 (Super Capacitor or Rechargeable Battery).
Optional 3Msps ADC
LED Indicators
Size: 93x64mm
Non-populated parts:
oJ400 JTAG connector
oJ990: GPIO expansion connector
oJ970: 4x4 keyboard connector
oJD22: External wifi antenna connector
oJA41 and JA42: TFT interface
oJC30: Camera interface
oUC20 3MBps ADC + JC21 Hirose connector
oSuper Capacitor or Rechargeable Battery.
Contact ISEE sales for custom assembly boards for fully previous IGEP™ v2 revision B
compatible (mechanical, electrical and logical) on IGEP0020-RCx PCBs.
IGEP™ v2 Bottom View
Bottom 3D View
Figure 1 IGEP™ v2 View
IGEP™ v2 Top View
Bottom 3D View
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4.3 IGEPTM v2 FEATURES
Feature
Specifications
ARM CPU
Texas Instruments OMAP3530/DM3730 720MHz/1GHz
L1 cache: 112 KB (DSP), 64 KB (ARM)
L2 cache: 96 KB (DSP), 256 KB (ARM)
NEON SIMD Coprocessor
DMA, Interrupt controllers, Timers
DSP
TMS320DM-C64+ 500 Mhz / 800 Mhz
2D/3D graphics
acceleration
Power VR SGX 530 (100/200 Mhz) providing 2D/3D graphics
acceleration with OpenGL ES 1.0, OpenGL ES 2.0 and OpenVG support.
Video acceleration
IVA2.2 Subsystem TMS320C64+ DSP core running at rate up to
520MHz. Supporting H.264, H.263, MPEG-4, MPEG-2, JPEG, WMV9
and additional codecs.
Camera Interface
Camera ISP processing capability to connect RAW image sensor
modules
Table 2 Processor
Figure 2 IGEP™ v2 GENERAL VIEW
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Feature
Specifications
RAM Memory
512 MBytes LPDDR SDRAM – 200 Mhz
Storage
NAND Flash 512 Mbytes
On board micro-SD socket
Table 3 Memory and Storage
Feature
Specifications
Debug
Console RS232 + JTAG Interface
Indicators
2 Bicolor USER LEDS
USB 2.0 LS/FS/HS OTG
1 Mini AB USB socket connector (dual slave and host role)
USB 2.0 HS HOST
1 Type A USB socket connector (standard USB host)
Audio stereo in/out
3.5mm standard stereo audio jack
microSD
microSD connector (SD and SDHC cards supported)
DVI video output
DVI-D using HDMI connector. (video and TS lines are available in
expansi on connector also).
Ethernet
10/100 MB BaseT (RJ45 connector with led link/activity)
Expansion connector
Power 5V and 1.8V, UART, McBSP, McSPI, I2C, GPIO, RS485 with
transceiver, Keyboard.
Table 4 On-board connectors and devices
Feature
Specifications
Wifi
IEEE 802.11b/g 2,4GHz
Bluetooth
2.0
Antenna WiFi/Bluetooth
1 shared internal antenna (integrated on PCB), optional external
antenna. 1 x HIROSE UL connector
Table 5 Wireless connectivity
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Feature
Specifications
Power
5Vcc / 1A (Without USB) – 5Vcc / 1.3A (With USB)
3.5mm socket connector for wall plug or JST Connector
Power from expansion
connectors
Supply Voltage from 5V and 1.8V
Power Management
TPS65950
Table 6 Power
Feature
Specifications
Temperature Range
Commercial ( 0 to 70 Cº) and Industrial range (-40 to +85 Cº Degrees)
are available (Contact ISEE sales)
PCB size
93 x 64 x 1.6 mm
Table 7 Mechanical and environmental
WARNING: IGEP™ v2 BOARD CAN ONLY BE POWERED WITH +5Vdc POWER
SUPPLY, OTHERWISE THE BOARD WILL BE PERMANENT DAMAGED!
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4.4 IGEP™ v2 BLOCK DIAGRAM
Figure 3 IGEP™ v2 revision C Block Diagram
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4.5 GENERAL VIEW
Figure 4 IGEP™ v2 revision C board top side components
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Figure 5 IGEP™ v2 revision C board bottom side components
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5ON-BOARD DEVICES & INTERFACES
5.1 SUMMARY
DEVICE
CONNECTOR TYPE
REF:
INTERFACE/COMMENTS
OMAP PROCESSOR
-
-
http: //focus.ti.c om
MEMORY
POP TECHNI QUE
-
NAND Flash 512 MB
512 MB LPDDR SDRAM 200 MHz
POWER Management
p/n: TPS65950
-
http: //focus.ti.c om
WIFI 802.11b/g
SMD COAXIAL
p/n: U.FL-R-SMT-1
JD22(*)
OPTIONAL EXTERNAL ANTENNA
(coaxial co nne cto r)
BLUETOOTH
SMD COAXIAL
p/n: U.FL-R-SMT-1
JD22(*)
OPTIONAL EXTERNAL ANTENNA
(coaxial co nne cto r)
MAIN POWER
p/n: RASM722BK
J200/J940(*)
+5Vdc / 1A
JTAG DEBUG
TSM-2x7; 2.54mm pi tc h
J400(*)
JTAG / DEBUG
RS485
HEADER 5 PIN 2mm pitch
p/n:S5B-PH-SM3-TB
J940(*)
UART1 + TRANSCEIVER
SERIAL DEBUG
HEADER 2x5; 2,54mm pitch
J960
UART3 + UART1 + TRANSCEIVER
KEYBOARD MATRIX
8 pin; 2.54mm pi tc h
J970(*)
Keyboard ma tri x 4x4
TFT INTERFACE
2x14pin; 1,27mm pitch
JA41(*)
DSS_DATA0:23
TFT INTERFACE-II
2x10pin; 1,27mm pitch
JA42(*)
LCD SYNC, TOUCHSCREEN, ETC
ANALOG to DIGITAL
CONVERTER (*)
JC20: U.FL-R-SMT-1;
JC21: 2pin 2,54mm pitch
JC20(*)/JC21(*)
OPTIONAL ANALOG INPUT TO
ADC.
CAMERA INTERFACE
2x14pin; 1,27mm pitch
JC30(*)
CAM_D0:D11 + others
S-VIDEO
TEST POINTS
TP400 / TP401
S-VIDEO
RTC Battery Back Up
p/n: VL1220
BT741(*)/C741(*)
OPTIONAL RTC BACKUP BATTERY
USB 2.0 OTG
USB mini AB
J830
HSUSB
USB 2.0 HOST
USB Type A socket
J800
USB1HS
ETHERNET
RJ45
JB01
GPMC_D0:D15
AUDIO
3.5mm Jack
J650 / J640
HSO/AUX
DVI-D INTERFACE
DVI-D
JA01
DSS_DATA0:23
MICRO SD
Mi cro SD Socke t
J900
MMC1_DAT0:3
LED INDICATORS
2Xbi color LED
D440/D240
GPIO26, GPIO27, GPIO28
EXPANSION
CONNECTOR
2x14pin; 2,54mm pitch
J990(*)
Mul tiplexed: GPIOs, UART2,
MMC2, McBSP3, McSPI, I2C)
Table 8 IGEP™ v2 Interface summary
(*) THESE DEVICES and/or CONNECTORS ARE NOT POPULATED BY DEFAULT
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5.2 IGEP™ v2 CONNECTORS MAP
Figure 6 IGEP™ v2 revision C CONNECTORS MAP
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5.3 OMAP PROCESSOR
IGEP™ v2 BOARD uses OMAP3530 (version ES3.1) or DM3730 as core processor and comes in a
0.4mm pitch memory POP package on it.
POP (Package on Package) is a technique where the memory, NAND and SDRAM, are mounted
on top of the OMAP3530 or DM3730. For this reason, when looking at the IGEP™ v2 BOARD,
you will not find an actual part labeled OMAP3530 or DM3730.
Figure 7 POP Package
For accurate information on this processor, revise OMAP DATA MANUAL official document
from Texas Instruments official site http://focus.ti .com
5.4 MEMORY
The memory is mounted on top of the processor as mentioned. The key function of the POP
memory is to provide:
4Gb (Giga Bits) NAND x 16 (512 Mega Bytes)
4Gb (Giga Bits) LP-DDR SDRAM x32 (512 Mega Bytes @ 200MHz)
5.5 POWER MANAGEMENT
The TPS65950 is used to provide power to the IGEP™ v2 Board with the exception of the 3.3V
regulator which is used to provide power to the DVI-D encoder and RS232 driver. In addition to
the power it also provides:
Stereo Line Audio Out
Stereo Line Audio in
Power on reset
USB OTG PHY
Status LED
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For accurate information on this chip, revise TPS65950 DATA MANUAL official document
from Texas Instruments official site http://focus.ti .com
5.6 WIFI/BLUETOOTH INTERFACE
IEEE802.11b/g compliant.
WLAN: Chipset based on Marvel l 88W8686. The 88W8686 integrates a RF transceiver
operating at 2.4GHz, a physical layer, a media access controller, and an ARM processor into a
single die.
BLUETOOTH: Chipset based on CSR BC4ROM/21e. Bluetooth 2.0 compliant.
Class 2, 2.5 mW (4 dBm) ~10 meters. Version 2.0 + EDR 3 Mbit/s
5.6.1 BLOCK DIAGRAM
Figure 8 Wi-Fi /Bluetooth Combo module block Diagram
5.6.2 INTERFACES
Terminal
Name
Type
System
Description
RST_N_B
I
BT
Reset (active low). It must be low for >5ms.
PCM_OUT
O
BT
Synchronous data output CMOS output, tri-statable with weak internal pull-down
PCM_SYNC
I/O
BT
Synchronous data sync, Bi Directional with weak internal pull-down.
PCM_IN
I
BT
Synchronous data input, CMOS input, with weak pull-down
PCM_CLK
I/O
BT
Synchronous data clock ,Bi Directional with weak internal pull-down.
UART_TX
O
BT
UART data output active high. CMOS output, tri-statable with weak internal pull-up.
UART_CTS
I
BT
UART clear to send active low. CMOS input with weak internal pull-down.
UART_RX
I
BT
UART data input active high. CMOS input, with weak internal pull up
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UART_RTS
O
BT
UART request to send active low. CMOS input with weak internal pull -down.
SD_D3
I/O
WLAN
SDIO 4-bit Mode: SD_DAT[3] Data Line Bit [3] SDIO 1-bit Mode: SD_DAT[3] Reserved SDIO
SPI Model: SD_DAT[3] Card Select (active low)
SD_D2
SPI_SINTn
I/O
WLAN
G-SPI Mode: SPI_SINTn G-SPI interrupt Output (active low) SDIO 4-bit Mo de : SD_DAT[2]
Data Line Bit [2] or Read Wait (optional) SDIO 1-bit Mode: SD_DAT[2] Read Wait (optional)
SDIO SPI Model: SD_DAT[2] Reserved
SD_D1
SPI_SDO
I/O
WLAN
G-SPI Mode: SPI_SDO
G-SPI Data Output SDIO 4-bit Mode : SD_DAT[1 ] Data Line Bit [1] SDIO 1 -bit Mode :
SD_DAT[1] Interrupt SDIO SPI Model: SD_DAT[1] Reserved
SD_D0
SPI_SCSn
I/O
WLAN
G-SPI Mode: SPI_SCSn G-SPI Chip Select input SDIO 4-bit Mode: SD_DAT[0] Data Line Bit
[0] SDIO 1-bit Mode: SD_DAT[0] Data Line SDIO SPI Model: SD_DAT[0] Data Output
SD_CMD
SPI_SDI
I/O
WLAN
G-SPI Mode: SPI_SDI G-SPI Data Input SDIO 4-bit Mode: SD_CMD Command/Response
SDIO 1-bi t Mode : SD_CMD Comma nd L ine SDIO SPI Mo de l: SD_CMD Da ta Input
SD_CLK
SPI_CLK
I/O
WLAN
G-SPI Mode: SPI_CLK G-SPI Clock Input SDIO 4-bit Mode: SD_CLK Clock Input SDIO 1-bit
Mode: SD_CLK Clock Input SDIO SPI Model: SD_CLK Clock Input
RESET_N_W
I
WLAN
Internal pull-up. Reset (active low)
PDn
I
WLAN
Full Power Down (active low) 0 = full power down mode 1 = normal mode
Table 9 Wi-Fi/Bluetooth Interface summary
Bluetooth UART uses the UART 2 from OMAP3530/DM3730.
Bluetooth Digital Audio uses MCBSP3 from OMAP3530/DM3730.
Wi-Fi uses MMC2 interface from OMAP3530/DM3730.
[MMC2_CLK0, MMC2_CMD, MMC2_DAT0, MMC2_DAT1, MMC2_DAT2, MMC2_DAT3].
UART2 and McBSP3 can be used in boards without Wi-Fi/Bluetooth or if the Bluetooth is in
resetandTPS65950PCMVSPit’sdisabled.
5.6.3 POWER-ON RESET SEQUENCE FOR WLAN
PDn / RESET_N_W tied together
PDn pin separated from RESET_N_W. Host cannot pulse RESET_N_W pin.
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PDn pin separated from RESET_N_W. Host controls pulsing of RESET_N_W pin.
5.6.4 WLAN RESET/PDN PINS
Reset can be done by using GPIO_94 or GPIO_138. See your IGEP™ v2 model to know default
assembly option (See FAQ in http://labs.igep.es)
Power down can be done by using GPIO_95 or GPIO_139. See your IGEP™ v2 model to know
default assembly option (See FAQ in http://labs.igep.es).
5.6.5 BLUETOOTH RESET PINS
Reset can be done by using GPIO_182 or GPIO_137. See your IGEP™ v2 model to know default
assembly option (See FAQ in http://labs.igep.es)
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5.6.6 PCM INTERFACE
5.6.6.1 TPS65950 SIDE
5.6.6.2 WI-FI MODULE SIDE
PCM_OUT –Output- Synchronous data output CMOS output, tri-state with weak internal pull-
down
PCM_SYNC -I/O- Synchronous data sync Bi Directional with weak internal pull-down.
PCM_IN – Input - Synchronous data input CMOS input, with weak pull-down
PCM_CLK - I/O - Synchronous data clock Bi Directional with weak internal pull-down.
McBSP3it’s connected to OMAP3530/DM3730 and TPS65950 (PCM VSP).
5.6.7 IGEP™ v2 ANTENNAS (INTERNAL/EXTERNAL - UD11, JD21, JD22)
For the cable you will find cable assemblies if you look for CABLE ASSEMBLY RF GSM MURATA
to SMA MALE.
JD21 and JD22 are U.FL series HIROSE connector for the external WIFI/BLUETOOTH antenna
(Part number U.FL-R-SMT-1).
This manual suits for next models
1
Table of contents
Other i-See Motherboard manuals
