iC-Haus iC-TW29 User manual

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 1/28
FEATURES
•Any output resolution with any input resolution
•Independently-programmed ABZ, UVW, and BiSS resolutions
•Absolute data interface for external revolution counters
•BiSS C-Mode interface (Encoder Proles 3, 3S, and 4)
•26-bit singleturn position and 32-bit revolution count via SPI
•Four capture registers for coded reference marks and
touch-probe applications
•Eccentricity compensation
•Input frequency up to 700 kHz
•AB output frequency of up to 12.5 MHz
•Differential RS422 line driver outputs for ABZ or UVW
•Simultaneous single-ended outputs for ABZ, UVW, BiSS
• Automatic compensation of amplitude, offset, and phase errors
•Digital ltering for ultra-low output jitter
•Encoder Link interface for in-eld re-conguration
•Internal EEPROM and oscillator
•LED intensity control by PWM output
•Low latency (2.4 µs or 5.0 µs)
•Pin-compatible with iC-TW28
APPLICATIONS
•Rotary and linear incremental or
absolute encoders
•Magnetic or optical sin/cos
sensor interface
•Brushless motor commutation
(2...64 poles)
•Imbedded motion control
PACKAGES
32-pin QFN
5 mm x 5 mm x 0.9 mm
RoHS compliant
BLOCK DIAGRAM
Interpolated Angle (IA)
SPI
Interface
xSS
SCK
SO
SI
Interpolator
ZERO
Channel
SIN+
SIN–
COS+
COS–
ZERO+
ZERO–
26-Bit
Gearbox
Includes
Filter,
Hysteresis,
and
Eccentricity
Correction
Zero Gating Window (ZW)
ABZ with
Output Freq.
Limiter
Normalized Angle (NR)
Revolution Count (RC)
UVW
BiSS Slave
with Encoder
Profile and
EDS
UVW Scan
Absolute Data
Interface
(ADI)
Revolution Count (RC),
Cycle Count (CC), and Sync Bits
I/O
Multiplexer
A+
A–
B+
B–
Z+
Z–
Auto Calibration,
Auto Adaption,
LED Control, Startup,
ID, EEPROM
xCALIBxIRQ LED
Position
Capture
BiSS Control Data
Encoder Link
Monitors:
Status/Fault, Temp.,
Sin/Cos Amplitude,
Excessive Error,
Excessive Adaption
GPIO
IA
CC
RC
AVDD AVSS DVDD DVSS IOVDD IOVSS
iC-TW29
Copyright ©2019, 2020 iC-Haus http://www.ichaus.com

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 2/28
DESCRIPTION
The iC-TW29 is a system-on-chip for encoder appli-
cations. The integration of a 14-bit interpolator with a
26-bit gearbox and a resolution-enhancing digital lter
provides a complete solution for arbitrary resolution
single and multiturn encoders. Independent I/O mod-
ules with individually programmed resolutions provide
BiSS C, standard encoder quadrature (ABZ), or com-
mutation (UVW) outputs separately or in combination.
The iC-TW29 accepts 20 mV to 2 V differential sin/-
cos input signals directly from magnetic or optical
sensors—no external signal conditioning is required
in most applications. The differential zero input ac-
cepts a wide range of digital and analog index gating
sources such as Hall or MR sensor bridges. Auto-
matic calibration and adaption (correction during op-
eration) of sensor offset, sin/cos amplitude match,
and phase quadrature provide and maintain minimum
angular error and jitter. Additionally, automatic calibra-
tion of gain, offset, and phase of the zero input allows
for rapid commissioning.
The gearbox tracks input cycles (up to 4096 per rev-
olution) and provides output resolutions of up to 26
bits per revolution. Auto-calibrated eccentricity com-
pensation increases achievable angular accuracy by
correcting for off-center optical discs or magnetic pole-
wheels. When combined with an external revolution
counting device (such as the iC-PVL) communicating
via its absolute data interface, the iC-TW29 provides
a complete BiSS multiturn absolute encoder solution.
The differential zero input can be used with a tra-
ditional index sensor to generate an incremental Z
output or to clear the gearbox counter in singleturn
absolute applications. It can also be used as a po-
sition capture input with a four-word FIFO to allow
decoding distance-coded reference marks in hosted
applications.
In addition to industry-standard incremental ABZ
quadrature output, the iC-TW29 also provides UVW
commutation output modes for 1 to 32 pole-pair mo-
tors as well as BiSS and SPI interfaces. The BiSS in-
terface provides BiSS encoder proles 3, 3S (safety),
or 4 as well as optional electronic data sheet EDS SE
functionality. BiSS passthrough mode allows a host
processor to implement any BiSS encoder prole or
EDS.
Extensive status/fault and signal quality monitoring
capabilities allow detection and notication of poor
operating conditions.
The iC-TW29 is congured via the bi-directional BiSS,
SPI, or Encoder Link interfaces. Encoder link uses
the incremental quadrature outputs to implement a
SPI-like serial interface for eld re-conguration or
diagnostics.
The iC-TW29 requires minimal external components
for operation. An EEPROM for storage of congu-
ration and calibration data, and RS422 line drivers
for the ABZ or UVW outputs are already integrated
on-chip. An external line driver/receiver is required for
BiSS applications. An integrated power-on reset cir-
cuit can be overridden by an external hardware reset
signal if necessary.
General notice on application-specic programming
Parameters dened in the datasheet represent supplier’s
attentive tests and validations, but - by principle - do not imply
any warranty or guarantee as to their accuracy, completeness or
correctness under all application conditions. In particular, setup
conditions, register settings and power-up have to be thoroughly
validated by the user within his specic application environment
and requirements (system responsibility).
For magnetic sensor systems: The chip’s performance in
application is impacted by system conditions like the quality of
the magnetic target, eld strength and stray elds, temperature
and mechanical stress, sensor alignment and initial calibration.
For optical sensor systems: The chip’s performance in
application is impacted by system conditions like the quality of
the optical target, the illumination, temperature and mechanical
stress, sensor alignment and initial calibration.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 3/28
CONTENTS
PACKAGING INFORMATION 4
PIN CONFIGURATION QFN32-5x5 . . . . . 4
PACKAGE DIMENSIONS . . . . . . . . . . . 5
PIN FUNCTIONS . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS 8
THERMAL DATA 8
ELECTRICAL CHARACTERISTICS 9
OPERATING REQUIREMENTS 13
SPIInterface .................. 13
Encoder Link Interface . . . . . . . . . . . . 14
BiSS Interface . . . . . . . . . . . . . . . . . 15
ADIInterface .................. 16
FUNCTIONAL BLOCK DIAGRAM 17
ELECTRICAL CONNECTIONS 20
Power and Ground . . . . . . . . . . . . . . . 22
Reference Outputs . . . . . . . . . . . . . . . 22
xCALIBInput .................. 22
SIN and COS Inputs . . . . . . . . . . . . . . 22
ZEROInputs .................. 23
ABZOutputs .................. 24
UVWOutputs.................. 24
xRSTInput ................... 24
xIRQ....................... 24
LEDOutput................... 24
BiSSENInput.................. 24
General-Purpose I/O . . . . . . . . . . . . . . 24
SPIPort..................... 25
ReservedPins ................. 25
CONFIGURATION AND CALIBRATION 26
Introduction................... 26
Default Conguration . . . . . . . . . . . . . 26
Input Conguration and Calibration . . . . . . 26
ABZ/UVW Conguration . . . . . . . . . . . . 26
BiSS/SSI Conguration . . . . . . . . . . . . 27

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 4/28
PACKAGING INFORMATION (Compatible with iC-TW28)
PIN CONFIGURATION QFN32-5x5
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
252627282930 31
32
<D-CODE>
<A-CODE>
<P-CODE>
PIN FUNCTIONS
No. Name Function
1 SIN+3+ Differential Sine Input
2 SIN–3– Differential Sine Input
3 AVDD +3.3 V Analog Power Supply Input
4 COS+3+ Differential Cosine Input
5 COS–3– Differential Cosine Input
6 AVSS Analog Ground
7 ZERO+4+ Differential Zero (Index) Input
8 ZERO–4– Differential Zero (Index) Input
9 VREF ADC Reference Voltage Output
10 VC Bias Output (VDD/2)
11 Reserved1Must be connected to ground
12 Reserved1Must be connected to ground
13 GPIO3General Purpose I/O
14 xRST4Reset Input (low active)
15 xCALIB4Auto-Calibration Input (low active)
16 xIRQ4Interrupt Request (active-low)
Input/Output or Fault Output
17 Z– – Differential RS422 Z Output
or Multifunction I/O
18 Z+ + Differential RS422 Z Output
or Multifunction I/O
19 IOVSS I/O Ground
20 B– – Differential RS422 B Output
or Multifunction I/O
21 B+ + Differential RS422 B Output
or Multifunction Output
22 IOVDD +3.3 V I/O Power Supply Input
23 A– – Differential RS422 A Output
or Multifunction I/O
24 A+ + Differential RS422 A Output
or Multifunction I/O
25 DVDD +3.3 V Digital Power Supply Input
26 LED4LED Intensity Control Output
or General-Purpose I/O
27 DVSS Digital Ground
28 SO SPI Slave Output (Master Input)
29 SI3SPI Slave Input (Master Output)
30 SCLK3SPI Clock Input
31 xSS4SPI Slave Select Input
32 BISSEN5BiSS Interface Enable
TP2Backside paddle
IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes);
1Must be connected to ground.
2Must be connected to a ground plane at AVSS potential. Can also be used to connect DVSS.
3Do not allow to oat. Connect to ground via 10 kΩresistor if not used.
4Do not allow to oat. Connect to 3.3 V or ground via 10 kΩresistor if not in use. Alternatively, program MAIN_CFG.zero = 1 for internal biasing.
5Connect to 3.3 V (to DVDD for to enable BiSS interface) or ground (to DVSS to disable BiSS interface). Do not allow to oat.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 5/28
PACKAGE DIMENSIONS
5
5
TOP
0.40
3.65
3.65
0.22 0.50
BOTTOM
0.90
±0.10
SIDE
R
0.15
3.60
4.90
3.60
4.90
0.30 0.50
0.70
RECOMMENDED PCB-FOOTPRINT
drb_qfn32-5x5-6_pack_1, 10:1
All dimensions given in mm.
Tolerances of form and position according to JEDEC MO-220.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 6/28
PIN FUNCTIONS
No. Name I/O Function Description
1 SIN+ Analog in Sine Input + Differential sine signal input. For single ended sensors SIN– must be
biased to an appropriate DC level.
2 SIN– Analog in Sine Input –
3 AVDD Supply Analog Power Supply +3.1 V to +3.6 V supply voltage input for analog circuitry. AVDD should
be tied together with DVDD and IOVDD and supplied from a clean
source.
4 COS+ Analog in Cosine Input + Differential cosine signal input. For single ended sensors COS– must
be biased to an appropriate DC level.
5 COS– Analog in Cosine Input –
6 AVSS Ground Analog Ground AVSS must be tied to high quality ground, usually a solid PCB plane.
7 ZERO+ Analog in Zero Input + Differential Zero Gating Input.
If single ended signal sources are used, the unused terminal (either
ZERO+ or ZERO–) must be tied to an appropriate DC bias.
8 ZERO– Analog in Zero Input –
9 VREF Analog out Bias Output Decouple with 100 nF capacitor to AVSS. Do not inject noise into this
pin as it directly impacts ADC conversion quality.
10 VC Analog out Bias Output Decouple with 100 nF capacitor to AVSS. Do not inject noise into this
pin as it directly impacts ADC conversion quality.
11 Reserved Digital in Test Input Reserved pins; must be connected to DVSS for normal operation.
12 Reserved Digital in Test Input
13 GPIO Digital in/out General-Purpose I/O Connect to AVSS if not used.
14 xRST Digital in,
active low
Reset Input The device is held in reset (low power mode) as long as xRST is low.
15 xCALIB Digital in,
active low
Calibration Control Device enters calibration mode on falling edge of CALIB. This pin must
be tied high if not used.
16 xIRQ Digital out,
active low
or input
IRQ or Fault Output or IRQ
input
Interrupt request output to external micro controller or interrupt re-
quest input. Output can also be used to directly drive a fault LED
in stand-alone applications. Can be congured as push-pull or
open-drain.
17 Z– Digital/RS422 out Z– or W– Output In ABZ output modes these are the differential Z outputs.
In UVW output modes these are the W outputs.
In BiSS mode (BISSEN pin high), pin Z+ is the data input SLI. If daisy
chaining is not required, Z+ can be grounded (IOVSS).
In other modes, these are multifunction I/O.
18 Z+ Digital/RS422 out Z+ or W+ Output
19 IOVSS Ground I/O Ground All ground pins must be connected to a high quality ground, usually a
solid PCB plane.
20 B– Digital/RS422 out B– or V– Output In ABZ output modes these are the differential B outputs.
In UVW output modes these are the V outputs.
In BiSS mode (BISSEN pin high), pin B+ is the data output SLO.
In other modes, these are multifunction I/O.
In Z test mode these show the Z gating window.
21 B+ Digital/RS422 out B+ or V+ Output
22 IOVDD Supply Output Drivers
Power Supply
+3.1 V to +3.6 V voltage terminal supplying all pin output drivers includ-
ing the RS422 drivers and LED current.
IOVDD and DVDD must be the same voltage level. IOVDD can require
up to 100mA depending on loads. It is usually sufcient to tie IOVDD to
the same supply as AVDD and DVDD.
23 A– Digital/RS422 out A– or U– Output In ABZ output modes these are the differential Z outputs.
In UVW output modes these are the W outputs.
In BiSS mode (BISSEN pin high), pin A+ is the clock input MA.
In other modes, these are multifunction I/O.
In Z test mode these show the un-gated Z signal once per input period.
With Encoder Link active, A+ is the ELCLK input and A– is ELIN input
or ELOUT output.
24 A+ Digital/RS422 out A+ or U+ Output
25 DVDD Supply Digital Power Supply +3.1 V to +3.6 V supply voltage terminal for digital circuits. DVDD
should be tied together with AVDD and IOVDD to a high quality supply.
26 LED Digital input
or output
LED PWM Output Used to supply the illumination LED of optical sensors to maintain
constant intensity and constant Sin/Cos sensor amplitude. Can be
congured as push-pull or open-drain. If not required for LED control, it
is a general purpose I/O.
27 DVSS Ground Digital Ground Pin must tied to high quality ground, usually a solid PCB plane.
28 SO Digital out SPI Slave Output Connect to SPI master MI pin.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 7/28
PIN FUNCTIONS
No. Name I/O Function Description
29 SI Digital in SPI Slave Input Connect to SPI master MO pin.
30 SCLK Digital in SPI Slave Clock Input Connect to SPI master clock output pin.
31 xSS Digital in SPI Slave Select Input Connects to SPI master slave select output pin.
32 BISSEN Digital in BiSS Interface Enable Connect to DVDD to enable the BiSS/SSI interface.
The I/O pins A+, B+, Z+ are used for MA, SLO, SLI.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 8/28
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these values damage may occur.
Item Symbol Parameter Conditions Unit
No. Min. Max.
G001 VDD Voltage at DVDD, AVDD, and IOVDD Referenced to DVSS, AVSS, and IOVSS
respectively
–0.3 4.1 V
G002 Vpin Pin Voltage at any pin Referenced to DVSS, AVSS, and IOVSS –0.3 AVDD +
0.3
V
G003 Ipin Input Current into any pin –2 2 mA
G004 Vesd1 ESD Susceptibility HBM, 100 pF discharged through 1.5 kΩ4 kV
G005 Tj Junction Temperature –40 150 °C
THERMAL DATA
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
T01 Ta Operating Ambient Temperature Range –40 125 °C
T02 Rthja Thermal Resistance Chip to Ambient QFN32-5x5 surface mounted to PCB
according to JEDEC 51
40 K/W
T03 Ts Storage Temperature –40 150 °C
All voltages are referenced to pin AVSS unless otherwise stated.
All currents owing into the device pins are positive; all currents owing out of the device pins are negative.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 9/28
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Total Device
001 VDD Permissible Supply Voltage
AVDD, DVDD, IOVDD
3.1 3.6 V
002 IAVDD Supply Current into AVDD AVDD, DVDD, IOVDD = 3.3 V, n = 1 kHz,
inter = x256, ABZ and UVW outputs active
15 mA
003 IDVDD Supply Current into DVDD AVDD, DVDD, IOVDD = 3.3 V, n = 1 kHz,
inter = x256, ABZ and UVW outputs active
25 mA
004 IIOVDD Supply Current into IOVDD RS422 drivers enabled (MAIN_CFG.rs422 = 1);
quadrature outputs terminated with 120 Ω85 mA
quadrature outputs open 2 mA
005 IRST Reset Current
(IAVDD + IDVDD + IIAVDD)
xRST low 1 µA
Signal Inputs and Ampliers: SIN+, SIN–, COS+, COS–
101 Vin() Permissible Input Voltage Refer to Figure 1
Low Input Range (MAIN_CFG.input = 0 or 1) 0.35 AVDD –
1.1
V
High Input Range (MAIN_CFG.input = 3) 1.0 AVDD V
For High Input Range and MAIN_CFG.input = 2
refer to Figure 1.
102 Ain()diff Permissible Differential Input
Amplitude, Max(SIN+ – SIN–) or
Max(COS+ – COS–)
Refer to Figure 2
Low Input Range (MAIN_CFG.input = 0 or 1) 20 700 mVpp
High Input Range (MAIN_CFG.input = 2 or 3) 65 2000 mVpp
103 Vcm() Permissible Input Common Mode
Range, (SIN+ + SIN–)/2 or
(COS+ + COS–)/2
Refer to Figure 3
Minimum gain (MAIN_CFG.input =/ 3) 0.7 AVDD –
1.45
V
Maximum gain (MAIN_CFG.input =/ 3) 0.35 AVDD –
1.1
V
Minimum gain (MAIN_CFG.input = 3) 2.0 AVDD V
Maximum gain (MAIN_CFG.input = 3) 1.0 AVDD V
104 n() Sin/Cos Input Frequency 700 kHz
105 Vos() Amplier Input Offset Voltage ±15 mV
106 Ilk() Input Leakage Current ±50 nA
108 OFFcorr Correctable Input Offset Voltage
As percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplier offset (item 105);
±25 %
(step size: 3.9 mV / gain)
109 Acorr Correctable Balance (Amplitude)
Mismatch
Max(Asin, Acos) / Min(Asin, Acos), where Asin
and Acos are the SIN/COS input amplitudes
respectively. (step size 0.02%)
±25 %
110 PHIcorr Correctable Phase Error (step size 0.015°)±26 °
111 Rin()diff Differential Input Resistance Low Input Range (MAIN_CFG.input = 0) 10 1000 MΩ
Low with Loss Detect. (MAIN_CFG.input = 1) 0.220 MΩ
High Input Range (MAIN_CFG.input = 2 or 3) 0.640 MΩ
Zero Signal Inputs and Amplier: ZERO+, ZERO–
201 Vin() Permissible Input Voltage 0 AVDD V
202 Vcm() Permissible Input Common Mode
Voltage
Refer to Figure 3
Minimum gain (MAIN_CFG.zero = 0) 0.7 AVDD –
1.45
V
Maximum gain (MAIN_CFG.zero = 0) 0.35 AVDD –
1.1
V
Minimum gain (MAIN_CFG.zero = 1) 2.0 AVDD V
Maximum gain (MAIN_CFG.zero = 1) 1.0 AVDD V
203 Vos() Input Referenced Offset Voltage ±20 mV
204 Ilk() Input Leakage Current ±50 nA
205 OFFcorr Correctable Input Offset Voltage
As percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplier offset (item 105);
±100 %
(step size 60 mV / gain)

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 10/28
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
206 Rin()diff Differential Input Resistance MAIN_CFG.zero = 0 10 1000 MΩ
MAIN_CFG.zero = 1 0.620 MΩ
Converter Performance
304 INL Integral Nonlinearity (over one
input SIN/COS cycle)
Refer to Figure 5, 1 Vpp-diff SIN/COS input
with compensated offset, gain and phase
0.2 °
305 DNL Differential Nonlinearity (over one
input SIN/COS cycle
Refer to Figure 5, 1 Vpp-diff SIN/COS input
with compensated offset, gain and phase
0.1 °
307 tAB Output Phase A vs. B Refer to Figure 4 25 %
308 twhi Duty Cycle at Output A, B Refer to Figure 4 50 %
309 AArel Relative Angle Accuracy Refer to Figure 4, at conditions of 305 2 %
310 tMTD Time Between AB Edges
(Minimum Transition Distance)
Refer to Figure 4, ABLIMIT = 0 1/fosc 20 ns
Internal Oscillator
401 fosc Oscillator Frequency Tj = 27 °C; AVDD, DVDD = 3.1 V 48 51 MHz
AVDD, DVDD = 3.6 V 48 52 MHz
402 TCf Temperature Coefcient 225 ppm/K
Internal EEPROM
501 Nwrite Permissible Number of Write
Cycles
Tj = –40 °C...85 °C 1000
502 Tjw Write Temperature Range –40 85 °C
503 Tjr Read Temperature Range –40 125 °C
504 DRTraw Raw Data Retention Time 10 years
505 DRTact Actual Data Retention Time (with
error correction)
Tj = 85 °C 50 years
Reset and Start-Up: xRST
601 DVDDonoff DVDD Power-On/Off Threshold xRST tied to DVDD 2.5 2.7 3.0 V
603 tstart Startup Time Valid EEPROM conguration, START.wait = 0 2 ms
Digital Input Pins: xRST, xCALIB, A+/– (Encoder Link active), A– and B– (BiSS mode), SI, SCLK, xSS,GPIO, BISSEN
701 Vt()hi Input Logic Threshold High DVDD = 3.6 V 1.9 V
702 Vt()lo Input Logic Threshold Low DVDD = 3.3 V 0.8 V
703 Ilk() Input Leakage Current at
SI, SCLK, xSS
±50 nA
704 f(SCLK) Permissible SPI Clock Frequency
at SCLK
TEST.spi = 0 20 MHz
TEST.spi = 1 40 MHz
705 tRQ Request Time at MA (A+) BiSSEN = high; for SSI data output to SLO, 24 / fosc
see Figure 9
Digital Output Pins: xIRQ, SO, A+/A–, B+/B–, Z+/Z– (CMOS drivers enabled: MAIN_CFG.rs422 = 0), Z– (BiSS mode)
801 I()max Permissible Output Current Per pin, indenite ±10 mA
802 Vout()hi Output Voltage High I() = –4 mA, 2.4 V
MAIN_CFG.irqpp = 1 (for xIRQ push-pull)
803 Vs()hi Saturation Voltage High Vs()hi = IOVDD - V(); I() = -4 mA, 0.7 V
MAIN_CFG.irqpp = 1 (for xIRQ push-pull)
804 Vs()lo Saturation Voltage Low I() = 4 mA 0.7 V
805 Isc()hi Short-Circuit Current High Any pin shorted to DVSS –30 –16 mA
806 Isc()lo Short-Circuit Current Low Any pin shorted to DVDD 16 30 mA
807 tr() Rise Time DVDD = 3.3 V, CL = 50 pF, 10% →90% VDD 20 ns
808 tf() Fall Time DVDD = 3.3 V, CL = 50 pF, 10% →90% VDD 20 ns
809 tout() Slave Timeout at SLO (B+) BiSSEN = high; for BiSS & SSI, see Figure 11;
BiSS_CFG0.at = 0 (xed) 1024
/ fosc
BiSS_CFG0.at = 1 (adaptive) 8 / fosc tinit + 1024
4 / fosc / fosc