iC-Haus iC-TW29 User manual

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 1/28
FEATURES
•Any output resolution with any input resolution
•Independently-programmed ABZ, UVW, and BiSS resolutions
•Absolute data interface for external revolution counters
•BiSS C-Mode interface (Encoder Proles 3, 3S, and 4)
•26-bit singleturn position and 32-bit revolution count via SPI
•Four capture registers for coded reference marks and
touch-probe applications
•Eccentricity compensation
•Input frequency up to 700 kHz
•AB output frequency of up to 12.5 MHz
•Differential RS422 line driver outputs for ABZ or UVW
•Simultaneous single-ended outputs for ABZ, UVW, BiSS
• Automatic compensation of amplitude, offset, and phase errors
•Digital ltering for ultra-low output jitter
•Encoder Link interface for in-eld re-conguration
•Internal EEPROM and oscillator
•LED intensity control by PWM output
•Low latency (2.4 µs or 5.0 µs)
•Pin-compatible with iC-TW28
APPLICATIONS
•Rotary and linear incremental or
absolute encoders
•Magnetic or optical sin/cos
sensor interface
•Brushless motor commutation
(2...64 poles)
•Imbedded motion control
PACKAGES
32-pin QFN
5 mm x 5 mm x 0.9 mm
RoHS compliant
BLOCK DIAGRAM
Interpolated Angle (IA)
SPI
Interface
xSS
SCK
SO
SI
Interpolator
ZERO
Channel
SIN+
SIN–
COS+
COS–
ZERO+
ZERO–
26-Bit
Gearbox
Includes
Filter,
Hysteresis,
and
Eccentricity
Correction
Zero Gating Window (ZW)
ABZ with
Output Freq.
Limiter
Normalized Angle (NR)
Revolution Count (RC)
UVW
BiSS Slave
with Encoder
Profile and
EDS
UVW Scan
Absolute Data
Interface
(ADI)
Revolution Count (RC),
Cycle Count (CC), and Sync Bits
I/O
Multiplexer
A+
A–
B+
B–
Z+
Z–
Auto Calibration,
Auto Adaption,
LED Control, Startup,
ID, EEPROM
xCALIBxIRQ LED
Position
Capture
BiSS Control Data
Encoder Link
Monitors:
Status/Fault, Temp.,
Sin/Cos Amplitude,
Excessive Error,
Excessive Adaption
GPIO
IA
CC
RC
AVDD AVSS DVDD DVSS IOVDD IOVSS
iC-TW29
Copyright ©2019, 2020 iC-Haus http://www.ichaus.com

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 2/28
DESCRIPTION
The iC-TW29 is a system-on-chip for encoder appli-
cations. The integration of a 14-bit interpolator with a
26-bit gearbox and a resolution-enhancing digital lter
provides a complete solution for arbitrary resolution
single and multiturn encoders. Independent I/O mod-
ules with individually programmed resolutions provide
BiSS C, standard encoder quadrature (ABZ), or com-
mutation (UVW) outputs separately or in combination.
The iC-TW29 accepts 20 mV to 2 V differential sin/-
cos input signals directly from magnetic or optical
sensors—no external signal conditioning is required
in most applications. The differential zero input ac-
cepts a wide range of digital and analog index gating
sources such as Hall or MR sensor bridges. Auto-
matic calibration and adaption (correction during op-
eration) of sensor offset, sin/cos amplitude match,
and phase quadrature provide and maintain minimum
angular error and jitter. Additionally, automatic calibra-
tion of gain, offset, and phase of the zero input allows
for rapid commissioning.
The gearbox tracks input cycles (up to 4096 per rev-
olution) and provides output resolutions of up to 26
bits per revolution. Auto-calibrated eccentricity com-
pensation increases achievable angular accuracy by
correcting for off-center optical discs or magnetic pole-
wheels. When combined with an external revolution
counting device (such as the iC-PVL) communicating
via its absolute data interface, the iC-TW29 provides
a complete BiSS multiturn absolute encoder solution.
The differential zero input can be used with a tra-
ditional index sensor to generate an incremental Z
output or to clear the gearbox counter in singleturn
absolute applications. It can also be used as a po-
sition capture input with a four-word FIFO to allow
decoding distance-coded reference marks in hosted
applications.
In addition to industry-standard incremental ABZ
quadrature output, the iC-TW29 also provides UVW
commutation output modes for 1 to 32 pole-pair mo-
tors as well as BiSS and SPI interfaces. The BiSS in-
terface provides BiSS encoder proles 3, 3S (safety),
or 4 as well as optional electronic data sheet EDS SE
functionality. BiSS passthrough mode allows a host
processor to implement any BiSS encoder prole or
EDS.
Extensive status/fault and signal quality monitoring
capabilities allow detection and notication of poor
operating conditions.
The iC-TW29 is congured via the bi-directional BiSS,
SPI, or Encoder Link interfaces. Encoder link uses
the incremental quadrature outputs to implement a
SPI-like serial interface for eld re-conguration or
diagnostics.
The iC-TW29 requires minimal external components
for operation. An EEPROM for storage of congu-
ration and calibration data, and RS422 line drivers
for the ABZ or UVW outputs are already integrated
on-chip. An external line driver/receiver is required for
BiSS applications. An integrated power-on reset cir-
cuit can be overridden by an external hardware reset
signal if necessary.
General notice on application-specic programming
Parameters dened in the datasheet represent supplier’s
attentive tests and validations, but - by principle - do not imply
any warranty or guarantee as to their accuracy, completeness or
correctness under all application conditions. In particular, setup
conditions, register settings and power-up have to be thoroughly
validated by the user within his specic application environment
and requirements (system responsibility).
For magnetic sensor systems: The chip’s performance in
application is impacted by system conditions like the quality of
the magnetic target, eld strength and stray elds, temperature
and mechanical stress, sensor alignment and initial calibration.
For optical sensor systems: The chip’s performance in
application is impacted by system conditions like the quality of
the optical target, the illumination, temperature and mechanical
stress, sensor alignment and initial calibration.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 3/28
CONTENTS
PACKAGING INFORMATION 4
PIN CONFIGURATION QFN32-5x5 . . . . . 4
PACKAGE DIMENSIONS . . . . . . . . . . . 5
PIN FUNCTIONS . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS 8
THERMAL DATA 8
ELECTRICAL CHARACTERISTICS 9
OPERATING REQUIREMENTS 13
SPIInterface .................. 13
Encoder Link Interface . . . . . . . . . . . . 14
BiSS Interface . . . . . . . . . . . . . . . . . 15
ADIInterface .................. 16
FUNCTIONAL BLOCK DIAGRAM 17
ELECTRICAL CONNECTIONS 20
Power and Ground . . . . . . . . . . . . . . . 22
Reference Outputs . . . . . . . . . . . . . . . 22
xCALIBInput .................. 22
SIN and COS Inputs . . . . . . . . . . . . . . 22
ZEROInputs .................. 23
ABZOutputs .................. 24
UVWOutputs.................. 24
xRSTInput ................... 24
xIRQ....................... 24
LEDOutput................... 24
BiSSENInput.................. 24
General-Purpose I/O . . . . . . . . . . . . . . 24
SPIPort..................... 25
ReservedPins ................. 25
CONFIGURATION AND CALIBRATION 26
Introduction................... 26
Default Conguration . . . . . . . . . . . . . 26
Input Conguration and Calibration . . . . . . 26
ABZ/UVW Conguration . . . . . . . . . . . . 26
BiSS/SSI Conguration . . . . . . . . . . . . 27

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 4/28
PACKAGING INFORMATION (Compatible with iC-TW28)
PIN CONFIGURATION QFN32-5x5
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
252627282930 31
32
<D-CODE>
<A-CODE>
<P-CODE>
PIN FUNCTIONS
No. Name Function
1 SIN+3+ Differential Sine Input
2 SIN–3– Differential Sine Input
3 AVDD +3.3 V Analog Power Supply Input
4 COS+3+ Differential Cosine Input
5 COS–3– Differential Cosine Input
6 AVSS Analog Ground
7 ZERO+4+ Differential Zero (Index) Input
8 ZERO–4– Differential Zero (Index) Input
9 VREF ADC Reference Voltage Output
10 VC Bias Output (VDD/2)
11 Reserved1Must be connected to ground
12 Reserved1Must be connected to ground
13 GPIO3General Purpose I/O
14 xRST4Reset Input (low active)
15 xCALIB4Auto-Calibration Input (low active)
16 xIRQ4Interrupt Request (active-low)
Input/Output or Fault Output
17 Z– – Differential RS422 Z Output
or Multifunction I/O
18 Z+ + Differential RS422 Z Output
or Multifunction I/O
19 IOVSS I/O Ground
20 B– – Differential RS422 B Output
or Multifunction I/O
21 B+ + Differential RS422 B Output
or Multifunction Output
22 IOVDD +3.3 V I/O Power Supply Input
23 A– – Differential RS422 A Output
or Multifunction I/O
24 A+ + Differential RS422 A Output
or Multifunction I/O
25 DVDD +3.3 V Digital Power Supply Input
26 LED4LED Intensity Control Output
or General-Purpose I/O
27 DVSS Digital Ground
28 SO SPI Slave Output (Master Input)
29 SI3SPI Slave Input (Master Output)
30 SCLK3SPI Clock Input
31 xSS4SPI Slave Select Input
32 BISSEN5BiSS Interface Enable
TP2Backside paddle
IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes);
1Must be connected to ground.
2Must be connected to a ground plane at AVSS potential. Can also be used to connect DVSS.
3Do not allow to oat. Connect to ground via 10 kΩresistor if not used.
4Do not allow to oat. Connect to 3.3 V or ground via 10 kΩresistor if not in use. Alternatively, program MAIN_CFG.zero = 1 for internal biasing.
5Connect to 3.3 V (to DVDD for to enable BiSS interface) or ground (to DVSS to disable BiSS interface). Do not allow to oat.

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 5/28
PACKAGE DIMENSIONS
5
5
TOP
0.40
3.65
3.65
0.22 0.50
BOTTOM
0.90
±0.10
SIDE
R
0.15
3.60
4.90
3.60
4.90
0.30 0.50
0.70
RECOMMENDED PCB-FOOTPRINT
drb_qfn32-5x5-6_pack_1, 10:1
All dimensions given in mm.
Tolerances of form and position according to JEDEC MO-220.

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 6/28
PIN FUNCTIONS
No. Name I/O Function Description
1 SIN+ Analog in Sine Input + Differential sine signal input. For single ended sensors SIN– must be
biased to an appropriate DC level.
2 SIN– Analog in Sine Input –
3 AVDD Supply Analog Power Supply +3.1 V to +3.6 V supply voltage input for analog circuitry. AVDD should
be tied together with DVDD and IOVDD and supplied from a clean
source.
4 COS+ Analog in Cosine Input + Differential cosine signal input. For single ended sensors COS– must
be biased to an appropriate DC level.
5 COS– Analog in Cosine Input –
6 AVSS Ground Analog Ground AVSS must be tied to high quality ground, usually a solid PCB plane.
7 ZERO+ Analog in Zero Input + Differential Zero Gating Input.
If single ended signal sources are used, the unused terminal (either
ZERO+ or ZERO–) must be tied to an appropriate DC bias.
8 ZERO– Analog in Zero Input –
9 VREF Analog out Bias Output Decouple with 100 nF capacitor to AVSS. Do not inject noise into this
pin as it directly impacts ADC conversion quality.
10 VC Analog out Bias Output Decouple with 100 nF capacitor to AVSS. Do not inject noise into this
pin as it directly impacts ADC conversion quality.
11 Reserved Digital in Test Input Reserved pins; must be connected to DVSS for normal operation.
12 Reserved Digital in Test Input
13 GPIO Digital in/out General-Purpose I/O Connect to AVSS if not used.
14 xRST Digital in,
active low
Reset Input The device is held in reset (low power mode) as long as xRST is low.
15 xCALIB Digital in,
active low
Calibration Control Device enters calibration mode on falling edge of CALIB. This pin must
be tied high if not used.
16 xIRQ Digital out,
active low
or input
IRQ or Fault Output or IRQ
input
Interrupt request output to external micro controller or interrupt re-
quest input. Output can also be used to directly drive a fault LED
in stand-alone applications. Can be congured as push-pull or
open-drain.
17 Z– Digital/RS422 out Z– or W– Output In ABZ output modes these are the differential Z outputs.
In UVW output modes these are the W outputs.
In BiSS mode (BISSEN pin high), pin Z+ is the data input SLI. If daisy
chaining is not required, Z+ can be grounded (IOVSS).
In other modes, these are multifunction I/O.
18 Z+ Digital/RS422 out Z+ or W+ Output
19 IOVSS Ground I/O Ground All ground pins must be connected to a high quality ground, usually a
solid PCB plane.
20 B– Digital/RS422 out B– or V– Output In ABZ output modes these are the differential B outputs.
In UVW output modes these are the V outputs.
In BiSS mode (BISSEN pin high), pin B+ is the data output SLO.
In other modes, these are multifunction I/O.
In Z test mode these show the Z gating window.
21 B+ Digital/RS422 out B+ or V+ Output
22 IOVDD Supply Output Drivers
Power Supply
+3.1 V to +3.6 V voltage terminal supplying all pin output drivers includ-
ing the RS422 drivers and LED current.
IOVDD and DVDD must be the same voltage level. IOVDD can require
up to 100mA depending on loads. It is usually sufcient to tie IOVDD to
the same supply as AVDD and DVDD.
23 A– Digital/RS422 out A– or U– Output In ABZ output modes these are the differential Z outputs.
In UVW output modes these are the W outputs.
In BiSS mode (BISSEN pin high), pin A+ is the clock input MA.
In other modes, these are multifunction I/O.
In Z test mode these show the un-gated Z signal once per input period.
With Encoder Link active, A+ is the ELCLK input and A– is ELIN input
or ELOUT output.
24 A+ Digital/RS422 out A+ or U+ Output
25 DVDD Supply Digital Power Supply +3.1 V to +3.6 V supply voltage terminal for digital circuits. DVDD
should be tied together with AVDD and IOVDD to a high quality supply.
26 LED Digital input
or output
LED PWM Output Used to supply the illumination LED of optical sensors to maintain
constant intensity and constant Sin/Cos sensor amplitude. Can be
congured as push-pull or open-drain. If not required for LED control, it
is a general purpose I/O.
27 DVSS Ground Digital Ground Pin must tied to high quality ground, usually a solid PCB plane.
28 SO Digital out SPI Slave Output Connect to SPI master MI pin.

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 7/28
PIN FUNCTIONS
No. Name I/O Function Description
29 SI Digital in SPI Slave Input Connect to SPI master MO pin.
30 SCLK Digital in SPI Slave Clock Input Connect to SPI master clock output pin.
31 xSS Digital in SPI Slave Select Input Connects to SPI master slave select output pin.
32 BISSEN Digital in BiSS Interface Enable Connect to DVDD to enable the BiSS/SSI interface.
The I/O pins A+, B+, Z+ are used for MA, SLO, SLI.

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 8/28
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these values damage may occur.
Item Symbol Parameter Conditions Unit
No. Min. Max.
G001 VDD Voltage at DVDD, AVDD, and IOVDD Referenced to DVSS, AVSS, and IOVSS
respectively
–0.3 4.1 V
G002 Vpin Pin Voltage at any pin Referenced to DVSS, AVSS, and IOVSS –0.3 AVDD +
0.3
V
G003 Ipin Input Current into any pin –2 2 mA
G004 Vesd1 ESD Susceptibility HBM, 100 pF discharged through 1.5 kΩ4 kV
G005 Tj Junction Temperature –40 150 °C
THERMAL DATA
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
T01 Ta Operating Ambient Temperature Range –40 125 °C
T02 Rthja Thermal Resistance Chip to Ambient QFN32-5x5 surface mounted to PCB
according to JEDEC 51
40 K/W
T03 Ts Storage Temperature –40 150 °C
All voltages are referenced to pin AVSS unless otherwise stated.
All currents owing into the device pins are positive; all currents owing out of the device pins are negative.

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 9/28
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Total Device
001 VDD Permissible Supply Voltage
AVDD, DVDD, IOVDD
3.1 3.6 V
002 IAVDD Supply Current into AVDD AVDD, DVDD, IOVDD = 3.3 V, n = 1 kHz,
inter = x256, ABZ and UVW outputs active
15 mA
003 IDVDD Supply Current into DVDD AVDD, DVDD, IOVDD = 3.3 V, n = 1 kHz,
inter = x256, ABZ and UVW outputs active
25 mA
004 IIOVDD Supply Current into IOVDD RS422 drivers enabled (MAIN_CFG.rs422 = 1);
quadrature outputs terminated with 120 Ω85 mA
quadrature outputs open 2 mA
005 IRST Reset Current
(IAVDD + IDVDD + IIAVDD)
xRST low 1 µA
Signal Inputs and Ampliers: SIN+, SIN–, COS+, COS–
101 Vin() Permissible Input Voltage Refer to Figure 1
Low Input Range (MAIN_CFG.input = 0 or 1) 0.35 AVDD –
1.1
V
High Input Range (MAIN_CFG.input = 3) 1.0 AVDD V
For High Input Range and MAIN_CFG.input = 2
refer to Figure 1.
102 Ain()diff Permissible Differential Input
Amplitude, Max(SIN+ – SIN–) or
Max(COS+ – COS–)
Refer to Figure 2
Low Input Range (MAIN_CFG.input = 0 or 1) 20 700 mVpp
High Input Range (MAIN_CFG.input = 2 or 3) 65 2000 mVpp
103 Vcm() Permissible Input Common Mode
Range, (SIN+ + SIN–)/2 or
(COS+ + COS–)/2
Refer to Figure 3
Minimum gain (MAIN_CFG.input =/ 3) 0.7 AVDD –
1.45
V
Maximum gain (MAIN_CFG.input =/ 3) 0.35 AVDD –
1.1
V
Minimum gain (MAIN_CFG.input = 3) 2.0 AVDD V
Maximum gain (MAIN_CFG.input = 3) 1.0 AVDD V
104 n() Sin/Cos Input Frequency 700 kHz
105 Vos() Amplier Input Offset Voltage ±15 mV
106 Ilk() Input Leakage Current ±50 nA
108 OFFcorr Correctable Input Offset Voltage
As percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplier offset (item 105);
±25 %
(step size: 3.9 mV / gain)
109 Acorr Correctable Balance (Amplitude)
Mismatch
Max(Asin, Acos) / Min(Asin, Acos), where Asin
and Acos are the SIN/COS input amplitudes
respectively. (step size 0.02%)
±25 %
110 PHIcorr Correctable Phase Error (step size 0.015°)±26 °
111 Rin()diff Differential Input Resistance Low Input Range (MAIN_CFG.input = 0) 10 1000 MΩ
Low with Loss Detect. (MAIN_CFG.input = 1) 0.220 MΩ
High Input Range (MAIN_CFG.input = 2 or 3) 0.640 MΩ
Zero Signal Inputs and Amplier: ZERO+, ZERO–
201 Vin() Permissible Input Voltage 0 AVDD V
202 Vcm() Permissible Input Common Mode
Voltage
Refer to Figure 3
Minimum gain (MAIN_CFG.zero = 0) 0.7 AVDD –
1.45
V
Maximum gain (MAIN_CFG.zero = 0) 0.35 AVDD –
1.1
V
Minimum gain (MAIN_CFG.zero = 1) 2.0 AVDD V
Maximum gain (MAIN_CFG.zero = 1) 1.0 AVDD V
203 Vos() Input Referenced Offset Voltage ±20 mV
204 Ilk() Input Leakage Current ±50 nA
205 OFFcorr Correctable Input Offset Voltage
As percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplier offset (item 105);
±100 %
(step size 60 mV / gain)

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 10/28
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
206 Rin()diff Differential Input Resistance MAIN_CFG.zero = 0 10 1000 MΩ
MAIN_CFG.zero = 1 0.620 MΩ
Converter Performance
304 INL Integral Nonlinearity (over one
input SIN/COS cycle)
Refer to Figure 5, 1 Vpp-diff SIN/COS input
with compensated offset, gain and phase
0.2 °
305 DNL Differential Nonlinearity (over one
input SIN/COS cycle
Refer to Figure 5, 1 Vpp-diff SIN/COS input
with compensated offset, gain and phase
0.1 °
307 tAB Output Phase A vs. B Refer to Figure 4 25 %
308 twhi Duty Cycle at Output A, B Refer to Figure 4 50 %
309 AArel Relative Angle Accuracy Refer to Figure 4, at conditions of 305 2 %
310 tMTD Time Between AB Edges
(Minimum Transition Distance)
Refer to Figure 4, ABLIMIT = 0 1/fosc 20 ns
Internal Oscillator
401 fosc Oscillator Frequency Tj = 27 °C; AVDD, DVDD = 3.1 V 48 51 MHz
AVDD, DVDD = 3.6 V 48 52 MHz
402 TCf Temperature Coefcient 225 ppm/K
Internal EEPROM
501 Nwrite Permissible Number of Write
Cycles
Tj = –40 °C...85 °C 1000
502 Tjw Write Temperature Range –40 85 °C
503 Tjr Read Temperature Range –40 125 °C
504 DRTraw Raw Data Retention Time 10 years
505 DRTact Actual Data Retention Time (with
error correction)
Tj = 85 °C 50 years
Reset and Start-Up: xRST
601 DVDDonoff DVDD Power-On/Off Threshold xRST tied to DVDD 2.5 2.7 3.0 V
603 tstart Startup Time Valid EEPROM conguration, START.wait = 0 2 ms
Digital Input Pins: xRST, xCALIB, A+/– (Encoder Link active), A– and B– (BiSS mode), SI, SCLK, xSS,GPIO, BISSEN
701 Vt()hi Input Logic Threshold High DVDD = 3.6 V 1.9 V
702 Vt()lo Input Logic Threshold Low DVDD = 3.3 V 0.8 V
703 Ilk() Input Leakage Current at
SI, SCLK, xSS
±50 nA
704 f(SCLK) Permissible SPI Clock Frequency
at SCLK
TEST.spi = 0 20 MHz
TEST.spi = 1 40 MHz
705 tRQ Request Time at MA (A+) BiSSEN = high; for SSI data output to SLO, 24 / fosc
see Figure 9
Digital Output Pins: xIRQ, SO, A+/A–, B+/B–, Z+/Z– (CMOS drivers enabled: MAIN_CFG.rs422 = 0), Z– (BiSS mode)
801 I()max Permissible Output Current Per pin, indenite ±10 mA
802 Vout()hi Output Voltage High I() = –4 mA, 2.4 V
MAIN_CFG.irqpp = 1 (for xIRQ push-pull)
803 Vs()hi Saturation Voltage High Vs()hi = IOVDD - V(); I() = -4 mA, 0.7 V
MAIN_CFG.irqpp = 1 (for xIRQ push-pull)
804 Vs()lo Saturation Voltage Low I() = 4 mA 0.7 V
805 Isc()hi Short-Circuit Current High Any pin shorted to DVSS –30 –16 mA
806 Isc()lo Short-Circuit Current Low Any pin shorted to DVDD 16 30 mA
807 tr() Rise Time DVDD = 3.3 V, CL = 50 pF, 10% →90% VDD 20 ns
808 tf() Fall Time DVDD = 3.3 V, CL = 50 pF, 10% →90% VDD 20 ns
809 tout() Slave Timeout at SLO (B+) BiSSEN = high; for BiSS & SSI, see Figure 11;
BiSS_CFG0.at = 0 (xed) 1024
/ fosc
BiSS_CFG0.at = 1 (adaptive) 8 / fosc tinit + 1024
4 / fosc / fosc

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iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 11/28
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
RS422 Drivers: A+/A–, B+/B–, Z+/Z– (RS422 drivers enabled: MAIN_CFG.rs422 = 1)
901 Idrv() Nominal RS422 Driver Current RL() = 120 Ωbetween + and – terminals 20 27 mA
902 Isc()hi Short Circuit Current High + or – pin shorted to IOVSS –55 mA
903 Isc()lo Short-Circuit Current Low + or – pin shorted to IOVDD 35 mA
LED Output (enabled: LED_CFG.en = 1)
A01 I()max Permissible Output Current for continuous operation ±15 mA
A02 Vout()hi Output Voltage High VDD = 3.3 V, Tj = 27 °C, I() = –10 mA 2.7 V
A03 Vs()hi Saturation Voltage High Vs()hi = DVDD – V(LED); I() = –10 mA 1 V
A04 Vs()lo Saturation Voltage Low I() = 10 mA 1 V
A05 Isc()hi Short-Circuit Current High LED pin shorted to DVSS –40 mA
A06 Isc()lo Short-Circuit Current Low LED pin shorted to DVDD 40 mA
Bias Outputs: VC, VREF
B01 VC Bias Voltage VC I(VC) = 0 50 %AVDD
B02 dVREF ADC Reference Voltage VREF
versus VC
dVREF = V(VREF) - V(VC); I(VREF) = 0 –1.1 –1 –0.9 V
Temperature Sensor
C01 Tacc Temperature Sensor Accuracy ±5°C
Tj = 100 °C±2°C
0 V
AVDD
MAIN_CFG.input = 2
AVDD
SIN– or COS–
SIN+ or COS+
0.35 V
0 V
0.35 V
1.1 V
1.1 V
0 V
AVDD
AVDD
SIN– or COS–
SIN+ or COS+
0.35 V
0 V
0.35 V
MAIN_CFG.input = 3
AVDD
– 1.1
AVDD
– 1.1
AVDD –
1.1
AVDD –
1.1
1.0 V
1.0 V
MAIN_CFG.input
= 0 or 1
Figure 1: Input Voltage Range (Vin())

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 12/28
SIN+%
COS+%
SIN–%
COS–%
0 V
Maximum Input Voltage
Minimum Input Voltage
Max. Input
Amplitude
(700 mV)
0 V
Maximum Input Voltage
Maximum
Input
Amplitude
(2 V)
SIN+%
COS+%
SIN–%
COS–%
Low Input Range
(MAIN_CFG.input = 0 or 1)
High Input Range
(MAIN_CFG.input = 3)
2.2 V
0.35 V
AVDD AVDD
1.0 V Minimum Input Voltage
Figure 2: Differential Input Amplitude (Ain()diff), Max(SIN+ – SIN–) or Max(COS+ – COS–)
0 V
1.85 V
0.7 V
2.2 V
0.35 V
AVDD
Minimum
Gain
Maximum
Gain
MAIN_CFG.input ≠3 or
MAIN_CFG.zero = 0
MAIN_CFG.input = 3 or
MAIN_CFG.zero = 1
0 V
2.0 V
1.0 V
AVDD
Minimum
Gain
Maximum
Gain
Figure 3: Input Common Mode Range, (SIN+ + SIN–)/2, (COS+ + COS–)/2, or (ZERO+ + ZERO–)/2
A
B
tMTD
twhi
T (100 %)
AArel
tAB
ABrel
Figure 4: Description of AB output signals
0° 360°180°
Converter
Error
INL: The maximum absolute error.
DNL: The maximum step
between two consecutive
samples.
Ideal converter
Actual converter
Angular Position
Figure 5: Denition of integral and differential nonlin-
earity

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 13/28
OPERATING REQUIREMENTS: SPI Interface
Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C
Item Symbol Parameter Conditions Unit
No. Min. Max.
SPI Interface Timing
I001 tC1 Permissible Clock Cycle Time
(See spec. item 704)
TEST.spi = 0 50 ns
TEST.spi = 1 25 ns
I002 tD1 Clock Signal Lo Level Duration TEST.spi = 0 15 ns
TEST.spi = 1 7.5 ns
I003 tD2 Clock Signal Hi Level Duration TEST.spi = 0 15 ns
TEST.spi = 1 7.5 ns
I004 tS1 Setup Time:
xSS lo before SCLK lo →hi
80 ns
I005 tH1 Hold Time:
xSS lo after SCLK hi →lo
50 ns
I006 tW1 Wait Time: between
xSS lo →hi and xSS hi →lo
200 ns
I007 tS2 Setup Time:
SI stable before SCLK lo →hi
5 ns
I008 tH2 Hold Time:
SI stable after SCLK lo →hi
10 ns
I009 tP1 Propagation Delay:
SO stable after xSS hi →lo
60 ns
I010 tP2 Propagation Delay:
SO high impedance after xSS lo →hi
25 ns
I011 tP3 Propagation Delay:
SO stable after SCLK hi →lo
20 ns
xSS
SCLK
SI
SO
tW1
tD1
tD2
tS1
TSI(hold)
TSI(set)
TSO(prop)
tH1
TSO(float)
Hi-Z
Figure 6: SPI Timing

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 14/28
OPERATING REQUIREMENTS: Encoder Link Interface
Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C
Item Symbol Parameter Conditions Unit
No. Min. Max.
Encoder Link Activation Sequence Timing
I101 T1 Activation Sequence Interval 1 A+ > 2.4 V, A– > 2.4 V 0.25 2 ms
I102 T2 Activation Sequence Interval 2 A+ < 0.8 V, A– > 2.4 V T1 – 10% T1 + 10% ms
I103 T3 Activation Sequence Interval 3 A+ < 0.8 V, A– < 0.8 V T1 – 10% T1 + 10% ms
I104 T4 Activation Sequence Interval 4 A+ > 2.4 V, A– < 0.8 V T1 – 10% T1 + 10% ms
Encoder Link Interface Timing (after activation)
I105 fclk(A+) ELink Clock Frequency Signal driven into A+ 1.0 MHz
I106 tD1(A+) ELink Clock Signal Hi Level Duration Signal driven into A+ 200 ns
I107 tD2(A+) ELink Clock Signal Lo Level Duration Signal driven into A+ 200 ns
I108 tS(A–) ELink Input Setup Time Signal driven into A– 200 ns
I109 tH(A–) ELink Input Hold Time Signal driven into A– 200 ns
I110 tP(A–) ELink Output Propagation Delay Signal driven out on A– 200 ns
A+
A–
External driver starts to overpower iC-
TW29 by forcing A+ and A– high.
T1
0.25–2 ms
T2
T1 ±10%
T3
T1 ±10%
T4
T1 ±10%
iC-TW29 stops driving A+ and A–.
Encoder Link interface is now active.
Normal operation. iC-TW29 is driving
quadrature signals on A+ and A–.
Figure 7: Encoder Link Activation Sequence
ELCLK (A+)
ELIN (A–)
ELOUT (A–)
TELCLK(high)
TELCLK(low)
TELIN(hold)
TELIN(set)
TELOUT(prop)
Figure 8: Encoder Link Read and Write Timing

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 15/28
OPERATING REQUIREMENTS: BiSS Interface
Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C
Item Symbol Parameter Conditions Unit
No. Min. Max.
SSI protocol (BiSSEN pin high and BISS_CFG0.ssi = 1)
I201 tframe Permissible Frame Repetition * indenite
I202 tCPermissible Clock Period With tRQ according to I205 250 ns
I203 tL1 Clock Signal Hi-Level Duration 125 tout ns
I204 tL2 Clock Signal Lo-Level Duration 125 tout ns
I205 tRQ Request Time Clock low-level duration at MA input (due to
Elec. Char. 705)
500 ns
I206 tP3 Output Propagation Delay 50 ns
I207 tout Slave Timeout see Elec. Char. 809
BiSS C protocol (BiSSEN pin high and BISS_CFG0.ssi = 0)
I208 tframe Permissible Frame Repetition * indenite
I209 tCPermissible Clock Period 100 ns
I210 tL1 Clock Signal Hi-Level Duration 50 tout ns
I211 tL2 Clock Signal Lo-Level Duration 50 tout ns
I212 tbusy Processing Time 240 ns
I213 tP3 Output Propagation Delay 50 ns
I214 tout Slave Timeout see Elec. Char. 809
I215 tS1 Setup Time:
SLI stable before MA hi →lo
25 ns
I216 tH1 Hold Time: SLI stable after MA hi →lo 10 ns
Note: * Allow tout to elapse.
tP3
DATA
tC
DATA
tout
tframe
tL2 tRQ
DATADATADATA
MA
SLO
tL1
Figure 9: SSI protocol timing
MA
SLO
tC
DATA
tframe
tL2 tL1
ACK
tbusy tout
tP3
START
START DATAACK
SLI
tS1 tH1
Figure 10: BiSS protocol timing
SLO
MA
tinit tout
Figure 11: BiSS slave timeout

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 16/28
OPERATING REQUIREMENTS: ADI Interface
Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C
Item Symbol Parameter Conditions Unit
No. Min. Max.
BiSS Protocol (ADI_CFG.biss = 1)
I301 tframe Clock Frame Repetition Note: This value can vary during operation. 1 3 ms
I302 tCClock Period ADI_CFG.freq = 0 5.9 7.7 µs
ADI_CFG.freq = 1 0.59 0.77 µs
I303 tL1, tL2 Clock Signal Hi/Lo Level Duration 50 % tC
I304 tbusy Permissible Processing Time relative to clock period ∞% tC
I305 tP0 Permissible Propagation Delay
(Line Delay Compensation)
not supported
(data is captured on next rising clock edge)
0 ns
I306 ∆tPPermissible Propagation Delay
Variance
not supported (refer to tSand tH) % tC
I307 tSSetup Time:
Data stable before clock edge lo →hi
without line delay compensation (tP0 = 0) 100 ns
I308 tHHold Time:
Data stable after clock edge lo →hi
without line delay compensation (tP0 = 0) 0 ns
I309 tout Permissible Slave Timeout tCµs
SSI Protocol (ADI_CFG.biss = 0)
I310 tframe Clock Frame Repetition Note: This value can vary unpredictably during
operation.
1 3 ms
I311 tCClock Period ADI_CFG.freq = 0 5.9 7.7 µs
ADI_CFG.freq = 1 0.59 0.77 µs
I312 tL1, tL2 Clock Signal Hi/Lo Level Duration 50 % tC
I313 tSSetup Time:
Data stable before clock edge lo →hi
100 ns
I314 tHHold Time:
Data stable after clock edge lo →hi
0 ns
I315 tout Permissible Slave Timeout tCµs
Clk Out (A-)
Data In (B-)
tH
START DATA
tC
tS
DATA
tout
tframe
tL2 tL1
ACK
tbus
tP0
Figure 12: ADI timing with BiSS protocol
tH
DATA
tC
tS
DATA
tout
tframe
tL2 tL1
DATADATADATA
Clk Out (A-)
Data In (B-)
Figure 13: ADI timing with SSI protocol

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 17/28
FUNCTIONAL BLOCK DIAGRAM
Interpolated Angle (IA)
SPI
Interface
xSS
SCK
SO
SI
Interpolator
ZERO
Channel
SIN+
SIN–
COS+
COS–
ZERO+
ZERO–
26-Bit
Gearbox
Includes
Filter,
Hysteresis,
and
Eccentricity
Correction
Zero Gating Window (ZW)
ABZ with
Output Freq.
Limiter
Normalized Angle (NR)
Revolution Count (RC)
UVW
BiSS Slave
with Encoder
Profile and
EDS
UVW Scan
Absolute Data
Interface
(ADI)
Revolution Count (RC),
Cycle Count (CC), and Sync Bits
I/O
Multiplexer
A+
A–
B+
B–
Z+
Z–
Auto Calibration,
Auto Adaption,
LED Control, Startup,
ID, EEPROM
xCALIBxIRQ LED
Position
Capture
BiSS Control Data
Encoder Link
Monitors:
Status/Fault, Temp.,
Sin/Cos Amplitude,
Excessive Error,
Excessive Adaption
GPIO
IA
CC
RC
Figure 14: Functional Block Diagram
The iC-TW29 uses a modular architecture as shown in
Figure 14.
Differential sine and cosine sensor signals are con-
verted to a 14-bit interpolated angle (IA) within one
input cycle by the interpolator. The interpolator also
provides complete analog and digital error correction
for the input signals to ensure lowest angular error and
jitter. A sophisticated digital lter with xed or variable
bandwidths improves performance with noisy inputs.
The zero channel generates the zero gating window
(ZW) from analog or digital zero or index sensors which
can be used to generate a traditional once-per-revo-
lution Z output. The ZERO input can also be used to
reset the gearbox counter and to capture the current
full absolute position of the iC-TW29.
The gearbox tracks the input cycles within a revolution
and provides a normalized 26-bit output representing
the angle within one output revolution (NR). This is
synchronized with the revolution count (RC) and the
cycle count (CC) from the absolute data interface (ADI)
or SPI port to form the complete absolute position. A
programmable noise and jitter lter increases angle res-
olution by two or more bits depending on conguration.
Hysteresis and eccentricity correction
The full absolute position value of the iC-TW29 can be
captured and read out over the SPI port. This posi-
tion capture takes place on the rising edge of the zero
gating window and can also be congured to generate
an interrupt. The most recent four absolute position
values are saved in a FIFO. This allows touch-probe or
distance-coded index applications to be easily imple-
mented.
Traditional encoder quadrature (ABZ) outputs are avail-
able as RS-422 compatible differential or single-ended
signals depending on device conguration. The ABZ
output resolution (edges or AB cycles per revolution) is
programmable and independent of the input resolution
(input cycles per revolution). The zero gating window
(ZW) from the zero signal path can be used to gener-
ate a programmable-width Z output synchronized with
the AB outputs. The Z output can also be synthesized
from absolute position data when the ZERO input is not
used.
The ABZ output module incorporates a programmable
AB output frequency limiter that guarantees a minimum
separation time between AB edges. This is useful to
avoid counting errors with PLCs or counters with input
frequency limits less than the 12.5 MHz maximum AB
output frequency of the iC-TW29.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 18/28
When the AB output frequency is being limited, the AB
outputs lag behind the sin/cos inputs. If this condition is
temporary or transient, the AB outputs catch up when
the limiter is no longer active. If this condition persists,
however, a fatal fault is generated and the iC-TW29
stops operating. The AB output frequency limiter can
also be programmed to activate xIRQ.
3-phase UVW outputs for commutation of brushless
motors with up to 64 poles (32 pole pairs) per revolution
are also available as RS-422 compatible differential or
single-ended signals depending on device congura-
tion.
A BiSS Slave interface provides BiSS C-Mode bidirec-
tional communication of output angle (with indepen-
dently programmable resolution), revolution count, and
conguration data. Encoder Proles 3, 3S (Safety), and
4 are implemented in the iC-TW29 or a custom prole
may be dened using a host processor. BiSS com-
mand requests are handled directly by the iC-TW29 for
stand-alone applications or can be passed through to
an external microprocessor via the SPI port in hosted
applications.
The BiSS interface can be congured to implement
BiSS Standard Encoder Electronic Data Sheet (EDS)
SE. This allows the BiSS master to read the encoder
conguration over the BiSS interface at startup. In
hosted applications, the host processor can implement
any BiSS EDS.
UVW scan mode allows external UVW signals to be
read by the iC-TW29 and sent to the BiSS master with
the BiSS single cycle data (BP4 or custom encoder pro-
le only). This allows commutation of a brushless motor
over BiSS before absolute position is synchronized.
The absolute data interface (ADI) is a BiSS/SSI master
for reading revolution and cycle count information from
an external absolute position system (such as iC-PVL).
Up to four synchronization bits can be used.
The I/O multiplexer determines which signals are trans-
ferred to the output pins. One of 23 output modes
(combinations of output types) can be selected. Up to
two different output types may be used simultaneously.
The SPI port is available for use by an external host
processor for initial calibration or general communica-
tion.
The iC-TW29 provides comprehensive monitoring func-
tions for status and faults, chip temperature and sin/cos
input signal quality.
The status/fault monitor monitors 16 internal conditions,
each of which can be individually congured to activate
a fault output to notify an external system during opera-
tion. The fault output is the active-low interrupt request
output (xIRQ) pin. In stand-alone applications, xIRQ
can be used to directly drive a fault LED. In hosted
applications, xIRQ is typically used to interrupt the host
when a fault occurs. In addition, real-time status and
fault information is available over the SPI and BiSS
interfaces.
The iC-TW29 incorporates an on-chip temperature sen-
sor. The temperature monitor can provide real-time
chip temperature data to a host processor or BiSS mas-
ter. The temperature monitor can be congured to
activate a status bit when chip temperature exceeds a
programmable limit. This condition can also activate
xIRQ.
The sin/cos amplitude monitor continuously monitors
the amplitude of the sin/cos input signals by calculating
the quantity
√sin2+cos2
. If the input amplitude is out-
side congured limits, a status bit is activated and an
interrupt can be generated.
The excessive error monitor continuously calculates
the residual offset, balance, and phase error of the cor-
rected sin/cos signals. These residues represent the
uncorrected signal error of the sin and cos channels,
and are typically zero (or near zero) when auto adaption
is used. If any of the error residues exceeds congured
limits, a status bit is set and an interrupt can be gen-
erated. In applications where auto adaption cannot be
used, the residues allow sensor signal quality to be
monitored by a host processor.
The excessive adaption monitor continuously compares
the current offset, balance, and phase correction pa-
rameter values to baseline values store in the EEPROM
during device conguration. If any of the correction val-
ues deviate from the base values (due to auto adaption)
by more than the congured limits, a status bit is set
and an interrupt can be generated.
Auto calibration is used at initial device commissioning
to automatically determine gain, offset, channel bal-
ance, and phase compensation values for the sin, cos,
and zero channels. Auto calibration is initiated using
the xCALIB input pin or via a serial command. Cali-
brated values can be stored in the internal EEPROM
for use on subsequent startups.
Auto adaption maintains optimal offset, channel bal-
ance, and phase compensation values for the sin and
cos channels during operation to ensure maximum in-
terpolator accuracy and lowest jitter under all operating
conditions.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 19/28
A congurable LED intensity control uses the calcu-
lated sin/cos amplitude value to control the intensity of
an optical sensor LED via the pulse-width modulated
LED output (pin 26). This maintains the sin/cos signals
at their calibrated amplitude in the presence of LED
ageing and varying application conditions.
Device startup can proceed automatically for
stand-alone applications or under the control of a host
processor in hosted applications. In general, outputs
are not enabled until the appropriate position (relative
or absolute) is established.
Device and chip identication is provided in the form
of a unique factory-programmed chip serial number as
well as a chip ID and revision code. In BiSS applica-
tions, user-programmable manufacturer ID, product ID,
device serial number, and production date are avail-
able.
The iC-TW29 incorporates an internal write-protected
EEPROM to store conguration and initial calibration
data for use at startup. In addition to a standard check-
sum on the EEPROM data, sophisticated data encoding
allows detection and correction of single-bit errors and
detection of two-bit errors for enhanced application se-
curity. The EEPROM can be unlocked using the SPI,
BiSS, or encoder link interfaces.
The Encoder Link interface provides read/write access
to the iC-TW29’s internal registers using the A+ and A–
outputs in ABZ or UVW output modes. This is useful for
eld reconguration or diagnostics of products incorpo-
rating the iC-TW29. Encoder Link can only be used for
conguration and diagnostics, it cannot be used to read
position. Encoder Link can be disabled to eliminate
tampering with nished products.

preliminarypreliminary
iC-TW29 26-BIT ENCODER PROCESSOR
WITH INTERPOLATION AND BiSS INTERFACE
Rev C1, Page 20/28
ELECTRICAL CONNECTIONS
The basic electrical connections for an incremental
stand-alone application with differential ABZ outputs
are shown in Figure 15. Other than the sin/cos sensor,
only a few bypass capacitors and other components
are required for operation.
Application Hint
The input voltages must not exceed the chip’s supply
voltage (3.3 V).
VREF
VC
100
nF
1µF
AVDD
AVSS
3.3V
SIN+
SIN–
COS+
COS–
Sensor
iC-TW29
xSS
SCLK
SI
SO
SPI
Configuration
Port
xCALIB
Calibration
Button
100
nF
1µF
IOVDD
3.3V
IOVSS
A+
A–
B+
B–
Z+
Z–
1µF
DVDD
DVSS
3.3V
BISSEN
ZERO+
ZERO–
xRST
3.3V
xIRQ
Fault LED
Differential
RS422
ABZ Outputs
GPIO
RESERVED
RESERVED
3.3V
120 Ω
120 Ω
120 Ω
xSS
SCLK
MOSI
MISO
3.3V
Figure 15: Typical Electrical Connections For Incremental Stand-Alone Application