Analog Devices ADV7604 User manual

ADV7604
Component/Graphics Digitizer with 4:1
Multiplexed HDMI Receiver
Hardware Manual
Rev. F
August 2010

ADV7604
Rev. F August 2010 2
Table of Contents
1INTRODUCTION TO ADV7604 HARDWARE MANUAL................................................................................. 8
1.1 ADV7604 DOCUMENTATION SET ...................................................................................................................... 8
1.2 DESCRIPTION OF ADV7604 HARDWARE MANUAL............................................................................................. 8
1.3 DISCLAIMER ....................................................................................................................................................... 8
1.4 NUMBER NOTATIONS ......................................................................................................................................... 8
1.5 REGISTER ACCESS CONVENTIONS ...................................................................................................................... 9
1.6 ACRONYMS AND ABBREVIATIONS ...................................................................................................................... 9
1.7 FIELD FUNCTION DESCRIPTION ........................................................................................................................ 10
1.8 REFERENCES..................................................................................................................................................... 11
2INTRODUCTION................................................................................................................................................... 13
2.1 ANALOG FRONT END........................................................................................................................................ 13
2.2 HDMI RECEIVER.............................................................................................................................................. 13
2.3 COMPONENT PROCESSOR ................................................................................................................................. 14
2.4 MAIN FEATURES OF ADV7604 ........................................................................................................................ 15
2.4.1 Analog Front End ....................................................................................................................................... 15
2.4.2 HDMI Receiver........................................................................................................................................... 15
2.4.3 Video Output Formats................................................................................................................................. 15
2.4.4 Component Video Processing..................................................................................................................... 15
2.4.5 RGB Graphics Processing.......................................................................................................................... 16
2.4.6 Additional Features .................................................................................................................................... 16
2.5 FUNCTIONAL BLOCK DIAGRAM........................................................................................................................ 17
2.6 PIN DESCRIPTIONS............................................................................................................................................ 18
3GLOBAL CONTROL REGISTERS..................................................................................................................... 28
3.1 ADV7604 REVISION IDENTIFICATION .............................................................................................................. 28
3.2 POWER MODES ................................................................................................................................................. 28
3.2.1 Power-down Modes .................................................................................................................................... 28
3.2.2 Power-Save Mode....................................................................................................................................... 32
3.2.3 Secondary Power-Down Controls............................................................................................................... 33
3.2.4 ADC Power-Down Control......................................................................................................................... 35
3.3 RESET CONTROL............................................................................................................................................... 36
3.4 CRYSTAL FREQUENCIES OPERATION ................................................................................................................ 36
3.5 GLOBAL PIN CONTROL ..................................................................................................................................... 37
3.5.1 Tristate Pixel Bus Drivers........................................................................................................................... 37
3.5.2 Tristate LLC Driver .................................................................................................................................... 37
3.5.3 Tristate Synchronization Output Drivers.................................................................................................... 38
3.5.4 Tristate Audio Output Drivers .................................................................................................................... 38
3.5.5 Drive Strength Selection (Data).................................................................................................................. 39
3.5.6 Drive Strength Selection (Clock) ................................................................................................................ 40
3.5.7 Drive Strength Selection (Synchronization)................................................................................................ 40
3.5.8 Synchronization Output Selection............................................................................................................... 41
3.5.9 Synchronization Output Signals Polarity.................................................................................................... 42
3.6 DIGITAL SYNTHESIZER CONTROLS ................................................................................................................... 44
3.6.1 Clock Generation for Analog CP Control................................................................................................... 44
3.6.2 Phase Control ............................................................................................................................................. 45
3.7 DLL ON LLC CLOCK PATH .............................................................................................................................. 45
3.8 CP AND HDMI SIMULTANEOUS MODE ............................................................................................................ 46
3.9 PIN CHECKER ................................................................................................................................................... 47
4PRIMARY MODE AND VIDEO STANDARD ................................................................................................... 49
4.1 PRIMARY MODE AND VIDEO STANDARD CONTROLS ........................................................................................ 49
4.2 SELECTING PRIMARY MODE AND VIDEO STANDARD FOR HDMI MODES ........................................................ 54
4.3 HDMI DECIMATION MODES ............................................................................................................................ 54
4.4 PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN ........................................... 55
4.5 RECOMMENDED SETTINGS FOR HDMI INPUTS ................................................................................................. 55

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5PIXEL PORT CONFIGURATION....................................................................................................................... 57
5.1 LLC CONTROL ................................................................................................................................................. 57
5.2 CP PIXEL PORT OUTPUT MODES ...................................................................................................................... 57
5.3 BUS ROTATION AND REORDERING CONTROLS ................................................................................................. 59
5.4 PIXEL DATA AND SYNCHRONIZATION SIGNALS CONTROL ............................................................................... 60
5.5 ROUNDING AND TRUNCATING DATA................................................................................................................ 61
5.6 DDR OUTPUT INTERFACE AND AV CODE REPETITION .................................................................................... 63
6ANALOG FRONT END......................................................................................................................................... 64
6.1 ADC SAMPLING CLOCK ADJUSTMENT ............................................................................................................. 64
6.2 ADCS AND VOLTAGE CLAMPS ......................................................................................................................... 64
6.2.1 ADC Power Control.................................................................................................................................... 64
6.2.2 ADC Input Range Control........................................................................................................................... 64
6.2.3 Clamping..................................................................................................................................................... 65
6.3 ANALOG INPUT MUXING .................................................................................................................................. 66
6.3.1 Analog Input Routing Recommendation ..................................................................................................... 66
6.3.2 Auto Configuration ..................................................................................................................................... 67
6.3.3 Recommended Analog Input Configurations .............................................................................................. 67
6.3.4 Manual Input Muxing ................................................................................................................................. 68
6.4 SYNC 1, SYNC 2, SYNC 3AND SYNC 4INPUT CONTROL ............................................................................. 70
6.4.1 Automatic Synchronization Configuration.................................................................................................. 71
6.4.2 Manual Synchronization Configuration...................................................................................................... 71
6.4.3 Manual Synchronization Application.......................................................................................................... 72
6.5 SYNCHRONIZATION STRIPPERS ......................................................................................................................... 73
6.5.1 Synchronization Filter Stage....................................................................................................................... 73
6.5.2 Sync Stripper Slice Level............................................................................................................................. 74
6.6 TRI 1-8 INPUT CONTROL ................................................................................................................................. 74
6.6.1 Description.................................................................................................................................................. 74
6.6.2 D-Terminal Connector................................................................................................................................ 75
6.6.3 SCART Connector....................................................................................................................................... 75
6.6.4 TRI 1-8 Input Resistor Selection................................................................................................................. 75
6.6.5 Trilevel Slicers............................................................................................................................................ 77
6.6.6 Trilevel Slicer Operation ............................................................................................................................ 78
6.6.7 Bilevel/Trilevel Selection ............................................................................................................................ 79
6.6.8 Trilevel Slicer Readbacks............................................................................................................................ 81
6.6.9 Slice Level Programming............................................................................................................................ 83
6.6.10 Trilevel Interrupts .................................................................................................................................. 87
6.7 ANTI ALIAS FILTERS ........................................................................................................................................ 88
6.7.1 Description.................................................................................................................................................. 88
6.7.2 Anti Alias Filter Control............................................................................................................................. 88
6.7.3 Anti Alias Filter Frequency Characteristics............................................................................................... 88
7HDMI RECEIVER ................................................................................................................................................. 90
7.1 5VCABLE DETECT .......................................................................................................................................... 90
7.2 EDID/REPEATER CONTROLLER........................................................................................................................ 92
7.3 ENHANCED-EXTENDED DISPLAY IDENTIFICATION DATA CONFIGURATION...................................................... 93
7.3.1 E-EDID Support for Power-down Mode 0.................................................................................................. 94
7.4 INTERNAL EDID............................................................................................................................................... 99
7.4.1 EDID RAM.................................................................................................................................................. 99
7.4.2 Structure of Internal E-EDID for Port A .................................................................................................. 101
7.4.3 Structure of Internal E-EDID of Ports B, C, and D.................................................................................. 102
7.5 EXTERNAL E-EDID........................................................................................................................................ 106
7.6 TRANSITION MINIMIZED DIFFERENTIAL SIGNALING EQUALIZATION.............................................................. 106
7.7 PORT SELECTION ............................................................................................................................................ 110
7.8 TMDS CLOCK ACTIVITY DETECTION ............................................................................................................ 110
7.9 CLOCK AND DATA TERMINATION CONTROL .................................................................................................. 111
7.10 TMDS MEASUREMENT .................................................................................................................................. 112
7.10.1 TMDS Measurement after TMDS PLL.................................................................................................112
7.10.2 TMDS Measurement Prior to TMDS PLL............................................................................................ 114
7.11 DEEP COLOR MODE SUPPORT ........................................................................................................................ 115

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7.12 VIDEO FIFO ................................................................................................................................................... 116
7.13 PIXEL REPETITION .......................................................................................................................................... 120
7.14 HDCP SUPPORT ............................................................................................................................................. 121
7.14.1 HDCP Decryption Engine.................................................................................................................... 121
7.14.2 Internal HDCP Key OTP ROM............................................................................................................ 122
7.14.3 HDCP Keys Access Flags.................................................................................................................... 122
7.15 HDMI SYNCHRONIZATION PARAMETERS....................................................................................................... 124
7.15.1 Horizontal Filters and Measurements.................................................................................................. 125
7.15.2 Horizontal Filter Locking Mechanism ................................................................................................. 125
7.15.3 Horizontal Filter Measurements.......................................................................................................... 125
7.15.4 Vertical Filters and Measurements...................................................................................................... 128
7.16 AUDIO CONTROL AND CONFIGURATION ......................................................................................................... 131
7.16.1 Audio DPLL ......................................................................................................................................... 132
7.16.2 Audio FIFO.......................................................................................................................................... 133
7.16.3 Audio Packet Type Flags...................................................................................................................... 135
7.16.4 Audio Output Controls......................................................................................................................... 137
7.16.5 MCLKOUT Setting............................................................................................................................... 138
7.16.6 Audio Channel Mode............................................................................................................................ 139
7.16.7 L-PCM and IEC 61937 Compressed Audio Interfaces ........................................................................ 139
7.16.8 DSD Interface....................................................................................................................................... 141
7.16.9 HBR Interface....................................................................................................................................... 143
7.16.10 Audio Muting........................................................................................................................................ 144
7.16.11 Audio Mute Configuration ................................................................................................................... 145
7.16.12 Audio Stream with Incorrect Parity Error ........................................................................................... 150
7.17 AUDIO CLOCK REGENERATION PARAMETERS ................................................................................................ 150
7.17.1 ACR Parameters Readbacks ................................................................................................................ 150
7.17.2 Monitoring ACR Parameters ............................................................................................................... 151
7.18 CHANNEL STATUS .......................................................................................................................................... 152
7.18.1 Validity Status Flag.............................................................................................................................. 152
7.18.2 General Control and Mode Information .............................................................................................. 154
7.18.3 Category Code ..................................................................................................................................... 155
7.18.4 Source Number and Channel Number.................................................................................................. 155
7.18.5 Sampling and Frequency Accuracy...................................................................................................... 155
7.18.6 Word Length......................................................................................................................................... 156
7.18.7 Channel Status Copyright Value Assertion.......................................................................................... 157
7.18.8 Monitoring Change of Audio Sampling Frequency.............................................................................. 157
7.19 PACKETS AND INFOFRAMES REGISTERS ......................................................................................................... 158
7.19.1 InfoFrames Registers ........................................................................................................................... 158
7.19.2 Packet Registers................................................................................................................................... 167
7.19.3 Customizing Packet/InfoFrame Storage Registers............................................................................... 172
7.20 REPEATER SUPPORT ....................................................................................................................................... 174
7.20.1 Repeater Routines Performed by the EDID/Repeater Controller ........................................................ 174
7.20.2 Repeater Actions Required by External Controller.............................................................................. 175
7.20.3 HDCP Registers Available in Repeater Map....................................................................................... 177
7.21 INTERFACE TO DPP SECTION.......................................................................................................................... 181
7.22 COLOR SPACE INFORMATION SENT TO THE DPP AND CP SECTIONS .............................................................. 183
7.23 STATUS REGISTERS ........................................................................................................................................ 184
7.24 HDMI SECTION RESET STRATEGY ................................................................................................................. 188
8DECIMATION AND COLOR SPACE CONVERSION................................................................................... 189
8.1 DATA PREPROCESSOR .................................................................................................................................... 189
8.2 DPP ENABLE CONTROL.................................................................................................................................. 189
8.3 DECIMATION FILTERS..................................................................................................................................... 190
8.3.1 DPP Automatic Selection.......................................................................................................................... 191
8.3.2 Decimation Filter Selection for Stage 1.................................................................................................... 191
8.3.3 Decimation Filter Selection for Stage 2.................................................................................................... 193
8.3.4 Chroma 4x Decimation Filter Selection in Stage 2................................................................................... 197
8.3.5 DPP Decimation Only Selection............................................................................................................... 198
8.4 COLOR SPACE CONVERSION MATRIX ............................................................................................................. 202
8.4.1 CP CSC or DPP CSC Selection................................................................................................................ 203

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8.4.2 Selecting Auto or Manual CSC Conversion Mode....................................................................................204
8.4.3 Auto Color Space Conversion Matrix....................................................................................................... 205
8.4.4 HDMI Auto CSC Operation...................................................................................................................... 208
8.4.5 Manual Color Space Conversion Matrix.................................................................................................. 211
8.4.6 CSC in Pass-through Mode....................................................................................................................... 216
8.5 COLOR CONTROLS.......................................................................................................................................... 217
9ENHANCED STANDARD DEFINITION PROCESSOR................................................................................. 218
9.1 BACKGROUND ................................................................................................................................................ 219
9.2 MODES OF OPERATION ................................................................................................................................... 219
9.3 DATAPATH SUMMARY.................................................................................................................................... 219
9.4 CLAMP AND GAIN........................................................................................................................................... 220
9.5 INPUT SIGNAL DETECTION ............................................................................................................................. 221
9.6 HSYNC SEPARATION ...................................................................................................................................... 221
9.7 VSYNC/FIELD SEPARATION............................................................................................................................ 221
9.8 OUTPUT TIMING SIGNALS............................................................................................................................... 222
9.9 BASIC CONTROL –ENABLING/DISABLING ESDP MODE ................................................................................ 223
9.10 NONSTANDARD SAMPLES PER LINE................................................................................................................ 224
9.11 ESDP FREE RUN MODE.................................................................................................................................. 225
10 COMPONENT PROCESSOR ............................................................................................................................. 226
10.1 INTRODUCTION TO COMPONENT PROCESSOR ................................................................................................. 226
10.2 CLAMP OPERATION ........................................................................................................................................ 227
10.3 CP GAIN OPERATION...................................................................................................................................... 230
10.3.1 Features of Manual Gain Control........................................................................................................ 230
10.3.2 Features of Automatic Gain Control.................................................................................................... 230
10.3.3 Manual Gain and Automatic Gain Control Selection .......................................................................... 231
10.3.4 Manual Gain Control........................................................................................................................... 233
10.3.5 Manual Gain Filter Mode.................................................................................................................... 235
10.3.6 Automatic Gain Control....................................................................................................................... 235
10.3.7 CP Peak Active Video Readback.......................................................................................................... 239
10.4 CP OFFSET BLOCK ......................................................................................................................................... 241
10.5 AV CODE BLOCK ........................................................................................................................................... 242
10.6 CP DATA PATH FOR ANALOG AND HDMI MODES ......................................................................................... 245
10.6.1 Pregain Block....................................................................................................................................... 245
10.7 SYNCHRONIZATION PROCESSED BY CP SECTION............................................................................................ 251
10.7.1 Sync Extracted by ESDP Block............................................................................................................ 251
10.7.2 Sync Extracted by Sync Slicer Section.................................................................................................. 252
10.7.3 External Sync and Sync from HDMI Section .......................................................................................253
10.7.4 Final Sync Muxing Stage...................................................................................................................... 256
10.8 SYNCHRONIZATION PROCESSING CHANNEL MUX .......................................................................................... 257
10.8.1 Synchronization Source Polarity Detector........................................................................................... 259
10.8.2 Standard Detection and Identification ................................................................................................. 267
10.8.3 Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism......................................... 270
10.9 CP OUTPUT SYNCHRONIZATION SIGNAL POSITIONING................................................................................... 277
10.9.1 CP Primary Synchronization Signals................................................................................................... 279
10.9.2 HSync Timing Controls........................................................................................................................ 279
10.9.3 VSync Timing Controls......................................................................................................................... 283
10.9.4 DE Timing Controls............................................................................................................................. 284
10.9.5 FIELD Timing Controls....................................................................................................................... 285
10.9.6 Secondary Synchronization Signals ..................................................................................................... 293
10.9.7 Ancillary Synchronization Signal Outputs ........................................................................................... 293
10.10 CP HORIZONTAL LOCK STATUS ..................................................................................................................... 296
10.11 NOISE AND CALIBRATION............................................................................................................................... 298
10.11.1 Measurement Window.......................................................................................................................... 298
10.11.2 Noise Measurement.............................................................................................................................. 298
10.11.3 Calibration Measurement .................................................................................................................... 299
10.12 CP HDMI CONTROLS..................................................................................................................................... 299
10.13 FREE RUN MODE ............................................................................................................................................ 300
10.13.1 Free Run Mode Thresholds.................................................................................................................. 300

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10.13.2 Free Run Feature in HDMI Mode........................................................................................................ 303
10.13.3 Free Run Default Color Output............................................................................................................ 304
10.14 CP STATUS ..................................................................................................................................................... 307
10.15 AUTO GRAPHICS MODE.................................................................................................................................. 308
10.15.1 Primary Auto Graphics Controls......................................................................................................... 308
10.15.2 Secondary Auto Graphics Control....................................................................................................... 309
10.15.3 Auxiliary Auto Graphics Controls........................................................................................................ 311
10.15.4 Setting Examples for 1280x720p.......................................................................................................... 312
10.16 EXTERNAL CLOCK AND CLAMP MODE OPERATION........................................................................................ 312
10.16.1 Introduction to External Clock and Clamp Mode ................................................................................ 312
10.16.2 Clamp Control...................................................................................................................................... 314
10.16.3 Configuring External Clock and Clamp Mode..................................................................................... 315
10.16.4 System Delay in ADV7604 ................................................................................................................... 320
11 VBI DATA PROCESSOR .................................................................................................................................... 322
11.1 VDP CONFIGURATION.................................................................................................................................... 322
11.1.1 VDP Default Configuration ................................................................................................................. 323
11.1.2 VDP Manual Configuration................................................................................................................. 324
11.2 FULL FIELD/FRAME DETECTION..................................................................................................................... 326
11.3 TELETEXT SYSTEM IDENTIFICATION............................................................................................................... 326
11.4 VDP CONFIGURATION.................................................................................................................................... 327
11.4.1 Hamming Code Error........................................................................................................................... 328
11.4.2 Adaptive Slice Level Generators.......................................................................................................... 331
11.5 VDP ANCILLARY DATA OUTPUT ................................................................................................................... 332
11.6 NIBBLE OUTPUT MODE .................................................................................................................................. 333
11.7 STRUCTURE OF VBI WORDS IN ANCILLARY DATA STREAM........................................................................... 335
11.7.1 Framing Code ...................................................................................................................................... 336
11.7.2 Data Bytes............................................................................................................................................ 337
11.8 READBACK REGISTERS................................................................................................................................... 338
11.9 USER INTERFACE FOR READBACK REGISTERS ................................................................................................ 338
11.9.1 Register Readback Protocol................................................................................................................. 338
11.9.2 Content Based Data Update................................................................................................................. 339
11.10 INTERRUPT BASED READING OF I2CREGISTERS ............................................................................................. 340
11.10.1 Interrupt Mask Register Details........................................................................................................... 341
11.10.2 Interrupt Status Register Details.......................................................................................................... 342
11.10.3 Interrupt Status Clear Register Details................................................................................................ 343
11.11 I2CREADBACK REGISTERS............................................................................................................................. 343
11.11.1 Teletext................................................................................................................................................. 343
11.11.2 CGMS and WSS.................................................................................................................................... 344
11.11.3 CCAP ................................................................................................................................................... 345
11.11.4 VITC..................................................................................................................................................... 346
11.11.5 VPS, PDC, UTC, GemStar, and CGMS Type B ................................................................................... 347
12 CUSTOMER ELECTRONIC CONTROL......................................................................................................... 351
12.1 MAIN CONTROLS............................................................................................................................................ 352
12.2 CEC TRANSMIT MODULE............................................................................................................................... 352
12.3 CEC RECEIVER MODULE ............................................................................................................................... 356
12.4 CLOCK GENERATOR MODULE ........................................................................................................................ 358
12.5 ANTIGLITCH FILTER MODULE ........................................................................................................................ 359
12.6 TYPICAL OPERATION FLOW............................................................................................................................ 359
12.6.1 Initializing CEC Module ...................................................................................................................... 359
12.6.2 Using CEC Module as Initiator............................................................................................................ 360
12.6.3 Using CEC Module as Follower.......................................................................................................... 361
13 AV.LINK BUS INTERFACE............................................................................................................................... 362
13.1 MAIN CONTROLS............................................................................................................................................ 363
13.2 AV.LINK TRANSMIT MODULE ........................................................................................................................ 363
13.3 AV.LINK RECEIVE MODULE ........................................................................................................................... 366
13.4 CLOCK GENERATOR MODULE ........................................................................................................................ 370
13.5 AV.LINK ANTIGLITCH FILTER ........................................................................................................................ 370

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13.6 FORMAT DESCRIPTION OF TRANSMITTED FRAMES ......................................................................................... 370
13.6.1 Mode 1.................................................................................................................................................. 371
13.6.2 Mode 2.................................................................................................................................................. 371
13.6.3 Mode 3.................................................................................................................................................. 371
13.7 MODE DETECTION .......................................................................................................................................... 372
13.8 ESC/DIR BIT VALIDATION ............................................................................................................................ 373
14 INTERRUPTS ....................................................................................................................................................... 374
14.1 INTERRUPTS.................................................................................................................................................... 374
14.1.1 Interrupt Request Output Operation .................................................................................................... 374
14.1.2 Interrupt Drive Level............................................................................................................................ 375
14.1.3 Interrupt Manual Assertion.................................................................................................................. 375
14.1.4 Multiple Interrupt Events ..................................................................................................................... 375
14.1.5 HDMI Interrupts Validity Checking Process.......................................................................................376
14.1.6 Storing Masked Interrupts.................................................................................................................... 379
14.1.7 Processing AFE Interrupts................................................................................................................... 380
15 HARDWARE DESIGN ........................................................................................................................................ 382
15.1 POWER SUPPLY SEQUENCE............................................................................................................................. 382
16 REGISTER ACCESS AND SERIAL PORTS DESCRIPTION ....................................................................... 383
16.1 MAIN I2CPORT............................................................................................................................................... 383
16.1.1 Register Access..................................................................................................................................... 383
16.1.2 Protocol for Main I2C Port .................................................................................................................. 384
16.2 DDC PORTS.................................................................................................................................................... 385
16.2.1 I2C Protocols for Access to the Internal EDID .................................................................................... 385
16.2.2 I2C Protocols for Access to HDCP Registers....................................................................................... 386
16.2.3 DDC Port A.......................................................................................................................................... 386
16.2.4 DDC Port B.......................................................................................................................................... 386
16.2.5 DDC Port C ......................................................................................................................................... 387
16.2.6 DDC Port D ......................................................................................................................................... 387
APPENDIX A.................................................................................................................................................................. 389
PCB LAYOUT RECOMMENDATIONS .............................................................................................................................. 389
ANALOGUE INTERFACE INPUTS .................................................................................................................................... 389
POWER SUPPLY BYPASSING .......................................................................................................................................... 389
HDMI INPUTS............................................................................................................................................................... 390
DIGITAL OUTPUTS (DATA AND CLOCKS)...................................................................................................................... 390
DIGITAL INPUTS............................................................................................................................................................ 391
XTAL AND LOAD CAP VALUE SELECTION ................................................................................................................... 391
APPENDIX B.................................................................................................................................................................. 393
RECOMMENDED CONFIGURATION FOR UNUSED PINS ................................................................................................... 393
APPENDIX C.................................................................................................................................................................. 400
PACKAGE OUTLINE DRAWING ...................................................................................................................................... 400
ORDERING GUIDE ......................................................................................................................................................... 400
LIST OF FIGURES........................................................................................................................................................ 401
LIST OF TABLES.......................................................................................................................................................... 403
LIST OF EQUATIONS.................................................................................................................................................. 405
DOCUMENT REVISION HISTORY........................................................................................................................... 406

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1Introduction to ADV7604 Hardware Manual
1.1 ADV7604 Documentation Set
The ADV7604 documentation set consists of the following manuals:
•ADV7604 Preliminary Datasheet
•ADV7604 Hardware Manual
•ADV7604 Software Manual
1.2 Description of ADV7604 Hardware Manual
This manual provides a detailed description of the functionality and features of the
Component/Graphic Digitizer and quad HDMI receiver section of the ADV7604.
1.3 Disclaimer
The information contained in this document is proprietary of Analog Devices Inc. (ADI). This
document must not be made available to anybody other than the intended recipient without the
written permission of ADI. No liability whatsoever is accepted for any undesired behavior of the
information provided in this document.
The content of this document is believed to be correct. If any errors are found within this document
or if clarification is needed, contact the authors at [email protected].
1.4 Number Notations
Notation Description
bit N Bits are numbered in little endian format, that is,
the least significant bit of a number is referred to
as bit 0
V[X:Y] Bit field representation covering bit X to Y of a
value or a field V
0xNN Hexadecimal (base-16) numbers are preceded by
the prefix ‘0x’
0bNN Binary (base-2) numbers are preceded by the
prefix ‘0b’
NN Decimal (base-10) are represented using no
additional prefixes or suffixes

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1.5 Register Access Conventions
Mode Description
R/W Memory location has read and write access.
Read only Memory location is read access only. A read
always returns 0 unless specified otherwise.
Write only Memory location is write access only.
1.6 Acronyms and Abbreviations
Acronym/Abbreviation Description
ACP Audio Content Protection
ADC Analog to Digital Converter
AFE Analog Front End
AGC Automatic Gain Control
AVI Auxiliary Video Information
BGA Ball Grid Array
CP Component Processor
CSC Color Space Converter/Conversion
CSync Composite Synchronization
DID Data Identification Word
DCM Decimation
DDR Double Data Rate
DDFS Direct Digital Frequency Synthesizer
DE Data Enable
DLL Delay Locked Loop
DPP Data Preprocessor
DSD Direct Stream Digital
DST Direct Stream Transport
DVI Digital Visual Interface
DUT Device Under Test (designate the ADV7604 unless stated
otherwise)
EAV End of Active Video
ECT Extended Command Table
ED Enhanced Definition
E-EDID Enhanced-Extended Display Identification Data
Configuration
EMC Electromagnetic Compatibility
EOM End of Message
EQ Equalizer
HD High Definition
HDCP High Bandwidth Digital Content Protection
HDMI High Bandwidth Multimedia Interface
HDTV High Definition Television
HSync Horizontal Synchronization
IC Integrated Circuit
ISRC International Standard Recording Code

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Acronym/Abbreviation Description
I2S Inter IC Sound
I2C Inter Integrated Circuit
KSV Key Selection Vector
LLC Line Locked Clock
LSB Least Significant Bit
Mbps Megabit per Second
MPEG Moving Picture Expert Group
ms Millisecond
MSB Most Significant Bit
OTP One Time Programmable
Rx Receiver
SA Slave Address
SAV Start of Active Video
SD Standard Definition
SMPTE Society of Motion Picture and Television Engineers
SNR Signal to Noise Ratio
SDR Single Data Rate
SOG Sync on Green
SOY Sync on Y
SPA Source Physical Address
SPD Source Production Descriptor
SSPD Synchronization Source Polarity Detector
STDI Standard Identification
TMDS Transition Minimized Differential Signaling
Tx Transmitter
US Up Sampling
VBI Video Blanking Interval
VDP VBI Data Processor
VSync Vertical Synchronization
XTAL Crystal Oscillator
1.7 Field Function Description
The function of a field is described in a table preceded by the bit name, a short function description,
the I2C map, the register location within the I2C map, and a detailed description of the field.
The detailed description consists of:
•For a readable field, the values the field can take
•For a writable field, the values the field can be set to

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REFERENCE_TRIM[2:0], ADC Reference Trim, AFE Map, Address 0x0F, [7:5]
ADC Reference Trim is used to adjust the ADC full range scale. The default value for ADC
Reference Trim is 3b000. This must be changed to 3b100 for proper operation.
Function
REFERENCE_TRIM[2:0] Description
xxx Adjust the ADC full-range scale.
000 1.0 V
001 1.1 V
010 1.2 V
011 1.3 V
100 Á1.4 V (recommended setting)
101 Reserved
110 Reserved
111 Reserved
Figure 1: Field Description Format
1.8 References
HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.3a, November 10,
2006
Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System,
Revision 1.3, December 21, 2006
CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D,
July 18, 2006
IUT, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line
Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998
IUT, ITU-R BT.601-5 Studio encoding parameters of digital television for standard 4:3 and
widescreen 16:9 aspect ratios, October 1995
IUT, ITU-R BT.709-5 Parameter values for the HDTV standards for production and international
programme exchange, April 2002
Default value
indicated by Á
The name of the field. In this example the field is
called REFERENCE_TRIM and is 3 bit long.
Short function
description
of the field
I2C location of the
field in big endian
format (MSB first,
LAST last)
Detailed
description
of the field
Function of the field for each
value the field can take or be
set to. Values are in binary
format.
Values the field can be set to
or take. These values are in
binary format if not preceded
by ‘0x’ and in hexadecimal
format if preceded by ‘0x’.

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CENELEC, EN 50157, Part 1, Domestic and similar electronic equipment interconnection
requirements: AV.link
CENELEC, EN 50157, Part 2-1, Domestic and similar electronic equipment interconnection
requirements: AV.link
CENELEC, EN 50157, Part 2-2, Domestic and similar electronic equipment interconnection
requirements: AV.link
CENELEC, EN 50157, Part 2-3, Domestic and similar electronic equipment interconnection
requirements: AV.link

ADV7604
Rev. F August 2010 13
2Introduction
The ADV7604 is a single chip, multiformat video decoder, and graphics digitizer with an integrated
4:1 multiplexed High-Definition Multimedia Interface (HDMI™).
The ADV7604 can operate in quad HDMI and analog input mode, thus providing simultaneous
HDMI and analog video sync processing. It integrates a component processor (CP), which can
processes YPrPb and RGB component formats, RGB graphics and video signals from the HDMI
receiver.
The ADV7604 can support decode of a component RGB/YPrPb video signal into a digital YCrCb or
RGB pixel output stream. Graphics digitization is supported with RGB graphics signals from VGA
to UXGA rates and converting them into a digital RGB or YCrCb pixel output stream.
The ADV7604 incorporates a quad input HDMI 1.3b compatible receiver that supports all HDTV
formats up to 1080p and display resolutions up to UXGA. The reception of encrypted video is
possible with the inclusion of HDCP. The ADV7604 can process all audio formats supported in the
HDMI 1.3 specification.
Fabricated in an advanced CMOS process, the ADV7604 is provided in a space-saving, 260-ball
15 mm x 15 mm BGA surface-mount, Pb-free package and is specified over the −40°C to +70°C
temperature range.
2.1 Analog Front End
The ADV7604 analog front end comprises four 12-bit ADCs that digitize the analog video signal
before applying it to the CP. The analog front end uses internal differential signaling to each ADC to
ensure high performance in a mixed signal application.
The video front end includes a 6-channel input mux that enables multiple video signals to be applied
to the ADV7604. Voltage clamps are positioned in front of each ADC to ensure that the video signal
remains within the range of the converter. Fine clamping of the video signals is performed
downstream by digital fine clamping in the CP.
4x oversampling is performed for component 525i, 625i, 525p, and 625p sources. 2x oversampling is
supported for 1080i and 720p. All other video standards are 1× oversampled. Oversampling the
video signals eliminates the needs for external anti aliasing filters with the benefit of an increased
SNR.
2.2 HDMI Receiver
The HDMI receiver on the ADV7604 incorporates active equalization of the HDMI data signals.
This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling,
especially at longer lengths and higher frequencies. The equalizer is programmable and is capable of
equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even the
highest HDMI data rates.

ADV7604
Rev. F August 2010 14
With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of
the ADV7604 allows for authentication of a video receiver, decryption of encoded data at the
receiver, and renewability of that authentication during transmission, as specified by the HDCP
v1.3b protocol.
The HDMI receiver offers audio functionality. The receiver contains an audio mute controller, which
can detect a variety of conditions that could result in audible extraneous noise in the audio output.
Upon detection of these conditions, the audio data can be muted to prevent audio clicks or pops.
2.3 Component Processor
The CP section is capable of decoding a wide range of component video formats in any color space.
Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p,
1250i, VGA up to UXGA at 60 Hz, and many other standards.
Two fully programmable any-to-any 3 × 3 color space conversion matrices are placed in the front
end and the back end of the CP section. Either of the two color space converters can be used to
implement YPrPb to RGB and RGB to YCrCb conversions. Many other standards of color space can
be implemented using the color space converter.
The output section of the CP is highly flexible. It can be configured in Single Data Rate (SDR) mode
with one data packet per clock cycle or in a Double Data Rate (DDR) mode where data is presented
on the rising and falling edge of the clock. In SDR mode, a 16/20/24-bit 4:2:2 or 24/30/36-bit 4:4:4
output is possible. In these modes, HSync, VSync/FIELD, and FIELD/DE (where applicable) timing
reference signals are provided. In DDR mode, the ADV7604 can be configured in an 8/10/12-bit
4:2:2 YCrCb or 12-bit 4:4:4 RGB/YCrCb pixel output interface with corresponding timing signals.
The CP section contains circuitry to enable the detection of Macrovision encoded YPrPb signals for
525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals.
VBI extraction of CGMS data is performed by the VDP section of the ADV7604 for interlaced,
progressive, and high definition scanning rates. The data extracted can be read back over the I2C
interface.
For more detailed product information about the ADV7604, contact the local ADI sales office.

ADV7604
Rev. F August 2010 15
2.4 Main Features of ADV7604
2.4.1 Analog Front End
The analog front end functionality includes:
•Four 170 MHz 12-bit ADCs enabling true 12-bit video decoding
•Six analog input channel mux enabling multisource connection without the
requirement of an external mux
•Three voltage clamp control loops ensuring any DC offsets are removed from the
video signal
•Digital PLL design delivering ultra low sampling jitter for digitizer
2.4.2 HDMI Receiver
•HDMI 1.3 compatible receiver
•HDCP v1.3 compliant receiver
•Supports all HDTV formats up to 1080p
•Supports all display resolutions up to UXGA (1600 x 1200 at 60 Hz)
•Supports IEC60958, 2 to 8 channels PCM
•Supports IEC61937 compressed audio
•Capable of receiving DSD and HBR packets
•Programmable front end equalization for HDMI operation over cable lengths up to 30
meters
•Audio mute for removing extraneous noises
•Programmable interrupt generator to detect HDMI packets
•Internal EDID support
•Power-down EDID support
•Consumer electronic control (CEC) controller
2.4.3 Video Output Formats
•Pseudo DDR (CCIR-656 type stream) 8/10/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and
625P
•SDR 16/20/24-bit 4:2:2 YCrCb for all standards
•SDR 24/30/36-bit 4:4:4 YCrCb/RGB for all standards
•Double data rate (DDR) 8/10/12-bit 4:2:2 YCrCb for all standards
•DDR 8/10/12-bit 4:4:4 YCrCb/RGB for all standards
2.4.4 Component Video Processing
•Formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other
HDTV formats
•Automatic adjustments for gain (contrast) and offset (brightness); manual adjustment
controls are also supported

ADV7604
Rev. F August 2010 16
•Support for analog component YPrPb/RGB video formats with embedded synchronization
or with separate HSync, VSync, or CSync
•Two any-to-any 3 × 3 CSC matrices support YCrCb to RGB and RGB to YCrCb. The
second CSC supports color controls such as saturation, brightness, hue, and contrast
•Two standard identification (STDI) blocks that enable dual system component format
detection
•Two synchronization source polarity detectors (SSPD) determine the source and polarity of
the synchronization signals that accompany video inputs
•Certified Macrovision copy protection detection on component formats (525i, 625i, 525p,
and 625p)
•Free run output mode provides stable timing when no video input is present
•Arbitrary pixel sampling support for nonstandard video sources
•Autographic mode allows support for an extended selection of standards
2.4.5 RGB Graphics Processing
•170 MHz conversion rate supports RGB input resolutions up to 1600 × 1200 at 60 Hz
(UXGA)
•Automatic or manual clamp and gain controls for graphics modes
•Contrast, brightness, saturation, and hue controls
•32-phase Delay Locked Loop (DLL) allows optimum pixel clock sampling
•Automatic detection of synchronization source and polarity by the SSPD block
•Standard identification is enabled by either of the available STDI blocks
•RGB can be color space converted to YCrCb and decimated to a 4:2:2 format for video
centric back-end IC interfacing
•Data enable (DE) output signal supplied for direct connection to HDMI/DVI transmitter IC
•Arbitrary pixel sampling support for nonstandard video sources
•Autographic mode allows support for an extended selection of standards
2.4.6 Additional Features
•HSync, VSync, FIELD, and DE output signals with programmable position, polarity, and
width
•Interrupts maskable on each interrupt request output pin, INT1 and INT2
•Low power consumption: 1.8 V digital core, 1.8 V analog, and 3.3 V digital input/output,
low power power-down mode, and green PC mode
•Temperature range : -40°C to +70°C
•15 mm x 15 mm Pb-free 256 pin 260-ball package BGA

ADV7604
Rev. F August 2010 17
2.5 Functional Block Diagram
AIN1
AIN2
AIN3
AIN4 ADC0
CLAMP
ADC1
CLAMP
ADC2CLAMP
SYNC PROCESSING
AND
CLOCK GENERATION
SYNC3
SYNC4
HS_IN1
VS_IN1
AVLINK
SCL
SDA
CEC
AVLINK
CEC
CONTROLLER
CONTROL
INTERFACE
I2C
VIDEO DATA
PROCESSOR
HS/CS, VS
CONTROL
AND
DATA
CONTROL
P0 TO P11
P12 TO P23
P24 TO P35
LLC
INT1
SYNC_OUT/INT2
HS
VS
_ FIELD
DE
MUX
RXA_C±
RXB_C±
RXC_C± PLL
EQUALIZER SAMPLER HDMI
PROCESSOR
EDID
REPEATER
CONTROLLER
HDCP
ENGINE HDCP
EEPROM
PACKET
PROCESSOR
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
RXA_5V
RXB_5V
RXC_5V
RXD_5V
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SHARED_EDID
PACKET /
INFOFRAME
MEMORY
LRCLK/DSD2B/DST_FF
SCLK/DST_CLK
SPDIF/DSD0/DST
RXA_0±
RXA_1±
RXA_2±
EQUALIZER
EQUALIZER
EQUALIZER
SAMPLER
RXB_0±
RXB_1±
RXB_2±
SAMPLER
RXC_0±
RXC_1±
RXC_2±
SAMPLER
RXD_0±
RXD_1±
RXD_2±
AIN5
AIN6
DATA
PREPROCESSOR
AND
COLOR
SPACE
CONVERTER
EMBEDDED
SYNC
A
B
C
BLC
DDCA_SDA
DDCA_SCL
12
12
12
12
12
12
BACK
END
CSC
RXD_C±
TRI7/HS_IN2
TRI8/VS_IN2
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
SYNC1
SYNC2
TRI1
TRI2
TRI3
TRI4
TRI5
TRI6
TRILEVEL
SLICER
CLAMPIN
12-
CHANNEL
INPUT
MATRIX
I2S0/DSD0B/HBR0
I2S1/DSD1A/HBR1
I2S2/DSD1B/HBR2
I2S3/DSD2A/HBR3
OUTPUT FORMATTER
COMPONENT
PROCESSOR
AND
ENHANCED
STANDARD
DEFINITION
PROCESSOR
ADV7604
MCLKOUT
Y_MUX_OUT
RAW_SYNC
RAW_VSYNC
AUDIO
07971-001
PWRDN
Figure 2: Functional Block Diagram

ADV7604
Rev. F August 2010 18
2.6 Pin Descriptions
123456789101112131415161718
A
DGND RXD_2- RXD_1- RXD_0- RXD_C- DGND RXC_2- RXC_1- RXC_0- RXC_C- TVDD RXB_2- RXB_1- RXB_0- RXB_C- TVDD TVDD DGND
A
B
RXD_5V RXD_2+ RXD_1+ RXD_0+ RXD_C+ TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ TVDD RXA_2+ RXA_2-
B
C
PWRDNB TVDD TVDD CVDD DGND TVDD TVDD DGND DGND DGND TVDD TVDD DGND DGND DGND DGND RXA_1+ RXA_1-
C
D
RXC_5V RXB_5V RXA_5V DDCD_SD
ADDCD_SC LDDCC_SD ADDCC_SC LCVDD DGND RTERM CVDD DDCB_SD ADDCB_SC LDDCA_SC LDDCA_SD ATVDD RXA_0+ RXA_0-
D
E
DE CEC DGND DGND RXA_C+ RXA_C-
E
F
HS VS_FIELD EP_MISO EP_MOSI DGND CVDD TVDD DGND
F
G
P1 P0 EP_CS EP_SCK DGND DGND DGND DGND PVDD PVDD TEST1 TEST2
G
H
P3 P2 RAW_VSY
NC RAW_SYN CDGND DGND DGND DGND AGND AGND XTALP AVDD REFN REFP
H
J
DGND DGND MCLKOUT SPDIF DVDD DGND DGND DGND AGND AGND XTALN AVDD AGND AGND
J
K
P4 P5 LRCLK SCLK DVDD DVDD DGND DGND AGND AVDD AVDD AVDD AIN11 AIN12
K
L
P6 P7 I2S3 I2S2 DVDD DVDD DGND DGND AGND AVDD TRI8/VS_I
N2 TRI7/HS_I N2 SYNC4 AIN10
L
M
P8 DGND DGND DGND DVDD DVDD DGND DGND AGND AVDD TRI5 TR6 AGND AGND
M
N
P9 DVDDIO DVDDIO DVDDIO TRI3 TRI4 AIN8 AIN9
N
P
P10 P11 I2S0 I2S1 AVDD AVDD SYNC3 AIN7
P
R
P12 P13 DGND DGND SCL DVDDIO INT1 CLAMPIN DVDDIO DGND FB_OUT SHARED_
EDID HS_IN1 AGND Y_Mux_out TRI2 AGND AGND
R
T
P14 P15 DGND DGND P25 DVDDIO SDA SYNC_OU
T/INT2 DVDDIO DGND RESETB AVLINK VS_IN1 AGND TRI1 SYNC2 AIN5 AIN6
T
U
P16 P17 P19 P21 P23 DGND P26 DCLKIN P28 DGND P31 P33 P35 AGND SYNC1 AVDD AVDD AIN4
U
V
DGND P18 P20 P22 P24 DGND P27 LLC P29 DGND P30 P32 P34 AGND AIN1 AIN2 AIN3 AGND
V
123456789101112131415161718
Figure 3: ADV7604 Pin Configuration
Table 1: Pin Function Descriptions
Pin Mnemonic Type Function
A1 DGND Ground Ground
B1 RXD_5V HDMI Input 5 V detect pin for port D in the HDMI
interface.
C1 PWRDNB Input Active low power-down pin.
If used this pin should be pulled high to power
up the ADV7604. Can also be used as in
system power detect where internal EDID can
be powered from 5 V signal of HDMI port
when connected to active equipment.
D1 RXC_5V HDMI Input 5 V detect pin for port C in the HDMI
interface.

ADV7604
Rev. F August 2010 19
Pin Mnemonic Type Function
E1 DE Digital Video
Output
DE (data enable) is a signal that indicates
active pixel data.
F1 HS Digital Video
Output
HS is a horizontal synchronization output
signal in the CP and HDMI processor.
G1 P1 Digital Video
Output
Video pixel output port.
H1 P3 Digital Video
Output
Video pixel output port.
J1 DGND Ground Ground
K1 P4 Digital Video
Output
Video pixel output port.
L1 P6 Digital Video
Output
Video pixel output port.
M1 P8 Digital Video
Output
Video pixel output port.
N1 P9 Digital Video
Output
Video pixel output port.
P1 P10 Digital Video
Output
Video pixel output port.
R1 P12 Digital Video
Output
Video pixel output port.
T1 P14 Digital Video
Output
Video pixel output port.
U1 P16 Digital Video
Output
Video pixel output port.
V1 DGND Ground Ground.
A2 RXD_2- HDMI Input Digital input channel 2 complement of port D
in the HDMI interface.
B2 RXD_2+ HDMI Input Digital input channel 2 true of port D in the
HDMI interface.
C2 TVDD Power Terminator supply voltage (3.3 V)
D2 RXB_5V HDMI Input 5 V detect pin for port B in the HDMI
interface.
E2 CEC Digital I/O Consumer electronic control channel.
F2 VS_FIELD Digital Video
Output
VS is a vertical synchronization output signal
in the CP and HDMI processor. FIELD is a
field synchronization output signal in all
interlaced video modes. VS or FIELD can be
configured for this pin.
G2 P0 Digital Video
Output
Video pixel output port.
H2 P2 Digital Video
Output
Video pixel output port.
J2 DGND Ground Ground.
K2 P5 Digital Video
Output
Video pixel output port.
L2 P7 Digital Video
Output
Video pixel output port.

ADV7604
Rev. F August 2010 20
Pin Mnemonic Type Function
M2 DGND Ground Ground.
N2 DVDDIO Power Digital I/O supply voltage (3.3 V).
P2 P11 Digital Video
Output
Video pixel output port.
R2 P13 Digital Video
Output
Video pixel output port.
T2 P15 Digital Video
Output
Video pixel output port.
U2 P17 Digital Video
Output
Video pixel output port.
V2 P18 Digital Video
Output
Video pixel output port.
A3 RXD_1- HDMI Input Digital input channel 1 complement of port D
in the HDMI interface.
B3 RXD_1+ HDMI Input Digital input channel 1 true of port D in the
HDMI interface.
C3 TVDD Power Terminator supply voltage (3.3 V).
D3 RXA_5V HDMI Input 5 V detect pin for port A in the HDMI
interface.
F3 EP_MISO Digital Output SPI master in/slave out for external EDID
interface.
G3 EP_CS Digital Output SPI chip select for external EDID interface.
H3 RAW_VSYNC Analog Output This pin outputs the raw-sliced, embedded
CSync or raw digital HS/CS.
J3 MCLKOUT Misc Digital Audio master clock output.
K3 LRCLK/DSD2B Misc Digital Data output clock for left and right audio
channels.
6th DSD data channel.
L3 I2S3/DSD2A/HBR3 Misc Digital I2S audio (channel 7 and channel 8).
5th DSD data channel.
4th block of HBR stream.
M3 DGND Ground Ground.
N3 DVDDIO Power Digital I/O supply voltage (3.3 V).
P3 I2S0/DSD0B/HBR0 Misc Digital I2S audio (channel 1 and channel 2).
2nd DSD channel 1.
1st block of HBR stream.
R3 DGND Ground Ground.
T3 DGND Ground Ground.
U3 P19 Digital Video
Output
Video pixel output port.
V3 P20 Digital Video
Output
Video pixel output port.
A4 RXD_0- HDMI Input Digital input channel 0 complement of port D
in the HDMI interface.
B4 RXD_0+ HDMI Input Digital input channel 0 true of port D in the
HDMI interface.
C4 CVDD Power Comparator supply voltage (1.8 V).
D4 DDCD_SDA HDMI Input HDCP slave serial clock port D. DDCD_SDA