ICS ICS1531 User manual

1531DaRev A 6/13/00 June, 2000
PRELIMINARY documents contain information on new products in
the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Integrated Circuit Systems, Inc.
ICS1531 Daughterboard Guide for ICS1531
Demonstration Board, Revision C
Introduction
Two daughterboards can be used with the ICS1531 Demo Board, Revision C, to demonstrate the ICS1531
capabilities:
•Low-Voltage Differential-Signaling (LVDS) Daughterboard
•Digital-to-Analog (DAC) Daughterboard
To configure and operate the ICS1531 Demo Board with its daughterboards, use this document with the
following documents:
•ICS1531 Data Sheet
•ICS1531 Register Tool Guide
•ICS1531 Demonstration Board Guide, Revision C
Revision History
This is the initial release of this document.
ICS1531 1531 Document Type: Daughterboard Guide
Product Stage: Preliminary

1531DaRevA 6/13/00 Copyright © 2000 Integrated Circuit Systems, Inc. All rights reserved. June, 2000
2
Chapter 1 Daughterboard LayoutsICS1531 Daughterboard - Preliminary
Chapter 1Daughterboard Layouts
Figure 1-1 shows the location of the components used to configure the LVDS Daughterboard. (For both a
figure of the ICS1531 Demo Board and an LCD interconnect table, see the ICS1531 Demo Board Guide.)
Figure 1-1.LVDS Daughterboard for ICS1531 Demo Board
Table 1-1 lists and describes components on the LVDS Daughterboard, a schematic for which is inChapter
3, “Schematics”. For the LVDS daughterboard, the input is digital (2 pixels/clock) and the output is
low-voltage digital signals (2 pixels/clock).
Table 1-1. LVDS Daughterboard Components
Component #
and Label (If Any) Component Name, Function, and Settings
H6, H7, H8 Header 6, 7, and 8.
Headers that connect the LVDS Daughterboard to the following signals from the
ICS1531 Demo Board:
•Input digital panel data that is output from ICS1531 Demo Board U1 (ICS1531)
•Clock signals from ICS1531 Demo Board U2 (Xilinx XC95144XL):
–H6 - clock signals are on pins PX and PY (two programmable control signals).
–H7 - clock signals are on pins PHS (panel HSYNC) and PVS (panel VSYNC).
–H8 - clock signals are on pins CLK (clock) and DE (display enable).
LT1086CT
Integrated Circuit Systems, Inc.
LVDS
ICS1531 DEMO BOARD REV C
COPYRIGHT © 2000
RA1 RA3 G RA5 RA7 G RB1 RB3 G RB G RB7 PY
BA1 BA3 G BA5 BA7 G BB1 BB3 G BB5 G BB7 DE
H6 H8
GA1 GA3 G GA5 GA7 G GB1 GB3 G GB5 G GB7 PVS
H7
BA0 BA2
G
BA4 BA6
G
BB0 BB2
G
BB4
G
BB6
CLK GA0 GA2
G
GA4 GA6
G
GB0 GB2
G
GB4
G
GB6 PHS
RA0 RA2
G
RA4 RA6
G
RB0 RB2
G
RB4
G
RB6
PX
U14
JP8
3V
5V
U13
JP10
U15
JP7
+12V +5V JP9
1
2
29
30
Serial
Number
Alternative
Connector
3
2 V5 / V3.3 4 GND 6 TXO 0- 8 TXO 1- 10 TXO 2- 12 TXO 3- 14 TXO Ck- 16 GND 18 TXE 0- 20 TXE 1- 24 TXE 3- 22 TXE 2- 26 TXE Ck-
JP9
V5 / V3.3 1
GND 3
TXO 0+ 5 TXO 1+ 7 TXO 2+ 9 TXO 3+ 11
TXO Ck+ 13
GND 15
TXE 0+ 17 TXE 1+ 19 TXE 3+ 23 TXE 2+ 21
TXE Ck+ 25
GND 27
V12 29 28 GND
30 V12

Chapter 1 Daughterboard Layouts
1531DaRevA 6/13/00 Copyright © 2000 Integrated Circuit Systems, Inc. All rights reserved. June, 2000
3
ICS1531 Daughterboard – Preliminary
JP7 Jumper 7.
Controls voltage to an LCD panel as follows:
•Pins 1 and 3 = Ground
•Pin 2 = +12 V
•Pin 4 = +5 V
JP8 Jumper 8.
Controls voltage to JP9 as follows:
•Pins 1 and 2 = +3.3 V to JP9 pins 1 and 2
•Pins 2 and 3 = +5 V to JP9 pins 1 and 2
JP9 Jumper 9.
Alternative connector for low-voltage differential signals (LVDS).
JP10 Jumper 10.
Selects input voltage to LVDS Daughterboard as follows:
•Pins 1 and 3 = +5 V
•Pins 2, 4, 6, 8 = Ground
•Pins 5 and 7 = +12 V
Serial number of
Daughter Board Serial number. Unique serial number, located near the right top side of the LVDS Daughterboard.
U13 Integrated Circuit 13.
LT1086CTvoltage regulator. Provides +3.3-V operating voltage to U14 and U15.
U14, U15 Integrated Circuit 14, 15
Low-voltage differential signaling (LVDS) transmitters.
Table 1-1. LVDS Daughterboard Components (Continued)
Component #
and Label (If Any) Component Name, Function, and Settings
Pin Number
and Name Function Pin Number and Name Function
1 - V5 / V3.3 Connects to JP8 Pin2 to
select either 5 or 3.3 V 16 - GND Ground
2 - V5 / V3.3 17 - TXE 0p Transmit Even 0 +
3 - GND Ground 18 - TXE 0m Transmit Even 0 -
4 - GND Ground 19 - TXE 1p Transmit Even 1 +
5 - TXO 0p Transmit Odd 0 + 20 - TXE 1m Transmit Even 1 -
6 - TXO 0m Transmit Odd 0 - 21 - TXE 2p Transmit Even 2 +
7 - TXO 1p Transmit Odd 1 + 22 - TXE 2m Transmit Even 2 -
8 - TXO 1m Transmit Odd 1 - 23 - TXE 3p Transmit Even 3 +
9 - TXO 2p Transmit Odd 2 + 24 - TXE 3m Transmit Even 3 -
10 - TXO 2m Transmit Odd 2 - 25 - TXE Ckp Transmit Even Clock +
11 - TXO 3p Transmit Odd 3 + 26 - TXE Ckm Transmit Even Clock -
12 - TXO 3m Transmit Odd 3 - 27 - GND Ground
13 - TXO Ckp Transmit Clock + 28 - GND Ground
14 - TXO Ckm Transmit Clock - 29 - V12 +12 V
15 - GND Ground 30 - V12 +12 V

1531DaRevA 6/13/00 Copyright © 2000 Integrated Circuit Systems, Inc. All rights reserved. June, 2000
4
Chapter 1 Daughterboard LayoutsICS1531 Daughterboard - Preliminary
Figure 1-2 shows the location of all components used to configure the ICS1531 DAC Daughterboard.
Figure 1-2.DAC Daughterboard for ICS1531 Demo Board
Table 1-2 lists and describes relevant components on the ICS1531 DAC Daughterboard, a schematic for
which is in Chapter 3, “Schematics”. For the DAC daughterboard, the input must be digital
(1 pixel/clock) and the output is analog (1 pixel/clock).
Table 1-2. DAC Daughterboard Components
Component #
and Label (If Any) Component Name, Function, and Settings
CN5 Connector 5.
DB-15 connector to analog VGA output.
H9, H10, H11 Header 9, 10, and 11.
Headers to connect DAC Daughterboard to these ICS1531 Daughterboard
signals:
•Input digital panel data that is output from ICS1531 Demo Board U1 (ICS1531)
•Clock signals from the ICS1531 Demo Board U2 (Xilinx XC95144XL):
–H6 - clock signals are on pins PX and PY (two programmable control signals).
–H7 - clock signals are on pins PHS (panel HSYNC) and PVS (panel VSYNC).
–H8 - clock signals are on pins CLK (clock) and DE (display enable).
JP11 Jumper 11.
Power input voltage to DAC Daughterboard.
•Pins 1 and 3 = +5 V
•Pins 2, 4, 6, 8 = Ground
•Pins 5 and 7 = +12 V
POT3 Potentiometer 3 (Optional).
5KΩpotentiometer for adjusting peak-to-peak voltage to U16 (the DAC).
Serial number of
Daughter Board Serial number. Unique serial number, located near the right top side of the DAC Daughterboard.
U16 Integrated Circuit 16.
Digital-to-analog converter.
Note: This component connects to pixel channel ‘A’ RGB data. (That is, there is
no connection to pixel channel ‘B’ RGB data.)
Digital-to-
Analog
Converter
Integrated Circuit Systems, Inc.
DAC
ICS1531 DEMO BOARD REV C
COPYRIGHT © 2000
RA1 RA3 G RA5 RA7 G RB1 RB3 G RB5 G RB7 PY
BA1 BA3 G BA5 BA7 G BB1 BB3 G BB5 G BB7 DE
H9 H1
GA1 GA3 G GA5 GA7 G GB1 GB3 G GB5 G GB7 PVS
H10
BA0 BA2
G
BA4 BA6
G
BB0 BB2
G
BB4
G
BB6
CLK GA0 GA2
G
GA4 GA6
G
GB0 GB2
G
GB4
G
GB6 PHS
RA0 RA2
G
RA4 RA6
G
RB0 RB2
G
RB4
G
RB6
PX
U16
JP11
Serial
Number
CN5
POT3

Chapter 2 ICS1531 Demo Board Connections
1531DaRevA 6/13/00 Copyright © 2000 Integrated Circuit Systems, Inc. All rights reserved. June, 2000
5
ICS1531 Daughterboard – Preliminary
Chapter 2ICS1531 Demo Board Connections
Table 2-1 lists and describes ICS1531 Demo Board components that connect to either the LVDS or the
DAC Daughterboard.
Chapter 3Schematics
This chapter gives the ICS1531 Daughterboard schematics, which show connections for the following:
•Schematic Page 5: Low-voltage digital signal (LVDS) Daughterboard, compatible with Pixelworks printed
circuit board
•Schematic Page 6: Digital-to-analog converter (DAC) Daughterboard
Table 2-1. ICS1531 Demo Board, Revision C, Components that connect to LVDS Daughterboard
Component
Number
and Label
(If Any)
ICS1531 Demo Board Component Name, Function, and Settings
H3, H4, H5 ICS1531 Demo Board Header 3, 4, and 5.
ICS1531 Demo Board headers that connect to H6, H7, and H8 of the LVDS or DAC
Daughterboard. (For details, see the ICS1531 Demonstration Board Guide, Revision C.)
JP6 ICS1531 Demo Board Header 6.
Provides 5 V and 12 V for the LVDS or DAC Daughterboard. (For details, see the
ICS1531 Demonstration Board Guide, Revision C.)

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Power
Input
5 V in3.3 V out
TO-220
3.3 Volt
Regulator
LVDS Daughter Board - PW Compatible A
ICS153x-C Demonstration Board
Integrated Circuit Systems
525 Race Street
San Jose, CA. 95126-3448
408-297-1201 fax [phone]
B
514Wednesday, April 19, 2000
Title
Size Document Number Rev
Date: Sheet of
TXOCKm
TXO3m
DRO6
DRO2
DRO4
DRO1
DRO5
DRO7
DRO0
DRO3
DBO0
DBO6
DBO3
DBO1
DBO5
DBO2
DBO4
DBO7
DGO7
DGO3
DGO5
DGO1
DGO0
DGO6
DGO2
DGO4
12VAON
AUXVCC
AUXV12
5VAON
RAout0
RAout1
RBout5
RBout6
RAout2
RBout2
RBout1
RBout7
RAout3
RBout4
RBout3
RAout4
RAout7
RAout6
RBout0
RAout5
RAUXON
GBout7
GBout6
GBout3
GAout1
GAout0
GAout6
GBout2
GAout5
GAout4
GAout3
GAout2
GBout1
GBout0
GAout7
GBout4
GBout5
BBout7
BBout6
BBout5
BBout3
BBout2
BBout1
BBout0
BAout5
BBout4
BAout4
BAout7
BAout3
BAout2
BAout1
BAout6
BAout0
PNLCLK
TXO1p TXO1m
TXO2p
TXO0p TXO0m
TXOCKp
TXO2m
TXO3p
TXE2m
TXECKm
PNLDE
TXE3m
TXE0p
TXE3p
TXE2p
TXECKp
TXE0m
TXE1mTXE1p
DRE5
DGE2
DGE6
DGE7
DBE7
DGE0
DGE1
DGE4
DRE7
DBE4
DRE1
DRE0
DBE0
DBE3
DRE2
DBE2
DBE1
DRE4
DRE3
DBE5
DBE6
DGE3
DRE6
DGE5
V33
V12
V5
V33
V12
V33
V33
V5
V5
V33
V33
V5
V12
C67
0.1uF
C68
0.1uF
C69
0.1uF
C76
0.1uF
C75
0.1uF
C79
0.1uF R703.3K
C80
0.1uF R713.3K
Q3
NPN
1
2 3
Q1A
IRF7314
1
2
7 8
Q1B
IRF7314
3
4
5 6
R693.3K
JP7
PWR_HDR
12
34
H6
Con26
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24 25
26
Q2
NPN
1
2 3
H7
Con26
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24 25
26
H8
Con26
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24 25
26
U14
DS90C383A
51
52
54
55
56
2
3
4
6
7
8
10
11
12
14
15
16
18
19
20
22
23
24
25
27
28
30
50
47
45
41
37
39
48
46
42
38
40
31
32
17
1 9 26 34 44
5 13 21 29 53 33 35 36 43 49
TXIN0
TXIN1
TXIN2
TXIN3
TXIN4
TXIN5
TXIN6
TXIN7
TXIN8
TXIN9
TXIN10
TXIN11
TXIN12
TXIN13
TXIN14
TXIN15
TXIN16
TXIN17
TXIN18
TXIN19
TXIN20
TXIN21
TXIN22
TXIN23
TXIN24
TXIN25
TXIN26
TXIN27
TXOUT0
TXOUT1
TXOUT2
TXOUT3
TXCOUT
TXOUT0
TXOUT1
TXOUT2
TXOUT3
TXCOUT
CLKIN
PWRDN
R_F
VCC1 VCC2 VCC3
PVCC
OVCC
GND1 GND2 GND3 GND4 GND5 PGND1 PGND2 OGND1 OGND2 OGND3
JP9
HEADER 15X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
JP10
HEADER 4X2
12
34
56
78
C72
0.1uF
C71
0.1uF
C78
0.1uF
C70
0.1uF
U15
DS90C383A
51
52
54
55
56
2
3
4
6
7
8
10
11
12
14
15
16
18
19
20
22
23
24
25
27
28
30
50
47
45
41
37
39
48
46
42
38
40
31
32
17
1 9 26 34 44
5 13 21 29 53 33 35 36 43 49
TXIN0
TXIN1
TXIN2
TXIN3
TXIN4
TXIN5
TXIN6
TXIN7
TXIN8
TXIN9
TXIN10
TXIN11
TXIN12
TXIN13
TXIN14
TXIN15
TXIN16
TXIN17
TXIN18
TXIN19
TXIN20
TXIN21
TXIN22
TXIN23
TXIN24
TXIN25
TXIN26
TXIN27
TXOUT0
TXOUT1
TXOUT2
TXOUT3
TXCOUT
TXOUT0
TXOUT1
TXOUT2
TXOUT3
TXCOUT
CLKIN
PWRDN
R_F
VCC1 VCC2 VCC3
PVCC
OVCC
GND1 GND2 GND3 GND4 GND5 PGND1 PGND2 OGND1 OGND2 OGND3
C77
0.1uF
U13
LT1086CT
1
2
3
ADJ
VOUT
VIN
+
C74
47uF
+
C73
47uF
R68
180
R67
380
JP8
jumper 3
1
23
DGO[7:0]
DRO[7:0]
DHS
DCLK
DVS
DBO[7:0]
DEN
PNLX
DRE0
DRE1
DRE2
DRE3
DRE4
DRE5
DRE6
DRE7
DRO0
DRO1
DRO2
DRO3
DRO4
DRO5
DRO6
DRO7
DGE0
DGE1
DGE2
DGE4
DGE5
DGE6
DGE7
DGO2
DGO0
DGO6
DGO1
DGO5
DGO3
DGO4
DGO7
DBE0
DBE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7
DBO2
DBO0
DBO6
DBO1
DBO5
DBO3
DBO4
DBO7
DHS
DVS
DCLK
DEN
PNLX
PNLY
DRE[7:0]
DEN
DGE[7:0]
DVS
PNLY
DCLK
DBE[7:0]
DHS
DGE3
PNLY

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Power
Input
DAC Daughter Board A
ICS153x-C Demonstration Board
Integrated Circuit Systems
525 Race Street
San Jose, CA. 95126-3448
408-297-1201 fax [phone]
B
614Thursday, April 20, 2000
Title
Size Document Number Rev
Date: Sheet of
RAout0
RAout1
RBout5
RBout6
RAout2
RBout2
RBout1
RBout7
RAout3
RBout4
RBout3
RAout4
RAout7
RAout6
RBout0
RAout5
GBout7
GBout6
GBout3
GAout1
GAout0
GAout6
GBout2
GAout5
GAout4
GAout3
GAout2
GBout1
GBout0
GAout7
GBout4
GBout5
BBout7
BBout6
BBout5
BBout3
BBout2
BBout1
BBout0
BAout5
BBout4
BAout4
BAout7
BAout3
BAout2
BAout1
BAout6
BAout0
PNLCLK
PNLDE
DGE2
DGE6
DGE7
DBE7
DGE0
DGE1
DGE4
DBE4
DBE0
DBE3
DBE2
DBE1
DBE5
DBE6
DGE3
DGE5
DRE5
DRE1
DRE0
DRE2
DRE4
DRE3
DRE6
DRE7
V12
V5
VAA V5
VAA
VAA
H9
Con26
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24 25
26
H10
Con26
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24 25
26
H11
Con26
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24 25
26
C87
0.1uF
B3 TDK-ACB2012M-150-T
JP11
HEADER 4X2
12
34
56
78
POT3
no
1 3
2
+
C84
47uF B2
TDK-ACB2012M-150-T
C83
0.1uF
C89
0.1uF
C88
0.1uF
R74
75
R75
75
R76
75
C81
0.1uF
+
C82
47uF
R72
1K
R73
560
C85
0.1uF
B5
TDK-ACB2012M-150-T
CN5
DB-15-F
1
2
3
4
5
10
9
8
7
611
12
13
14
15
.
.
.
.
.
.
.
.
.
..
.
.
.
.
B6
TDK-ACB2012M-150-T
U16
ADV7123
35
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
14
15
16
17
18
19
20
21
22
23
12
11
24
38 25 26
27
31
33
34
32
28
37
36 29 30 13
COMP
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
SYNC
BLANK
CLOCK
PSAVE GND GND
IOB
IOG
IOR
IOR
IOG
IOB
RSET
VREF
VAA VAA VAA
DRE0
DRE1
DRE2
DRE3
DRE4
DRE5
DRE6
DRE7
DRO0
DRO1
DRO2
DRO3
DRO4
DRO5
DRO6
DRO7
DGE0
DGE1
DGE2
DGE3
DGE4
DGE5
DGE6
DGE7
DGO2
DGO0
DGO6
DGO1
DGO5
DGO3
DGO4
DGO7
DBE0
DBE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7
DBO2
DBO0
DBO6
DBO1
DBO5
DBO3
DBO4
DBO7
DHS
DVS
DCLK
DEN
PNLX
PNLY
DCLK
DVS
DHS
DEN
DGE[7:0]
DBE[7:0]
DRE[7:0]