Infineon Technologies Cypress CYW20733 User manual

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CYW20733
Single-Chip Bluetooth Transceiver
Wireless Input Devices
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document No. 002-14859 Rev. *S Revised November 9, 2017
The Cypress CYW20733 is a Bluetooth 3.0 + EDR compliant, stand-alone baseband processor with an integrated 2.4 GHz trans-
ceiver. The device is ideal for applications in wireless input devices including game controllers, keyboards, and joysticks. Built-in
firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile specifications. The
CYW20733 radio has been designed to provide low power, low cost, and robust communications for applications operating in the
globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification 3.0 + EDR. The single-
chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires minimal exter-
nal components to make a fully compliant Bluetooth device. The CYW20733 is available in three package options: a 81-pin, 8 mm ×
8 mm FBGA, a 121-pin, 9 mm × 9 mm FBGA, and a 56-pin, 7 mm x 7 mm QFN.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Features
■Integrated LDO to reduce BOM cost
■Bluetooth specification 3.0 + EDR compatible
■Bluetooth HID profile version 1.1 compliant
■Bluetooth Device ID profile version 1.3 compliant
■Supports AFH
■Excellent receiver sensitivity
■On-chip support for common keyboard and mouse inter-
faces eliminates external processor
■Infrared (IR) modulator
■IR learning
■Integrated 200 mW filterless Class-D audio amplifier
■Triac control
■Triggered Broadcom Fast Connect
■One I/O capable of sinking 100 mA for high- current drive
applications
■Programmable key scan matrix interface, up to 8 × 20 key-
scanning matrix
■Three-axis quadrature signal decoder
■On-chip support for serial peripheral interface (master and
slave modes)
■Broadcom Serial Communications Interface (compatible
with Philips® I2C slaves)
■Two independent half-duplex PCM/I2S interfaces
■Real-time clock supported with 32.768 kHz oscillator
■Programmable output power control meets Class 2 or
Class 3 requirements
■On-chip PA with a maximum output power of +10dBm with-
out external component
■Integrated ARM7TDMI-S™-based microprocessor core
■On-chip power on reset (POR)
■On-chip software control power management unit
■Three package types available:
❐81-pin FBGA package (8 mm × 8 mm)
❐121-pin FBGA package (9 mm × 9 mm)
❐56-pin QFN package (7 mm x 7 mm)
■RoHS compliant
Applications
■Game controllers
■Wireless pointing devices: mice, trackballs
■Wireless keyboards
■Joysticks
■Point-of-sale (POS) input devices
■Remote controls
■Home automation
■3D glasses
Broadcom Part Number Cypress Part Number
BCM20733 CYW20733
BCM20733A3KFB1G CYW20733A3KFB1G
BCM20733A3KFB2G CYW20733A3KFB2G
BCM20733A3KML1G CYW20733A3KML1G

Document No. 002-14859 Rev. *S Page 2 of 67
CYW20733
Figure 1. Functional Block Diagram
Keyboard
Matrix
Scanner
w/FIFO
3-Axis
Mouse
Signal
Controller
Processing
Unit
(ARM7)
System Bus
Bluetooth
Baseband
Core
2.4 GHz
Radio
RF Control
and Data
T/R
Switch
RF I/O
GPIO
Control/
Status
Registers
Frequency
Synthesizer
57 GPIO Pins
Ref Xtal
LDO
CTRL
I/O Ring Bus
I/O Ring
Control
Registers
Peripheral
Interface
Block
1.2V VDDC
Domain
VDDO Domain
WAKE
1.2V
LDO
1.62V -3.6V
1.2V
VDDC
Volt. Trans
BSC/SPI
Master
Interface
(BSC is I2C-
compat)
SDA/
MOSI
SCK
6 quadrature inputs
(3 pair) + Hi -current
Driver Controls
8 x 20
Scan
Matrix
57 GPIO
32 kHz
LPCLK
28 ADC
Inputs
24 MHz
24 MHz
AutoCal
MISO
1.2V VDDRF
Domain
PWM
WDT
128 kHz
LPO
÷4
32 kHz
LPCLK
128 kHz
LPCLK
32 kHz Xtal (opƟonal)
Power
1.2V
POR
1.2V
Test
UART
IR
I/O
IR
Mod.
and
Learning
SPI
M/S
MIA
POR
CT ɇѐ
ADC
28 ADC
Inputs
VSS,
VDDO,
VDDC
Periph
UART
Tx
Rx
RTSN
CTSN
Muxed on GPIO
384K
ROM
80K
RAM
High
Sink IO
PMU
Digital
Audio
Block
Tx
Rx
RTSN
CTSN
Class-D
Driver
Speaker
3V
Speaker
Out

Document No. 002-14859 Rev. *S Page 3 of 67
CYW20733
Contents
1.Functional Description ....................................... 4
1.1 Integrated Radio Transceiver .............................. 4
1.1.1 Transmitter Path ...................................... 4
1.1.2 Receiver Path .......................................... 4
1.1.3 Local Oscillator ........................................ 4
1.1.4 Calibration ............................................... 4
1.1.5 Internal LDO Regulator ............................ 4
1.2 Microprocessor Unit ............................................ 5
1.2.1 EEPROM Interface .................................. 5
1.2.2 Serial Flash Interface ............................... 5
1.2.3 Internal Reset .......................................... 5
1.2.4 External Reset ......................................... 6
1.3 Bluetooth Baseband Core ................................... 6
1.3.1 Frequency Hopping Generator ................ 6
1.3.2 E0 Encryption .......................................... 6
1.3.3 Link Control Layer ................................... 6
1.3.4 Adaptive Frequency Hopping .................. 6
1.3.5 Bluetooth Version 3.0 Features ............... 6
1.3.6 Test Mode Support .................................. 7
1.4 Peripheral Transport Unit (PTU) ......................... 7
1.4.1 Broadcom Serial Control Interface .......... 7
1.4.2 UART Interface ........................................ 8
1.5 PCM Interface ..................................................... 9
1.5.1 System Diagram ...................................... 9
1.5.2 Slot Mapping .......................................... 10
1.5.3 Frame Synchronization .......................... 10
1.5.4 Data Formatting ..................................... 10
1.6 I2S Interface ...................................................... 10
1.7 Clock Frequencies ............................................ 10
1.7.1 Crystal Oscillator ................................... 10
1.8 GPIO Port .......................................................... 12
1.9 Keyboard Scanner ............................................ 12
1.9.1 Theory of Operation ............................... 13
1.10 Mouse Quadrature Signal Decoder ................... 13
1.10.1 Theory of Operation ............................... 13
1.11 ADC Port ........................................................... 13
1.12 PWM ................................................................. 14
1.13 Serial Peripheral Interface ................................. 15
1.14 Infrared Modulator ..............................................18
1.15 Infrared Learning ................................................19
1.16 Shutter Control for 3D Glasses ..........................19
1.17 Triac Control .......................................................20
1.18 Cypress Proprietary Control Signalling
and Triggered Broadcom Fast Connect .............20
1.19 Integrated Filterless Class-D Audio Amplifier .....20
1.20 High-Current I/O .................................................21
1.21 Power Management Unit ....................................22
1.21.1 RF Power Management ..........................22
1.21.2 Host Controller Power Management ......22
1.21.3 BBC Power Management .......................22
2.Pin Assignments............................................... 23
2.1 Ball Maps ...........................................................29
2.1.1 81-Pin FBGA Ball Map ...........................29
2.1.2 121-Pin FBGA Ball Map .........................31
2.1.3 56-Pin QFN Diagram ..............................32
3.Specifications.................................................... 33
3.1 Electrical Characteristics ....................................33
3.2 RF Specifications ...............................................37
3.3 Timing and AC Characteristics ...........................39
3.3.1 UART Timing ..........................................39
3.3.2 SPI Timing ..............................................40
3.3.3 BSC Interface Timing .............................41
3.3.4 PCM Interface Timing .............................43
3.3.5 I2S Timing ...............................................48
4.Mechanical Information.................................... 53
4.0.1 Tape Reel and Packaging
Specifications .........................................56
5.Ordering Information ........................................ 62
6.IoT Resources ................................................... 62
A.Acronyms and Abbreviations.......................... 62
Document History........................................................... 64
Sales, Solutions, and Legal Information ...................... 67

Document No. 002-14859 Rev. *S Page 4 of 67
CYW20733
1. Functional Description
1.1 Integrated Radio Transceiver
The CYW20733 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low power, low cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 + EDR and meets or exceeds the requirements to
provide the highest communication link quality of service.
1.1.1 Transmitter Path
The CYW20733 features a fully integrated zero IF transmitter. The baseband transmit data is GFSK modulated in the modem block
and upconverted to the 2.4 GHz ISM band. The transmit path consists of signal filtering,
I/Q upconversion, output power amplification, and RF filtering. It also incorporates the /4-DQPSK and 8-DPSK modulation schemes,
which support the 2 Mbps and 3 Mbps enhanced data rates, respectively.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and
8-DPSK signals. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the
transmitted signal and is much more stable than direct VCO modulation schemes.
Power Amplifier
The integrated power amplifier (PA) for the CYW20733 can transmit at a maximum power of +4 dBm for class 2 operation. The transmit
power levels are for basic rate and EDR. Due to the linear nature of the PA, combined with some integrated filtering, no external filters
are required for meeting Bluetooth and regulatory harmonic and spurious requirements.
The CYW20733 internal PA can deliver a maximum output power of +10 dBm for basic rate and +8 dBm for EDR with a flexible supply
range of 2.5V to 3.0V.
1.1.2 Receiver Path
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation
enables the CYW20733 to be used in most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20733 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
1.1.3 Local Oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO
subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW20733 uses an internal RF and IF
loop filter.
1.1.4 Calibration
The CYW20733 radio transceiver features an automated calibration scheme that is self-contained in the radio. No user interaction is
required during normal operation or during manufacturing to provide the optimal performance. Calibration will optimize the gain and
phase performance of all the major blocks within the radio to within 2% of optimal conditions. Calibrated blocks include filters, the
matching networks between key components, and key gain blocks. The calibration process corrects for both process and temperature
variations. It occurs transparently during normal operation and the setting time of the hops and will calibrate for temperature variations
as the device cools and heats during normal operation in its environment.
1.1.5 Internal LDO Regulator
To reduce the external BOM, the CYW20733 has an integrated 1.2V LDO regulator to provide power to the digital and RF circuits and
system components. The 1.2V LDO regulator operates from a 1.62V to 3.63V input supply with a 60 mA maximum load current.
In noisy environments, a ferrite bead may be needed between the digital and RF supply pins to isolate noise coupling and suppress
noise into the RF circuits.
Note: Always place the decoupling capacitors near the pins as close together as possible.

Document No. 002-14859 Rev. *S Page 5 of 67
CYW20733
1.2 Microprocessor Unit
The CYW20733 microprocessor unit (µPU) runs software from the link control (LC) layer up to the Human Interface Device (HID). The
microprocessor is based on an ARM7™ 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU
has 320 KB of ROM for program storage and boot-up, 80 KB of RAM for scratch-pad data, and patch RAM code.
The internal boot ROM allows for flexibility during power-on reset to enable the same device to be used in various configurations,
including UART, and with an external serial EEPROM or with an external flash memory. At power-up, the lower layer protocol stack
is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.2.1 EEPROM Interface
The CYW20733 provides the BSC (Broadcom Serial Control) master interface; the BSC is programmed by the CPU to generate four
different types of BSC transfers on the bus: read-only, write-only, combined read/write, and combined write/read. BSC supports both
low-speed and fast mode devices. The BSC is compatible with a Philips® I2C slave device, except that master arbitration (multiple
I2C masters contending for the bus) is not supported. Native support for Microchip® 24LC128, Microchip 24AA128, and STMicroelec-
tronics® M24128-BR is included.
The EEPROM can contain customer application configuration information, including: application code, configuration data, patches,
pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.
1.2.2 Serial Flash Interface
The CYW20733 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
■Atmel® AT25BCM512B
■MXIC MX25V512ZUI-20G
1.2.3 Internal Reset
The CYW20733 has an integrated power-on reset circuit that resets all circuits to a known power-on state.
Figure 1. Internal Reset Timing
VDDO
VDDOPOR
VDDC
VDDOPORthreshold
VDDOPORdelay
~2ms
VDDCPOR
VDDCPORthreshold
VDDCPORdelay
~2ms
BasebandReset
Crystal
warm‐up
delay:
~5ms
CrystalEnable
StartreadingEEPROMandfirmwareboot.

Document No. 002-14859 Rev. *S Page 6 of 67
CYW20733
1.2.4 External Reset
An external active-low reset signal, RESET_N, can be used to put the CYW20733 in the reset state. The RESET_N pin has an internal
pull-up resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after
the VDDO supply voltage level has been stabilized.
Figure 2. External Reset Timing
1.3 Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data
into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these
functions, it independently handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/
RX data before sending over the air:
■Receive Functions: Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic
redundancy check (CRC), data decryption, and data de-whitening.
■Transmit Functions: Data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and
data whitening.
1.3.1 Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,
Bluetooth clock, and the device address.
1.3.2 E0 Encryption
The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide
minimal intervention.
1.3.3 Link Control Layer
The Link Control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit
(LCU). This layer consists of the command controller, which takes commands from the software, and other controllers that are
activated or configured by the command controller to perform the link control tasks. Each task performs in a different state in the
Bluetooth link controller. STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page
scan, inquiry, inquiry scan, and sniff.
1.3.4 Adaptive Frequency Hopping
The CYW20733 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map
selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop
map.
1.3.5 Bluetooth Version 3.0 Features
The CYW20733 is fully compliant with the Bluetooth 3.0 standard, including the following options:
RESET_N
Pulsewidth
>20µs
CrystalEnable
BasebandReset
StartreadingEEPROMandfirmwareboot.
Crystal
warm‐up
delay:
~5ms

Document No. 002-14859 Rev. *S Page 7 of 67
CYW20733
■Enhanced power control
■HCI read, encryption key size command
The CYW20733 supports all of the new Bluetooth version 2.1 features:
■Extended inquiry response
■Sniff subrating
■Encryption pause and resume
■Secure simple pairing
■Link supervision timeout changed event
■Erroneous data reporting
■Non-automatically flushable packet boundary flag
■Security Mode 4
1.3.6 Test Mode Support
The CYW20733 fully supports Bluetooth Test Mode, as described in Part 1 of the Bluetooth System Version 2.1 specification. This
includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth test mode, the device supports enhanced testing features to simplify RF debugging and qualifi-
cation and type approval testing. These features include:
■Fixed frequency carrier wave (unmodulated) transmission
■Simplified type approval measurements (Japan)
■Aid in transmitter performance analysis
■Fixed frequency constant receiver mode
■Receiver output directed to I/O pin
■Direct BER measurements using standard RF test equipment
■Facilitated spurious emissions testing for receive mode
■Fixed frequency constant transmission
■8-bit fixed pattern or PRBS-9
■Modulated signal measurements with standard RF test equipment
■Connectionless transmitter test
■Hopping or fixed frequency
■Multiple packet types
■Multiple data patterns
■Connectionless receiver test
1.4 Peripheral Transport Unit (PTU)
1.4.1 Broadcom Serial Control Interface
The CYW20733 provides a 2-pin master BSC interface that can be used to retrieve configuration information from an external
EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse
devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible wait-
state insertion by either master or slave devices.
Listed below are the transfer clock rates supported by the BSC:
■100 kHz
■400 kHz
■800 kHz (Not a standard I2C-compatible speed.)

Document No. 002-14859 Rev. *S Page 8 of 67
CYW20733
■4 MHz maximum (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The following transfer types are supported by the BSC:
■Read (up to 127 bytes can be read)
■Write (up to 127 bytes can be written)
■Read-then-Write (Up to 127 bytes can be read, and up to 127 bytes can be written.)
■Write-then-Read (Up to 127 bytes can be written, and up to 127 bytes can be read.)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20733 are required on
both SCL and SDA for proper operation.
1.4.2 UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 1.5
Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI
command. The CYW20733 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The
interface supports the Bluetooth 3.0 UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
The UART clock is 24 MHz. The baud rate of the CYW20733 UART is controlled by two values. The first is a UART clock divisor (also
called the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (also called
the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to
eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end
of each bit time.
When setting the baud rate manually, the UART clock divisor is an 8-bit value that is stored as 256 minus the chosen divisor. For
example, a divisor of 13 is stored as 256 – 13 = 243 = 0xF3.
The baud rate adjustment is also an 8-bit value, of which the four MSBs are the number of additional clock cycles to insert in the first
half of each bit time, and the four LSBs are the number of clock cycles to insert in the second half of each bit time. If either of these
two values is over eight, it is rounded to eight.
To compute the baud rate, the calculation is expressed as:
24 MHz ÷ ((16 × UART clock divisor) + total inserted 24-MHz clock cycles)
Table 2 contains example values to generate common baud rates.
Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during
normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud
rate registers.
The CYW20733 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.
Peripheral UART Interface
The CYW20733 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through
the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 3.
Table 2. Common Baud Rate Examples
Desired Baud Rate
(bps)
UART Clock Divi-
sor
Baud Rate Adjustment Actual Baud Rate
(bps)
Error
(%)
High Nibble Low Nibble
1500000 0xFF 0x00 0x00 1500000 0.00
921600 0xFF 0x05 0x05 923077 0.16
460800 0xFD 0x02 0x02 461538 0.16
230400 0xFA 0x04 0x04 230769 0.16
115200 0xF3 0x00 0x00 115385 0.16
57600 0xE6 0x00 0x00 57692 0.16
38400 0xD9 0x01 0x00 38400 0.00
28800 0xCC 0x00 0x00 28846 0.16
19200 0xB2 0x01 0x01 19200 0.00
14400 0x98 0x00 0x00 14423 0.16
9600 0x64 0x02 0x02 9600 0.00

Document No. 002-14859 Rev. *S Page 9 of 67
CYW20733
1.5 PCM Interface
The CYW20733 PCM interface can connect to linear PCM codec devices in master or slave mode. In master mode, the device
generates the PCM_BCLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM
interface as inputs to the device.
The channels can be configured to either transmit or receive, but they must be assigned to different time slots. The two half-duplex
channels cannot be combined to form a single full-duplex channel.
1.5.1 System Diagram
Figure 3 shows options for connecting the device to a PCM codec device as a master or a slave.
Figure 3. PCM Interface with Linear PCM Codec
Table 3. CYW20733 Peripheral UART
Pin Name pUART_TX pUART_RX pUART_CTS_N pUART_RTS_N
Configured pin name P0 P2 P3 P1
P5 P4 P7 P6
P24 P25 P35 P30
P31 P33 – –
P32 P34 – –
PCMInterfaceSlaveMode
PCMCodec
(Master)
CYW20733
(Slave)
PCM_IN
PCM_BCLK
PCM_SYNC
PCM_OUT
PCMInterfaceMasterMode
PCMCodec
(Slave)
CYW20733
(Master)
PCM_IN
PCM_BCLK
PCM_SYNC
PCM_OUT
PCMInterfaceHybridMode
PCMCodec
(Hybrid)
CYW20733
(Hybrid)
PCM_IN
PCM_BCLK
PCM_SYNC
PCM_OUT

Document No. 002-14859 Rev. *S Page 10 of 67
CYW20733
1.5.2 Slot Mapping
The PCM data output driver tri-states its output on unused slots to allow other devices to share the same PCM interface signals. The
data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.
1.5.3 Frame Synchronization
The device supports both short and long frame synchronization types in both master and slave configurations. In short frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the 8 kHz audio frame rate (which is a single bit period in
width) and synchronized to the rising edge of the bit clock. The PCM slave expects PCM_SYNC to be high on the falling edge of the
bit clock and the first bit of the first slot to start at the next rising edge of the clock. In the long frame synchronization mode, the frame
synchronization signal is an active-high pulse at the 8 kHz audio frame rate. However, the duration is 3-bit periods, and the pulse
starts coincident with the first bit of the first slot.
1.5.4 Data Formatting
The device can be configured to generate and accept several different data formats. The device uses 13 of the 16 bits in each PCM
frame. The location and order of these 13 bits is configurable to support various data formats on the PCM interface. The remaining
three bits are ignored on the input and may be filled with zeros, ones, a sign bit, or a programmed value on the output. The default
format is 13-bit two’s complement data, left justified, and clocked most significant bit first.
1.6 I2S Interface
The I2S interface supports up to two half-duplex channels. The channels can be configured to either transmit or receive, but they must
be assigned to different time slots (left or right). The two half-duplex channels cannot be combined to form a single full-duplex channel.
The I2S interface is capable of operating in either slave or master mode. The device supports a 16-bit data width with 8-kHz and 16-
kHz frame rates.
1.7 Clock Frequencies
The CYW20733 is set with a crystal frequency of 24 MHz.
1.7.1 Crystal Oscillator
The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load
capacitors in the 5 pF to 30 pF range are required to work with the crystal oscillator. The selection of the load capacitors is crystal
dependent. Ta b l e 5 shows the recommended crystal specification.
Table 4. PCM Interface Time-Slotting Scheme
Audio Sample Rate Time-Slotting Scheme
8 kHz The number of slots depends on the selected interface rate, as follows:
Interface rate Slot
1281
2562
5124
10248
204816
16 kHz The number of slots depends on the selected interface rate, as follows:
Interface rate Slot
2561
5122
10244
20488

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CYW20733
Figure 4. Recommended Oscillator Configuration—12 pF Load Crystal
HID Peripheral Block
The peripheral blocks of the CYW20733 all run from a single 128-kHz low-power RC oscillator. The oscillator can be turned on at the
request of any of the peripherals. If a peripheral is not enabled, it shall not assert its clock request line.
The keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock
request line if a key-press is detected.
Real-Time Clock and 32 kHz Crystal Oscillator
The CYW20733 has a 48-bit counter that can be configured to be clocked directly from a 32.768 kHz or 32.000 kHz crystal oscillator.
The real-time clock counter value is accessible via firmware.
Figure 5 shows the 32 kHz crystal (XTAL) oscillator with external components, and Table 6 lists the oscillator’s characteristics. It is a
standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis was
added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit can be operated
with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at a similar frequency. The default component values are:
R1 = 10 M, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Table 5. Reference Crystal Electrical Specifications
Parameter Conditions Min Typ Max Unit
Input signal amplitude – 400 – 2000 mVp-p
Nominal frequency – – 24.000 – MHz
Oscillation mode – Fundamental –
Frequency tolerance @25°C – ±10 – ppm
Tolerance stability over temp @0°C to +70°C – ±10 – ppm
Equivalent series resistance – – – 50 Ω
Load capacitance – – 12 – pF
Operating temperature range – 0 – +70 °C
Storage temperature range – –40 – +125 °C
Drive level – – – 200 W
Aging – – – ±10 ppm/year
Shunt capacitance – ––2pF

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CYW20733
Figure 5. 32-kHz Oscillator Block Diagram
1.8 GPIO Port
The CYW20733 has 40 general-purpose I/Os (GPIOs) in the 81-pin package and 58 GPIOs in the 121-pin package. All GPIOs support
programmable pull-ups and are capable of driving up to 8 mA at 3.3V or 4 mA at 1.8V, except P26, P27, P28, and P29, which are
capable of driving up to 16 mA at 3.3V or 8 mA at 1.8V. GPIO P57 is capable of sinking 100 mA for VDDIO = 3.0V and 60 mA for
VDDIO = 1.62V.
Port 0–Port 1, Port 8–Port 18, Port 20–Port 23, and Port 28–Port 38
All of these pins can be programmed as ADC inputs.
Port 26–Port 29
P[26:29] consist of four pins. All pins are capable of sinking up to 16 mA for LEDs. These pins also have the PWM function, which
can be used for LED dimming.
1.9 Keyboard Scanner
The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host
microcontroller to intervene. The scanner has the following features:
■Ability to turn off its clock if no keys are pressed.
■Sequential scanning of up to 160 keys in an 8 × 20 matrix.
■Programmable number of columns from 1 to 20.
■Programmable number of rows from 1 to 8.
■16-byte key-code buffer (can be augmented by firmware).
■128 kHz clock—allows scanning of full 160-key matrix in about 1.2 ms.
■N-key rollover with selective 2-key lockout if ghost is detected.
■Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs.
Table 6. XTAL Oscillator Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Unit
Output frequency Foscout – – 32.768 – kHz
Frequency tolerance – Crystal
dependent
– 100 – ppm
Start-up time Tstartup – – – 500 ms
XTAL drive level Pdrv For crystal
selection
0.5 – – W
XTAL series resistance Rseries For crystal
selection
––70k
XTAL shunt capacitance Cshunt For crystal
selection
––1.3pF
C2
C1
R1 32.768kHz
XTAL

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CYW20733
■Hardware debouncing and noise/glitch filtering.
■Low-power consumption. Single-digit µA-level sleep current.
1.9.1 Theory of Operation
The key scan block is controlled by a state machine with the following states:
Idle
The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs
on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not already enabled by another peripheral)
and the state machine to enter the scan state. Also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0.
Scan
In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. After the last row is reached, the row
counter is reset and the column counter is incremented. This cycle repeats until the row and column counters are both at their
respective terminal count values. At that point, the state machine moves into the Scan-End state.
As the keys are being scanned, the key-index counter is incremented. This counter is the value compared to the modifier key codes
stored, or in the key-code buffer if the key is not a modifier key. It can be used by the microprocessor as an index into a lookup table
of usage codes.
Also, as the nth row is scanned, the row-hit register is ORed with the current 8-bit row input values if the current column contains two
or more row hits. During the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit
was detected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set
to indicate this.
Scan End
This state determines whether any keys were detected while in the scan state. If yes, the state machine returns to the scan state. If
no, the state machine returns to the idle state, and the 128 kHz clock request signal is made inactive.
The microcontroller can poll the key status register.
1.10 Mouse Quadrature Signal Decoder
The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by an optomechanical
mouse. The decoder has the following features:
■Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options:
❐For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1.
❐For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1.
❐For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1.
■Control of up to four external high-current GPIOs to power external optoelectronics:
❐Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high currents and having multiple
high-current devices on at the same time.
❐Sample time can be staggered for each axis.
❐Sense of the control signal can be active high or active low.
❐Control signal can be tristated for off condition or driven high or low, as appropriate.
1.10.1 Theory of Operation
The mouse decoder block has four 10-bit PWMs for controlling external quadrature devices and sampling the quadrature inputs at its
core.
The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals, photodiodes, and
photodetectors.
1.11 ADC Port
The CYW20733 contains a 16-bit ADC.
Additionally:
■There are 28 analog input channels. All channels are multiplexed on various GPIOs.
■There is a built-in reference with bandgap-based reference modes.
■The maximum conversion rate is 187 kHz.
■There is a rail-to-rail input swing.

Document No. 002-14859 Rev. *S Page 14 of 67
CYW20733
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes
the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input
multiplexers that select the ADC input signal (Vinp) and the ADC reference signals (Vref).
1.12 PWM
The CYW20733 has four internal PWMs. The PWM module consists of the following:
■PWM1–4
■Each of the four PWM channels, PWM1–4, contains the following registers:
❐10-bit initial value register (read/write)
❐10-bit toggle register (read/write)
❐10-bit PWM counter value register (read)
■PWM configuration register shared among PWM1–4 (read/write). This 12-bit register is used:
❐To configure each PWM channel
❐To select the clock of each PWM channel
❐To change the phase of each PWM channel
Figure 6 on page 15 shows the structure of one PWM.
Table 7. Sampling Rate and Effective Number of Bits
Mode Effective Number of Bits (ENOB) Sampling Rate (kHz) Latencya(μs)
a. Settling time of the ADC and filter after switching channels.
Minimum Typical
0 10.4 13.0 5.859 171
1 10.2 12.6 11.7 85
2 9.7 12.0 46.875 21
3 9.3 11.5 93.75 11
4 7.9 10.0 187 5

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CYW20733
Figure 6. PWM Block Diagram
1.13 Serial Peripheral Interface
The CYW20733 has two independent SPI interfaces. One is a master-only interface (SPI_1) and the other (SPI_2) can be either a
master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user
applications, the CYW20733 has optional I/O ports that can be configured individually and separately for each functional pin, as shown
in Table 8. The CYW20733 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20733 can also act as an
SPI slave device that supports a 1.8V or 3.3V SPI master.
Note: SPI voltage depends on VDDO/VDDM; therefore, it defines the type of devices that can be supported.
Table 8. CYW20733 First SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name SCL SDA P24 –
––P26–
––P32
b
b. Default for serial flash.
P33b
––P39–
pwm_cfg_adrregister pwm#_init_val_adrregister pwm#_togg_val_adrregister
pwm#_cntr_adr
enable
cntrvalueisARMreadable
clk_sel
o_flip
10'H000
10'H3FF
10
10 10
Example:PWMcntrw/pwm#_init_val=0(dashedline)
PWMcntrw/pwm#_init_val=x(solidline)
10'Hx
pwm_out
pwm_togg_val_adr
pwm_out

Document No. 002-14859 Rev. *S Page 16 of 67
CYW20733
Table 9. CYW20733 Second SPI Set (Master Mode)
Configuration SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
1p3 p0p1–
2p3 p0p5–
3p3 p4p1–
4p3 p4p5–
5 p3 p27 p1 –
6 p3 p27 p5 –
7 p3 p38 p1 –
8 p3 p38 p5 –
9p7 p0p1–
10 p7 p0 p5 –
11 p7 p4 p1 –
12 p7 p4 p5 –
13 p7 p27 p1 –
14 p7 p27 p5 –
15 p7 p38 p1 –
16 p7 p38 p5 –
17 p24 p0 p25 –
18 p24 p4 p25 –
19 p24 p27 p25 –
20 P24 P38 P25 –
21 p36 p0 p25 –
22 p36 p4 p25 –
23 p36 p27 p25 –
24 P36 P38 p25 –

Document No. 002-14859 Rev. *S Page 17 of 67
CYW20733
Table 10. CYW20733 Second SPI Set (Slave Mode)
Configuration SPI_CLK SPI_MOSI SPI_MISO SPI_CS
1p3 p0p1p6
2p3 p0p1p2
3p3 p0p5p6
4p3 p0p5p2
5 p3 p0 p25 p6
6 p3 p0 p25 p2
7p3 p4p1p6
8p3 p4p1p2
9p3 p4p5p6
10 p3 p4 p5 p2
11 p3 p4 p25 p6
12 p3 p4 p25 p2
13 p7 p0 p1 p2
14 p7 p0 p1 p6
15 p7 p0 p5 p6
16 p7 p0 p5 p2
17 p7 p0 p25 p2
18 p7 p0 p25 p6
19 p7 p4 p1 p6
20 p7 p4 p1 p2
21 p7 p4 p5 p6
22 p7 p4 p5 p2
23 p7 p4 p25 p2
24 p7 p4 p25 p6
25 p24 p27 p1 p26
26 p24 p27 p1 p32
27 p24 p27 p1 p39
28 p24 p27 p5 p26
29 p24 p27 p5 p32
30 p24 p27 p5 p39
31 P24 P27 P25 P26
32 p24 p27 p25 p32
33 P24 P27 P25 P39
34 p24 p33 p1 p26
35 p24 p33 p1 p32
36 p24 p33 p1 p39
37 p24 p33 p5 p26
38 p24 p33 p5 p32
39 p24 p33 p5 p39
40 P24 P33 P25 P26
41 p24 p33 p25 p32
42 P24 P33 P25 P39
43 p24 p38 p1 p26
44 p24 p38 p1 p32
45 p24 p38 p1 p39

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CYW20733
1.14 Infrared Modulator
The CYW20733 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.
For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from
firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.
If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20733 IR TX firmware driver
inserts this information in a hardware FIFO and makes sure that all descriptors are played out without an underrun glitch. See Figure 7.
46 p24 p38 p5 p26
47 p24 p38 p5 p32
48 p24 p38 p5 p39
49 P24 P38 P25 P26
50 p24 p38 p25 p32
51 P24 P38 P25 P39
52 p36 p27 p1 p26
53 p36 p27 p1 p32
54 p36 p27 p1 p39
55 p36 p27 p5 p26
56 p36 p27 p5 p32
57 p36 p27 p5 p39
58 P36 P27 P25 P26
59 p36 p27 p25 p32
60 P36 P27 P25 P39
61 p36 p33 p1 p26
62 p36 p33 p1 p32
63 p36 p33 p1 p39
64 p36 p33 p5 p26
65 p36 p33 p5 p32
66 p36 p33 p5 p39
67 P36 P33 P25 P26
68 p36 p33 p25 p32
69 P36 P33 P25 P39
70 p36 p38 p1 p26
71 p36 p38 p1 p32
72 p36 p38 p1 p39
73 p36 p38 p5 p26
74 p36 p38 p5 p32
75 p36 p38 p5 p39
76 P36 P38 P25 P26
77 p36 p38 p25 p32
78 P36 P38 P25 P39
Table 10. CYW20733 Second SPI Set (Slave Mode) (Cont.)
Configuration SPI_CLK SPI_MOSI SPI_MISO SPI_CS

Document No. 002-14859 Rev. *S Page 19 of 67
CYW20733
Figure 7. Infrared TX
1.15 Infrared Learning
The CYW20733 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.
For modulated signals, the CYW20733 can detect carrier frequencies between
10–500 kHz and the duration that the signal is present or absent. The CYW20733 firmware driver supports further analysis and
compression of a learned signal. A learned signal can then be played back through the CYW20733 IR TX subsystem. See Figure 8.
Figure 8. Infrared RX
1.16 Shutter Control for 3D Glasses
The CYW20733, combined with the CYW20702, provides full system support for 3D glasses on televisions. The CYW20702 gets
frame synchronization signals from the TV, converts them into proprietary timing control messages, then passes the messages to the
CYW20733. The CYW20733 uses these messages to synchronize the shutter control for the 3D glasses with the television frames.
CYW20733
R1
VCC
Q1
R2
Infrared‐LD
D1
IRTX
U1
CYW20733
VCC
D2
Photodiode
IRRX
U3