iSBC 80/30
The iSBC 80/30 provides vectoring for
12
interrupt
levels, four
of
which are handled directly by the interrupt
processing capability
of
the 8085A CPU. These four
levels (TRAP, RST
7.5;
RST
6.5,
and RST 5.5) represent
(in decreasing order
of
priority) the four highest priority
interrupts
of
the iSBC 80/30. These four interrupts gener-
ate the following unique memory address: TRAP (24H),
RST
7.5
(3CH), RST 6.5 (34H), and RST 5.5 (2CH). An
8085A JUMP instruction at each
of
these addresses then
provides linkage
to
interrupt service routines located in-
dependently anywhere in the lower65K bytes
of
memory.
All interrupt inputs with the exception
of
TRAP may be
masked via software. The TRAP interrupt should be used
for conditions such as power-down sequences which re-
quire immediate attention by the 8085A CPU.
An Intel
8259A
Programmable Interrupt Controller
(PIC) provides vectoring for the next eight interrupt
levels. The PIC treats each true input signal condition
as
an interrupt request. After resolving the interrupt priority,
the PIC issues a single interrupt request to the CPU.
Interrupt priorities are independently programmable
under software control. Similarly, an interrupt can be
masked under software control. The programmable inter-
rupt priority modes are:
a. Fully Nested Priority. Each interrupt request has a
fixed priority: input 0
is
highest, input 7 is lowest.
b. Auto-Rotating Priority. Each interrupt request has
equal priority. Each level, after receiving service,
becomes the lowest priority level until the next
interrupt occurs.
c. Specific Priority. Software assigns lowest priority.
Priority
of
all other levels
is
in numerical sequence
based on lowest priority.
The PIC, which can be programmed
to
respond to edge-
sensitive
or
level-sensitive inputs, generates a unique
memory address for each interrupt level. These addresses
are equally spaced at intervals
of
4 to 8 (software select-
able) bytes. This 32-
or
64-byte block may be located to
begin at any 32-
or
64-byte boundary in the 65,536 byte
memory space. A single 8085A JUMP instruction at each
of
these addresses then provides linkage
to
locate each
interrupt service routine independently anywhere in
memory.
Interrupt requests may originate from
18
sources. Two
jumper-selectable interrupt requests can be automatically
generated by the Programmable Peripheral Interface
(PPI) when a byte
of
information
is
ready to be transferred
to
the 8085A CPU (i.e., input buffer
is
full)
or
a byte
of
information has been transferred to a peripheral device
(i.e.,
output buffer
is
empty). Two jumper-selectable
interrupt requests can be automatically generated by the
USART when a character
is
ready to be transferred to the
8085A CPU
(i.e.,
receive channel buffer
is
full)
or
when a
character
is
ready to be transmitted (i.e., transmit channel
data buffer is empty). A jumper-selectable interrupt
General Information
request can be generated by two
of
the programmable
counters and by the Universal Peripheral Interface (UPI).
Eight additional interrupt request lines are available to the
user for direct interfaces to user designated periphral
devices via the Multibus, and two interrupt request lines
may be jumper routed directly from peripherals via the
parallel I/O driver/ terminator section.
Control logic is also included for generation
of
a Power-
Fail Interrupt, which works in conjunction with an AC
LOW signal from an Intel iSBC 635 Power Supply
or
equivalent.
The iSBC 80/30 includes the resources for supporting a
variety
of
OEM
system requirements.
For
those appli-
cations requiring additional processing capacity and the
benefits
of
multiprocessing (i.e., several
CPU's
and/or
controllers logically sharing systems tasks with com-
munication over the Multibus), the iSBC 80/30 provides
full bus arbitration control logic. This control logic allows
up to three bus masters (e.g., any combination
of
iSBC
80/30, iSBC 80/20, DMA controller, diskette
cont~oller,
etc.)
to
share the Multibus in serial (daisy-chain) fashion
or
up
to
16
bus masters to share the Multibus using an
external parallel priority resolving network.
The Multibus arbitration logic operates synchronously
with the bus clock, which is derived either from the iSBC
80/30
or
can be optionally generated by some other bus
master. Data, however,
is
transferred via a handshake
between the controlling master and the addressed slave
module. This arrangement allows different speed control-
lers to share resources on the same bus, and transfers via
the bus proceed asynchronously. Thus, the transfer speed
is
dependent on transmitting and receiving devices only.
This design prevents slower master modules from being
handicapped in their attempts to gain control
of
the bus,
but does not restrict the speed at which faster modules can
transfer data via the same bus. The most obvious appli-
cations for the master-slave capabilities
of
the bus are
mUltiprocessorconfigurations, high-speed direct memory
access (DMA) operations, and high-speed peripheral
control, but are by
no
means limited to these three.
1-3. SYSTEM SOFTWARE
DEVELOPMENT
Intel's RMX/80 Real-Time Multitasking Software, spe-
cifically designed for Intel iSBC 80 single board com-
puters, provides the capability to monitor and control
mUltiple asynchronous external events. The RMX/80
Executive, which synchronizes and controls the execu-
tion
of
multiple tasks,
is
provided as a linkable and
relocatable module that requires
only
2K
bytes
of
memory. Optional linkage and relocatable modules for
1-3
