Intel iSBC 80 Quick user guide

iSBC 80/30
SINGLE BOARD COMPUTER
HARDWARE
REFERENCE MANUAL
Manual Order Number: 9800611 A
l
Copyrightf 1978 Intel Corporation
I Intel Corporation. 3065 Bowers Avenue, Santa Clara, California 95051 I

ii
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written consent of -Intel Corporation.
The following are trademarks of Intel Corporation and may be used only to describe Intel products:
ICE
INSITE
INTEL
INTELLEC
iSBC
LIBRARY MANAGER
MCS
MEGACHASSIS
MICROMAP
MULTI BUS
PROMPT
RMX
UPI
"SCOPE
Printed in U.S.A./852/067817.5K TL

PREFACE
This manual provides general information, installation, programming information,
principles
of operation, and service information for the Intel iSBC 80/30 Single Board
Computer. Additional information
is available in the following documents:
• Intel MCS-85 User's Manual, Order No. 98-366
• Intel UPI-41 User's Manual, Order No. 9800504
• Intel 8080/8085 Assembly Language Programming Manual, Order No. 9800301
• Intel 8255A Programmable Peripheral Interface, Application Note AP-15
• Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter, Application
Note AP-16
• Intel MULTIBUS Interfacing, Application Note AP-28
• Intel 8259 Programmable Interrupt Controller, Application Note AP-31
iii

CHAPTER 1
GENERAL INFORMATION PAGE
Introduction
.............. : . . . . . . . . . . . . . . . . . . . . .. 1-1
Description ..................................... 1-1
System Software Development .............. ' ....... 1-3
Equipment Supplied . . . . . . . . . . . . ... . . . . . . . . . . . . . .
.. 1-4
Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-4
Specifications
................................... 1-4
CHAPTER 2
PREPARATION FOR
USE
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Unpacking and Inspection
......................... 2-1
Installation Considerations . . . . . . . . . . . . . . . . . . . . . . .
.. 2-1
User-Furnished Components
..................... 2-1
Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Cooling Requirement
.. . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Physical Dimensions
............................ 2-1
Component Installation
............................ 2-3
ROM/EPROM Chips ........................... 2-3
Universal Peripheral Interface
.................... 2-4
Line Drivers and I/O Terminators . . . . . . . . . . . . . . .
.. 2-4
Rise Time/Noise Capacitors
...................... 2-4
Jumper Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-4
ROM/EPROM Configuration ..................... 2-4
On-Board RAM Addresses ...................... 2-4
On-Board 8085A Access ...................... 2-7
System Access
.............................. 2-7
Priority Interrupts
.............................. 2-8
8251A Port Configuration
....................... 2-12
8255A Port Configuration
....................... 2-12
8041/8741A Port Configuration
................... 2-12
Multibus Configuration
........................... 2-15
Signal Characteristics
........................... 2-15
Serial Priority Resolution
........................ 2-23
Parallel Priority Resolution
...................... 2-24
Power Fail/Memory Protect Configuration ............ 2-24
Parallel I/O Cabling
.............................. 2-27
Serial I/O Cabling
................................ 2-27
Board Installation
................................ 2-29
CHAPTER 3
PROGRAMMING INFORMATION
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Failsafe
Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Memory Addressing
.............................. 3-1
I/O Addressing .................................. 3-2
System Initialization
.............................. 3-2
8251A USART Programming
...................... 3-3
Mode Instruction Format
........................ 3-3
Sync Characters
............................... 3-3
Command Instruction Format .................... 3-3
Reset
........................................ 3-4
Addressing
................................... 3-4
Initialization
.................................. 3-4
iv
CONTENTS
PAGE
Operation ..................................... 3-5
Data Input/Output
............................ 3-5
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 3-6
8253 PIT Programming
........................... 3-6
Mode Control Word and Count
................... 3-7
Addressing
................................... 3-10
Initialization
.................................. 3-10
Operation ..................................... 3-11
Counter Read
............................... 3-11
Clock Frequency/Divide Ratio Selection
.......... 3-11
Rate Generator/Interval Timer
.................. 3-12
Interrupt Timer
.............................. 3-12
8255A PPI Programming
.......................... 3-13
Control Word Format
........................... 3-13
Addressing
................................... 3-14
Initialization
.................................. 3-14
Operation ..................................... 3-14
Read Operation
.............................. 3-14
Write Operation
............................. 3-14
8259A PIC Programming
.......................... 3-14
Interrupt Priority Modes
......................... 3-14
Fully Nested Mode
........................... 3-14
Auto-Rotating Mode
.......................... 3-15
Specific Rotating Mode
....................... 3-15
Interrupt Mask
................................ 3-15
Status Read
................................... 3-15
Initialization Command Words
................... 3-15
Operation Command Words ...................... 3-16
Addressing
................................... 3-16
Initialization
.................................. 3-16
Operation ..................................... 3-16
8041/8741A UPI Programming ..................... 3-17
Interrupt Handling
............................... 3-22
TRAP Input ................................... 3-22
RST 7.5, 6.5, 5.5 Inputs
........................ 3-23
INTR Input
................................... 3- 23
CHAPTER 4
PRINCIPLES
OF OPERATION
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Interval
Timer. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 4-1
Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Universal Peripheral Interface
.. . . . . . . . . . . . . . . . . .. 4-2
Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-2
ROM/EPROM Configuration. . . . . . . . . . . . . . . . . . . .. 4-2
RAM Configuration
............................ 4-2
Bus Interface
.................................. 4-2
Dual-Port Control
.............................. 4-2
Circuit Analysis
................... ' ............. ; .... '. 4-2

PAGE
Initialization
........ - .......................... 4-2
Clock Circuits
................................. 4-3
SOS5A CPU Timing .... '" ..................... 4-3
Instruction Timing
........................... 4-3
Opcode Fetch Timing. . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Memory Read Timing
........................ 4-6
I/O Read Timing ............................. 4-6
Memory Write Timing ........................ 4-6
I/O Write Timing ............................ 4-7
Interrupt Acknowledge Timing
................. 4-7
Address Bus
.................................. 4-9
Bus Time Out
................................. 4-9
Data Bus
..................................... '4-9
Read/Write Signal Generation . . . . . . . . . . . . . . . . . .
.. 4-9
I/O Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . .. 4-9
Memory Control Signals
...................... 4-9
_Dual Port Control Logic. . . . . . . . . . . . . . . . . . . . . . . .. 4-9
Bus Access Timing
.......................... .4-12
CPU Access Timing ......................... .4-12
Multibus Interface
............................. .4-12
I/O Operation ................................ .4-13
TABLE
1-1.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
TITLE PAGE
Specifications
........................... 1-4
User-Furnished and Installed Components .... 2-2
User-Furnished Connector Details ........... 2-3
Line Driver and I/O Terminator Locations .... 2-4
Jumper Selectable Options. . . . . . . . . . . . . . .
.. 2-5
ROM/EPROM Configuration Jumpers ....... 2-7
Jumper Configuration for On-Board
8085A CPU Access
of On-Board RAM .... 2-7
65K Page System Memory Selection
........ 2-S
SK/16K Block Selection Within 65K Page
.... 2-S
Priority Interrupt Jumper Matrix
............ 2-11
Connector
13 Pin Assignments Vs.
Jumper Configuration ................... 2-12
8255A Port Configuration Jumpers
.......... 2-13
Multibus Connector PI Pin Assignments ..... 2-16
Multibus Signal Functions ................. 2-17
iSBC 80/30 DC Characteristics ............. 2-18
CONTENTS (Continued)
PAGE
On-Board I/O Operation ..................... .4-13
System I/O Operation ........................ .4-13
ROM/EPROM Operation ........ ' ............... .4-13
RAM Operation
.............................. .4-14
RAM Controller
............................ .4-14
On-Board Read/Write Operation ............... .4-14
Bus Read/Write Operation
.................... .4-14
Interrupt Operation
............................ .4-15
CHAPTER 5
SERVICE INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
Replaceable Parts
............................ ; ... 5-1
Service Diagrams ................................ 5-1
Service and Repair Assistance ...................... 5-1
APPENDIX A
8085 INSTRUCTION SET
APPENDIX B
TELETYPEWRITER MODIFICATIONS
TABLE
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
3-1.
3-2.
3-3.
3-4.
TABLES
TITLE PAGE
lSBC 80/30 'At Characteristics
(Master Mode)
........................ 2-21
iSBC SO/3~ AC Characteristics (Slave Mode) .2-21
AuxHiary Connector P2 Pin Assignments ..... 2-26
Auxiliary Signal (Connector P2)
DC Characteristics ..................... 2-26
Connector 11 Pin Assignments ............. 2-27
Connector 12 Pin Assignments ............. 2-27
Parallel I/O Signal (Connector 11/12)
DC Characteristics ..................... 2-2S
Connector 13 Vs. RS232C Pin COITl!spondence2-29
On-Board Memory Address (for CPU Access) 3-1
I/O Address Assignments .........•........ 3-2
Typical USART Mode or Command
Instruction Subroutine
.................. 3-5
Typical USART Data Character
Read Subroutine ....................... 3-6
v

TABLE
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
FIGURE
1-1.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
. 3-7.
3-8.
3-9.
3-10.
3-11.
vi
TITLE
PAGE
Typical USART Data Character
Write Subroutine
....................... 3-6
Typical USART Status Read Subroutine
..... 3-7
PIT Counter Operation Vs. Gate Inputs ...... 3-10
Typical PIT Control Word Subroutine
....... 3-10
Typical PIT Count Value Load Subroutine
... 3-11
Typical PIT Counter Read Subroutine
....... 3-11
PIT Count Value Vs. Rate Multiplier
for Each Baud Rate
................... .3-12
PIT Rate Generator Frequencies and
Timer Intervals
.... c •••••••••••••••••••• 3-13
PIT Time Intervals Vs. Timer Counts ....... 3-13
Typical PPI Initialization Subroutine
......... 3-14
Typical PPI Port Read Subroutine
........... 3-14
Typical PPI Port Write Subroutine
.......... 3-15
PIC Device Address Insertion .............. 3-16
TITLE PAGE
iSBC 80/30 Single Board Computer . . . . . . . .. 1-1
Jumper Configuration for Multibus Access of
On-Board RAM (16-Bit Address System) .. 2-9
Jumper Configuration for Multibus Access
of
On-Board RAM (20-Bit Address System) .. 2-10
Bus Exchange Timing (Master Mode)
....... 2-22
Bus Exchange Timing (Slave Mode)
......... 2-23
Serial Priority Resolution Scheme
........... 2-24
Parallel Priority Resolution Scheme ......... 2-25
USART Synchronous Mode Instruction
Word Format
.......................... 3-3
USART Synchronous Mode Transmission
Format
............................... 3-3
USART Asynchronous Mode Instruction
Word Format
.......................... 3-3
USART Asynchronous Mode Transmission
Format
............................... 3-4
USART Command Instruction Word Format .. 3-4
Typical USART Initialization and
I/O Data Sequence ..................... 3-5
USART Status Read Format ............... 3-7
PIT Mode Control Word Format ............ 3-8
PIT Programming Sequence Examples ....... 3-9
PIT Counter Register Latch Control
Word Format.
......................... 3-.12
PPI Control Word Format ................. 3-13
TABLE
3~18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
4-1.
5-1.
5-2.
TABLES (Continued)
TITLE
PAGE
Typical PIC Initialization Subroutine ........ 3'-17
PIC Operation Procedures
................. 3-19
Typical PIC Interrupt Request Register
Read Subroutine
....................... 3-20
Typical PIC In-Service Register
Read Subroutine
..... ' .. ' ................ 3-20
Typical PIC Set Mask Register Subroutine .... 3-20
Typical PIC Mask Register Read Subroutine .. 3-21
Typical PIC End-of-Interrupt
Command Subroutine
................... 3-21
Typical UPI Data Byte Read Subroutine
..... 3-22
Typical UPI Data Byte Write Subroutine
..... 3-22
8085A CPU Restart Interrupt V~ctors ........ 3-22
CPU Status and Control Lines. . . . . . . . . . . . .. 4-4
Replaceable Parts
.......... ,............. 5-1
List of Manufacturers' Codes
.............. 5-3
ILLUSTRATIONS
FIGURE
TITLE PAGE
3-12.
3-13.
3-14.
3-15.
3-16.
4.-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
5-1.
5-2.
5-3.
5-4.
PPI Port C Bit Set/Reset Control
Word Format
.......................... 3-15
PIC Device Interrupt Addresses ............. 3-16
PIC Initialization Command Word Formats ... 3-17
PIC Operation Control Word Formats ........ 3-18
UPI Data Bus Buffer and
Status Registers
........................ 3-21
iSBC 80/30 Input/Output and
Interrupt Block Diagram
............... .4-17
iSBC 80/30 ROM/EPROM and Dual Port
RAM Block Diagram .................. .4-19
Typical CPU Instruction Cycle
............. 4-4
Opcode Fetch Machine Cycle .............. 4-5
Opcode Fetch Machine Cycle (With Wait) .... 4-5
Memory Read (or I/O Read) Machine Cycles . 4-6
Memory Write (or I/O Write) Machine Cycles 4-7
Interrupt Acknowledge Machine Cycles
...... 4-8
Dual Port Control Bus Access Timing
With CPU Lockout
.................... .4-10
Dual Port Control CPU Access Timing
With Bus Lockout
.................... .4-11
iSBC 80/30 Parts Locations Diagram
........ 5-5
iSBC 80/30 Schematic Diagram
............ 5-7
iSBC 604 Schematic Diagram
.............. 5-25
iSBC 614 Schematic Diagram
.............. 5-27

1-1. INTRODUCTION
The iSBC 80/30 Single Board Computer, which is a
member
of Intel's complete line of iSBC 80 computer
products,
is a computer system on a single printed-
circuit assembly. The iSBC 80/30 includes a central pro-
cessor unit (CPU),
16K bytes of dynamic random access
memory (RAM), one serial and three parallel I/O ports,
aprogrammable
timer~ priority interrupt logic, and Multi-
bus control logic. Also included
is dual portcontrol logic
to allow the iSBC 80/30 to act
as a slave RAM device
to other bus masters in the system. Provision is made
for user-installation
of masked or programmable read
only memory (ROM
or EPROM) and an Intel 8041 or
8741A Universal Peripheral Interface.
1-2. DESCRIPTION
The iSBC 80/30 Single Board Computer (figure 1-1) is
controlled by an Intel 8085A Microprocessor (CPU),
which includes six 8-bit general-purpose registers and an
accumulator. The six general-purpose registers may be
addressed individually
or in pairs, which allows both
single precision and double precision operations. The
CPU has a 16-bit program counter which allows direct
CHAPTER 1
GENERAL INFORMATION
addressing of up to 65K of memory. An external stack,
located within any portion
of read/write memory, may be
used
as a last-in/first-out storage area for the contents of
the program counter, flags, accumulator, and all six
general-purpose registers. A 16-bit stack pointer controls
the addressing
of this external stack, which allows sub-
routine nesting that
is bounded only by the 65K address
limitation.
The iSBC 80/30 has an internal bus for all on-board
memory and I/O operations and accesses the system bus
(Multibus) for all external memory and I/O operations.
Hence, local (on-board) operations do not involve the
Multibus and allow true parallel processing when several
bus masters (e.g., DMA devices and other single board
computers) are used in a multimaster scheme.
The
16K of dynamic RAM is implemented with eight Intel
2717 chips and an Intel 8202 Dynamic RAM Controller.
Dual port control logic is included to interface this 16K
RAM with the Multibus
so that the iSBC 80/30 can func-
tion as a slave RAM device when not in control
of the
Multibus. The CPU has priority when accessing on-board
RAM. After the CPU completes its read
or write opera-
tion, the controlling bus master
is allowed to access RAM
and complete its operation. Where both the CPU and the
controlling bus master have the need to write
or read
PARALLEL
1/0
OPTIONAL
8041/8741
1/0 SERIAL
1/0
(MULTIBUS) (AUXILIARY)
611-1 Figure 1-1. iSBC 80/30 Single Board Computer
1-1

General Information
several words to or from on-board RAM, their operations
are interleaved. The slave RAM decode logic allows ex-
tended Multibus addressing
so that bus masters having a
20-bit address capability can partition the iSBC 80/30
RAM into any 8K or 16K segment in a I-megabyte
address space. The CPU, however, has only
16 address
lines and memory must therefore reside in the 0-65K byte
address space. There
is no conflict in assigning RAM
addresses for CPU access and slave access since separate
decoding logic is used.
Jumpers are included to allow the user to reserve 8K
bytes
of on-board RAM for use by the 8085A CPU only.
This reserved RAM address space
is not accessible via the
Multibus and does not occupy any system address space.
Two IC sockets are included to accommodate up
to .8K of
user-installed ROM or EPROM. Configurationjumpers
allow ROM
or EPROM to be installed in lK, 2K, or 4K
increments. All on-board ROM/EPROM operations are
performed at maximum processor speed.
The iSBC 80/30 includes 24 programmable parallel I/O
lines implemented by means of an Intel 8255A Program-
mable Peripheral Interface (PPI). The system software is
used to configure the I/O lines in any combination
of
unidirectional input/output and bidirectional ports. The
I/O interface may be customized to meet specific periph-
eral requirements and, in order
to take full advantage
of the large number of possible I/O configurations, IC
sockets are provided for interchangeable I/O line drivers
and terminators. Hence, the flexibility
of the parallel
I/O interface is further enhanced by the capability of
selecting the appropriate combination of optional line
drivers and terminators
to provide the required sink
current, polarity, and drive/termination characteristi9s
for each application. The 24 programmable I/O lines and
signal ground lines are brought out to a 50-pin edge
connector
(11) that mates with flat, woven, or round
cable.
Sockets are provided
fora user-supplied Inte18041/8741A
Universal Programmable Interface (UPI) and associated
line drivers and terminators. The 8041/8741A is a single-
chip microcomputer which contains a CPU, ) K bytes
of
ROM (8041) or EPROM (8741),64 bytes of RAM, 16
programmable I/O lines, and an 8-bit timer. Special inter-
face registers are included in the chip which enable the
UPI to function as a slave processor to the 8085A CPU.
The UPI allows the user to specify algorithms for con-
trolling user peripherals directly in the chip, thereby
relieving the 8085A CPU for other system functions. An
RS232C driver and an RS232C receiver are included
so
that the UPI may optionally be used to handle a simple
serial I/O interface. In addiiion to providing the capability
of user-supplied algorithms for the 8041/8741A the
iSBC 80/30 supports all the preprogrammed 8041/8741A
devices such
as the Intel 8278 Keyboard Encoder, 8294
Data Encryption Controller, and 8295 Matrix Printer
Driver.
1-2
iSBC 80/30
The RS232C compatible serial I/O port is controlled and
interfaced
by an Intel 8251A US ART (Universal Syn-
chronous/Asynchronous Receiver/Transmitter) chip. The
USART is individually programmable for operation in
most synchronous
or asynchronous serial datatransmission
formats (including IBM Bi-Sync).
In the synchronous mode the following are programmable:
a. Character length,
b. Sync character (or characters), and
c. Parity.
In the asynchronous mode the following are programmable:
a. Character length,
b. Baud rate factor (clock divide ratios of 1, 16, or 64).
c. Stop bits, and
d
.. Parity.
In both the synchronous and asynchronous modes, the
serial I/O portfeatures half-
or full-duplex, double-buffered
transmit and receive capability. In addition, USART error
detection circuits can check for parity, overrun, and fram-
ing errors. The USART transmit and receive clock rates are
supplied by a programmable baud rate/time generator.
These clocks may optionally be supplied from an external
source. The RS232C command lines, serial data lines, and
signal ground lines are brought.out to a 50-pin edge
connector
(13) that mates with flat or round cable.
Three independent, fully programmable 16-bit interval
timer/event counters are provided by an Intel 8253
Programmable Interval Timer (PIT). Each counter
is
capable of operating in either BCD or binary modes; two
of these counters are available to the systems designer to
generate accurate time intervals under software control.
Routing for the outputs and gate/trigger inputs
of two of
these counters is jumper-selectable; the outputs of these
two counters may be independently routed to the 8259A
Programmable Interrupt Controller (PIC), the I/O line
drivers associatedwith the 8255A Programmable Periph-
eral Interface (PPI), the 8041/8741A Universal Program-
mable Interface, or used as inputs to the 8255A PPI
and 8041/8741A (UPI). The gate/trigger inputs ofthe two
counters may be routed
to I/O terminators associated with
the 8255A PPI
or as output connections from the 8255A
PPI. The third counter is used as a programmable baud
rate generator for the serial I/O port. In utilizing the iSBC
80/30, the systems designer simply configures, via
software, each counter independently
to meet system
requirements. Whenever a given time delay
or count is
needed, software commands to ·the 8253 PIT select the
desired function. The contents
of each counter may be
read at any time during system operation with simple
operations for event counting applications, and special
commands are included
so that the contents of each
counter can be read
"on the fly."

iSBC 80/30
The iSBC 80/30 provides vectoring for 12 interrupt
levels, four
of which are handled directly by the interrupt
processing capability
of the 8085A CPU. These four
levels (TRAP, RST
7.5; RST 6.5, and RST 5.5) represent
(in decreasing order
of priority) the four highest priority
interrupts
of the iSBC 80/30. These four interrupts gener-
ate the following unique memory address: TRAP (24H),
RST 7.5 (3CH), RST 6.5 (34H), and RST 5.5 (2CH). An
8085A JUMP instruction at each of these addresses then
provides linkage
to interrupt service routines located in-
dependently anywhere in the lower65K bytes
of memory.
All interrupt inputs with the exception of TRAP may be
masked via software. The TRAP interrupt should be used
for conditions such as power-down sequences which re-
quire immediate attention by the 8085A CPU.
An Intel 8259A Programmable Interrupt Controller
(PIC) provides vectoring for the next eight interrupt
levels. The PIC treats each true input signal condition
as
an interrupt request. After resolving the interrupt priority,
the PIC issues a single interrupt request to the CPU.
Interrupt priorities are independently programmable
under software control. Similarly, an interrupt can be
masked under software control. The programmable inter-
rupt priority modes are:
a. Fully Nested Priority. Each interrupt request has a
fixed priority: input 0
is highest, input 7 is lowest.
b. Auto-Rotating Priority. Each interrupt request has
equal priority. Each level, after receiving service,
becomes the lowest priority level until the next
interrupt occurs.
c. Specific Priority. Software assigns lowest priority.
Priority of all other levels is in numerical sequence
based on lowest priority.
The PIC, which can be programmed
to respond to edge-
sensitive
or level-sensitive inputs, generates a unique
memory address for each interrupt level. These addresses
are equally spaced at intervals
of 4 to 8 (software select-
able) bytes. This 32-
or 64-byte block may be located to
begin at any 32-
or 64-byte boundary in the 65,536 byte
memory space. A single 8085A JUMP instruction at each
of these addresses then provides linkage to locate each
interrupt service routine independently anywhere in
memory.
Interrupt requests may originate from 18 sources. Two
jumper-selectable interrupt requests can be automatically
generated by the Programmable Peripheral Interface
(PPI) when a byte of information is ready to be transferred
to the 8085A CPU (i.e., input buffer is full) or a byte of
information has been transferred to a peripheral device
(i.e., output buffer is empty). Two jumper-selectable
interrupt requests can be automatically generated by the
USART when a character is ready to be transferred to the
8085A CPU (i.e., receive channel buffer is full) or when a
character
is ready to be transmitted (i.e., transmit channel
data buffer is empty). A jumper-selectable interrupt
General Information
request can be generated by two
of the programmable
counters and by the Universal Peripheral Interface (UPI).
Eight additional interrupt request lines are available to the
user for direct interfaces to user designated periphral
devices via the Multibus, and two interrupt request lines
may be jumper routed directly from peripherals via the
parallel I/O driver/ terminator section.
Control logic is also included for generation
of a Power-
Fail Interrupt, which works in conjunction with an AC
LOW signal from an Intel iSBC 635 Power Supply or
equivalent.
The iSBC 80/30 includes the resources for supporting a
variety
of OEM system requirements. For those appli-
cations requiring additional processing capacity and the
benefits
of multiprocessing (i.e., several CPU's and/or
controllers logically sharing systems tasks with com-
munication over the Multibus), the iSBC 80/30 provides
full bus arbitration control logic. This control logic allows
up to three bus masters (e.g., any combination
of iSBC
80/30, iSBC 80/20, DMA controller, diskette
cont~oller,
etc.) to share the Multibus in serial (daisy-chain) fashion
or up to 16 bus masters to share the Multibus using an
external parallel priority resolving network.
The Multibus arbitration logic operates synchronously
with the bus clock, which is derived either from the iSBC
80/30
or can be optionally generated by some other bus
master. Data, however,
is transferred via a handshake
between the controlling master and the addressed slave
module. This arrangement allows different speed control-
lers to share resources on the same bus, and transfers via
the bus proceed asynchronously. Thus, the transfer speed
is dependent on transmitting and receiving devices only.
This design prevents slower master modules from being
handicapped in their attempts to gain control
of the bus,
but does not restrict the speed at which faster modules can
transfer data via the same bus. The most obvious appli-
cations for the master-slave capabilities
of the bus are
mUltiprocessorconfigurations, high-speed direct memory
access (DMA) operations, and high-speed peripheral
control, but are by
no means limited to these three.
1-3. SYSTEM SOFTWARE
DEVELOPMENT
Intel's RMX/80 Real-Time Multitasking Software, spe-
cifically designed for Intel iSBC 80 single board com-
puters, provides the capability to monitor and control
mUltiple asynchronous external events. The RMX/80
Executive, which synchronizes and controls the execu-
tion
of multiple tasks, is provided as a linkable and
relocatable module that requires
only 2K bytes of
memory. Optional linkage and relocatable modules for
1-3

General Information
teletypewriter and CRT control, diskette file system,
high-speed mathematics unit, and analog subsystems are
also available.
The development cycle
of iSBC 80/30 based products
may be significantly reduced using an Intel Intellec
Microcomputer Development System. The resident
macroassembler, text editor, and system monitor greatly
simplify the design, development, and debug
of iSBC
80/30 system software. An optional diskette operating
system provides
-a relocating macroassembler, relocating
loader and linkage editor, and a library manager. A
unique In-Circuit Emulator (lCE-85) option provides the
capability
of developing and debugging software directly
on the iSBC 80/30.
Intel's high level programming language, PL/M, is also
available
as a resident Intellec Microcomputer Develop-
ment System option. PL/M provides the capability to pro-
gram
in a natural, algorithmic language and eliminates the
need to manage register usage
or allocate memory. PL/M
programs can be written in a much shorter time than
assembly language programs for a given application.
iSBC 80/30
1-4. EQUIPMENT SUPPLIED
The following are supplied with the iSBC 80/30 Single
Board Computer:
a. Schematic diagram,
d,wg no. 2002132
b. Assembly drawing, dwg no. 1001576
1-5. EQUIPMENT REQUIRED
Because the iSBC 80/30 is designed to satisfy a variety of
applications, the user must purchase and install only those
components required to satisfy his particular needs. A list
of components required to configure all the intended
applications
of the iSBC 80/30 is provided in table 2-1.
1-6. SPECIFICATIONS
Specifications of the iSBC 80/30 Single Board Computer
are listed
in table 1-1.
Table 1-1. Specifications
WORD SIZE
Instruction:
Data:
CYCLE TIME:
MEMORY CAPACITY
On-Board ROMIEPROM:
1-4
On-Board RAM:
Off-Board Expansion:
MEMORY ADDRESSING
On-Board ROM/EPROM:
On-Board RAM
(CPU Access):
On-Board
RAM
(Multibus Access):
8, 16, or 24 bits.
8 bits.
1.44
f.Lsec ±0.1% for fastest executable instruction; i.e., four clock cycles.
Up to 8K bytes; user installed in 1 K, 2K, or 4K increments.
16K bytes of dynamic RAM; integrity maintained during power failure with user-
furnished batteries.
Up to 65K bytes of user-specified.combinations of RAM, ROM, and EPROM.
0-07FF (using 2708 or 2758 EPROM's or 8308 ROM's);
O-OFFF (using 2716
EPROM's or 2316E ROM's); 0-1 FFF (using 2332 ROM's).
Jumpers allow on-board
CPU to· access either 8K or 16K. For 8K RAM access,
addresses may be set on 8K boundaries 2000, 4000,
... EOOO. For 16K
access, addresses may
be set on 16K boundaries 4000, 8000, or COOO. One
or both 8K segments may be reserved for CPU use only.
Jumpers allow board to act as slave for 8K or 16K RAM access by another
bus master; 16-bit or 20-bit addressing is accommodated and addresses are
irrespective
of addresses used for CPU access. For 16-bit addrljssing, boundaries
may
be set on any 8K or 16K segment of 65K byte address space. For 20-bit
addressing, boundaries may be set on any 8K or 16K segment of 1M byte
address space.

iSBC 80/30
SERIAL COMMUNICATIONS
Synchronous:
Asynchronous:
Sample Baud Rate:
INTERVAL TIMER AND BAUD RATE
GENERATOR
Input Frequency (selectable):
Output Frequencies:
SYSTEM CLOCK (808SA CPU):
General Information
Table 1-1. Specifications (Continued)
S-, 6-, 7-, or 8-bit characters.
Internal; 1 or 2 sync characters.
Automatic sync insertion.
5-, 6-, 7-, or 8-bit characters.
Break character generation.
1, 1 '12, or 2 stop bits.
False start bit detection.
Baud Rate
(Hz)2
Frequency'
(kHz, Software Selectable) Synchronous Asynchronous
+16 +64
153.6 -9600 2400
76.8 -4800 1200
38.4 38400 2400 600
19.2 19200 1200 300
9.6 9600 600 150
4.8 4800 300 75
2.4 2400 150 -
1.76 1760 110 -
Notes: 1. Frequency selected by 1/0 writes of appropriate 16-bitfrequency factor to
Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software-
programmable rates available. Any frequency from 18.75 Hz to 614.4 kHz
may
be generated utilizing on-board crystal oscillatorand 16-bit Program-
mable Interval Timer (used here as frequency divider).
2.46 MHz ±0.1%
(0.41 /-Lsec period nominal),
1.23 MHz ±0.1% (0.82 /-Lsec period nominal), and
153.6 kHz ±0.1% (6.5
/-Lsec period nominal).
Function Single Timer
Min. Max.
Real-Time
Interrupt 1.63/-Lsec 426 msec
Interval
Rate
Dual Timers
(Two Timers Cascaded)
Min. Max.
46528
3.26/-Lsec minutes
Generator 2.348 Hz 614.4 kHz 0.000036Hz 307.2 kHz
(Frequency)
2.7648 MHz ±0.1%.
1-5

General Information iSBC 80/30
Table 1-1. Specifications (Continued)
1-6
I/O ADDRESSING:
INTERFACE COMPATIBILITY
Serial I/O:
Parallel I/O:
Optional I/O:
INTERRUPTS:
COMPATIBLE CONNECTORS/CABLES:
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity:
PHYSICAL CHARACTERISTICS
Width:
Depth:
Thickness:
Weight:
All communication to Parallel I/Oand Serial I/O Ports,Timer, and InterruptController
is via read and write commands from on-board 8085A CPU. Refer to table 3-2.
EIA Standard RS232C signals provided and supported:
Carrier Detect Receive Data
Clear to Send Ring Indicator
Data Set Ready Secondary Receive Data
Data Terminal Ready SecondaryTransmit Data
Request to Send Transmit Clock
Receive Clock Transmit Data
24 programmable lines (8 lines per port); one port includes bidirectional bus driver.
IC sockets included for user installation of line drivers and/or I/O terminators as
required for interface ports. Refer to table 2-1.
IC socket included for Intel 8041/8741 Universal Peripheral Interface (UPI). Also
included are
IC sockets for user installation of line drivers and/or I/O terminators as
required for interface. Refer to table 2-1.
8085A CPU includes five interrupt inputs, each of which vectors processor to the
following unique memory locations for entry point to service routine:
Interrupt Vector Priority Type
Input Address
TRAP 24H Highest Non-maskable
RST 7.5 3CH t Maskable
RST 6.5 34H Maskable
RST 5.5 2CH Maskable
INTR Note Lowest Maskable
Note: INTR input provided by8259A PIC, which
is programmableto pro-
videvectorCALLaddressofservice routineforinterrupting device.
Jumpers allow selection of 12 priority interrupts from 18 interrupt sources. PIC may
be programmed to respond to edge-sensitive or level-sensitive inputs.
Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-29 and
2-30 for recommended types and lengths of I/O cables.
To 90% without condensation.
30.48 cm (12.00 inches).
17.15
cm (6.75 inches).
1.27 cm (0.50 inch).
425 gm (15 ounces).

iSBC 80/30 General Information
Table 1-1. Specifications (Continued)
POWER REQUIREMENTS:
CONFIGURATION
Vce = +5V±5%
VDD = +12V±5% VSS = -5V±5%
VAA = -12V±5%
Without EPROM' 3.5A 220 rnA -SOmA
With 8041/8741 UPI2
3.6A 220 rnA -SOmA
RAM Only3 350 rnA 20 rnA 2.5 rnA -
With iSSC 53Q4
3.5A 320 rnA -150 rnA
With 2K EPROM5 4.4A 350 rnA 95 rnA 40 rnA
(using 8708)
With 2K EPROM5 4.6A 220 rnA 50 rnA
(Using 8758) -
With 4K EPROM5
(4.6A ! (220 rnA
\,
(50 rnA)
(Using 2716) -
With 8K ROM5 4.6A 220 rnA 50 rnA
(Using 2332) -
Notes: 1. Does not include power for optional ROM/EPROM, 8041/8741 UPI, I/O drivers, and I/O terminators.
2. Does not include power required for optional ROM/EPROM, I/O drivers and I/O terminators.
3. RAM chips powered via auxiliary power bus.
4. Does notinclude powerfor optional ROM/EPROM, 8041/8741 UPI, I/O drivers, and I/O terminators. PowerforiSSC530
is supplied via serial port connector.
5. Includes powerrequired for two ROM/EPROM chips, 8041/8741 UPI, and I/O terminators installed for 341/0 lines; all
terminator inputs low.
1-7/1-8'

2-1. INTRODUCTION
This chapter provides instructions for preparing the iSBC
80/30 Single Board Computer for use in the user-defined
environment.
It is advisable that the contents of Chapters
1 and 3 be fully understood before beginning the con-
figuration and installation procedures provided
in this
chapter.
2-2. UNPACKING AND INSPECTION
Inspect the shipping carton immediately upon receipt for
evidence
of mishandling during transit. .If the shipping
carton
is severely damaged or waterstained, request that
the carrier's agent be presentwhen the carton
is opened. If
the carrier's agent is not present when the carton is opened
and the contents
of the carton are damaged, keep the
carton and packing material for the agent's inspection.
Forrepairs to a product damaged in shipment, contact the
Intel Technical Support Center (see paragraph 5-4)
to
obtain a Return Authorization Number and further in-
structions. A purchase order will be required to complete
the repair. A copy
of the purchase ordershould be submit-
ted to the carrier with your claim.
Itis suggested that salvageable shipping cartons and pack-
ing material be saved for future use in the event the
product must be reshipped.
2-3. INSTALLATION CONSIDERATIONS
The iSBC80/30 is designed for use in one of the following
configurations:
a. Standalone (single-board) system.
b. Bus master in a single bus master system.
c. Bus master in a multiple bus master system.
CHAPTER 2
PREPARATION FOR USE
Important criteria for installing and interfacing the
iSBC 80/30 in the above environments are presented in
following paragraphs.
2-4. USER-FURNISHED COMPONENTS
Because the iSBC 80/30 is designed to satisfy a variety of
applications, the userneed purchase and install only those
components required to satisfy his particular configura-
tion. A list
of components required to configure all the
intended applications
of the iSBC 80/30 are listed in table
2-1. Table 2-2 lists details, types, and vendors
of those
connectors referenced in table 2-1.
2-5. POWER REQUIREMENTS
The iSBC 80/30 requires +5V, -5V, + 12V, and -12V
power supply inputs. The currents required from these
supplies are listed in table 1-1. (The - 5V supply is
mandatory only if Intel 2708 EPROM chips are installed;
an on-board regulator that operates offthe
-12V supply.
can otherwise supply the -5V power.)
2-6. COOLING REQUIREMENT
The iSBC 80/30 dissipates 401 gram-calories/minute
(1.62 Btu/minute) and adequate circulation
of air must be
provided to prevent a temperature rise above 55°C
(131°F). The System 80 enclosures and the Intellec Sys-
tem include fans to provide adequate intake and exhaust of
ventilating air.
2-7. PHYSICAL DIMENSIONS
Physical dimensions of the iSBC 80/30 are as follows:
a. Width:
b. Height:
c. Thickness:
30.48 cm (12.00 inches).
17.15 cm (6.75 inches).
1.25 cm (0.50 inch).
2-1

Preparation for Use iSBC 80/30
Table 2-1. User-Furnished and Installed Components
Item Item Description Use
No.
1 iSBC 604 Modular Backplane and Cardcage. In- Provides power input pins and Multibus
cludes four slots with bus terminators. signal interface between iSBC 80/30 and
{See figure 5-3.} three additionalboards
in a multipleboard
system.
2 iSBC 614 Modular Backplane and Cardcage. In- Provides four-slot extension ofiSBC 604.
cludes four slots without bus terminators.
{See figure 5-4.}
3 Connector See Multibus connector details in Powerinputs
and Multibussignal interface
{mates with
P1}
table 2-2. Not required if iSBC 80/30
is installed in
in
an iSBC 604/q14.
4 Connector See Auxiliary connector details in Auxiliary backup battery inputs and asso-
{mates with
P2}
table 2-2. ciated memory protect functions.
5 Connector See parallel I/O connector details in Interfaces parallel I/O ports to Intel 8255A
{mates with J1} table 2-2. Programmable Peripheral Interface {PPI}.
6 Connector See parallel I/O connector details in Interfaces I/O ports to optional Intel 8041/
{mates with J2} table 2-2. 8741A Universal Peripheral Interface
{UPI}.
7 Connector See serial I/O connector details in Interfaces serial I/O port to
Intel. 8251A
{mates with J3} table 2-2. Programmable Communications Interface
{USART}.
8 ROM/EPROM Chips One
or two each of the following Intel On-board UVerasable PROM forprogram
ROM/EPROM chips: development and/or dedicated program
use. Compatible ROM chips can also
be
ROM EPROM BITS employed. Use either ROM or EPROM;
do not mix.
8308 2708 1K x 8
-2758 1K x 8
2316E 2716 2K x 8
2332 -4K x 8
9 Intel 8041/8741 A Universal Peripheral Interface {UPI}. Single chip microcomputer with program
memory, data memory, CPU, event
timer, I/O, and clock oscillator. Inter-
faces two 8-bit I/O ports; two additional
input bits {TO and T1} for conditional
branch and event timer functions.
10 Line Drivers Type Current Used for interface to Intel 8255A and
optional Intel 8041/8741. Requires two
SN74031,OC 16 rnA line driver IC's for each 8-bit parallel
SN7400 I 16 rnA output port. {Exception: refer to para-
SN7408 NI
16 rnA graph 2-11.}
SN7409 NI, OC 16 rnA
Types selected as typical; I = invert-
ing,
NI = noninverting, and OC = open
collector.
11
I/O Terminators Intel iSBC 901 Divider or iSBC 902 Used for interface
to Intel 8255A and
Pull-Up: optional Intel 8041/8741A. Requires two
~
901 's or two 902's for each 8-bit parallel
220 input port. {Exception: refer to paragraph
iSBC 901
2-11.} Additional 901 or 902 required for
330 8041/8741
if TO and T1 inputs are used
iSBC 902
l~~v
for conditional branch or event timer
0 0 functions.
12 Capacitors Seven capacitors as required. Rise time/noise capacitors for serial I/O
port.
2-2

iSBC 80/30 Preparation for
Use
Table 2-2. User-Furnished Connector Details
No. Of
Palrsl Centers Connector Intel
Function Pins (Inches) Type Vendor Vendor Part No. Part No.
3M 3415-0000 WITH EARS
Parallel 3M 3415-0001 WID EARS iSBC 956
I/O 25/50 0.1
Flat Crimp AMP 88083-1 Cable
Connector ANSLEY 609-5015 Set
SAE
S06750 SERIES
Parallel AMP 2-583485-6
I/O 25/50
0.1
Soldered VIKING 3VH25/1JV5 N/A
Connector TI H312125
Parallel TI H311125
I/O 25/50 0.1 Wirewrap1 VIKING 3VH25/1
JN05
N/A
COC3
VPB01B25000A1
Connector
ITICANNON
EC4A050A1A
Serial 3M 3462-0001 iSBC 955
I/O 13/26
0.1
Flat Crimp AMP 88106-1 Cable
ANSLEY 609-2615
Connector SAE
S06726 SERIES Set
Serial TI H312113
I/O 13/26 0.1
Soldered N/A
Connector AMP 1-583485-5
Serial
1/0
13/26
0.1 Wirewrap1
TI
H311113 N/A
Connector
COC3
VPB01E43000A1
Multibus 43/86 0.156 Soldered1 MICRO PLASTICS MP-0156-43-BW-4 N/A
Connector ARCO AE443WP1 LESS EARS
VIKING 2VH43/1AV5
Multibus
COC3
VFB01E43000A1 or
Connector 43/86 0.156 Wirewrapl.2
COC3
VPB01 E43AOOA 1 MOS 985
VIKING 2VH43/1AV5
AUXiliary 30/60
0.1
Soldered1 TI H312130 N/A
Connector VIKING 3VH30/1JN5
Auxiliary 30/60
0.1
Wirewrapl.2
COC3
VPB01 B30AOOA2
N/A
Connector
TI
H311130
NOTES:
1.
Connector heights are not guaranteed to conform to OEM packaging equipment.
2.
Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment.
3.
CDC VPB01 ..., VPB02 ..., VPB04 ..., etc. are identical connectors with different electroplating thicknesses or metal
surfaces.
2-8. COMPONENT INSTALLATION
Instructions for installing the optional ROM/EPROM,
Intel 8041/8741A Universal Peripheral Interface, line
drivers,
VO terminators, and rise time/noise capacitors
are given in following paragraphs. When installing the
optionalchips, besureto orientpin 1
of thechip adjacentto
thewhite dotlocatednearpin 1
of the associatedICsocket.
The grid location on figure 5
-1 (parts location diagram) .
and figure 5-2 (schematic diagram) are specified for each
user-installed component. Because the schematic dia-
gram consists of nine sheets, grid references to figure 5 ... 2
consist
of four alphanumeric characters. For example,
grid reference 6ZD4 signifies sheet 6 Zone D4.
2-9. ROM/EPROM cmps
Install the ROM/EPROM chips in IC sockets A25 and
A37. (Refer to figure 5
-1 zone ZC3 and figure 5-2 zone
3ZA3.) Sockets A25 and A37, respectively, accom-
modate the low order and high-order addresses of the
ROM/EPROM chip pair. For instance, if two Intel 2716
EPROM chips are installed, the chip installed in IC socket
A25 is assignedaddresses 0000-07FF; thechipinstalled in
IC socket A37 is assigned addresses 0800-0FFF.
2-3

Preparation for Use
The default (factory connected) jumpers are configured
for Intel 2316E ROM
or 2716 EPROM. If different type
chipsare installed, reconfigure thejumpers as described in
paragraph 2-14.
2-10. UNIVERSAL PERIPHERAL
INTERFACE
Install the optional Inte18041/8741A Universal Peripheral
Interface (UPI) chip in socket A20. (Refer to figure 5-1
zone ZC6 and figure 5-2. zone 5ZC4.)
2-11. LINE DRIVERS AND 110
TERMINATORS
Table2-3 liststheI/Oportsandthelocation of associatedIC
sockets for installing eitherline drivers
or I/O terminators.
(Refer
to table 2 -1 items 10 and 11.) Port E8 is factory
equipped with Intel 8226 Bidirectional Bus Drivers and
requires no additional components. (Refer
to paragraphs
2-22 and 2-23.)
2-12. RISE TIME/NOISE CAPACITORS
Eye pads are provided so that rise time/noise capacitors
may be installed
as required on the individual serial I/O
pins. Theselection
of capacitorvalues is attheoption of the
user and is normally a function
of the particular environ-
ment. The location
of these eye pads are as follows:
Capacitor Fig. 5-1
Fig. 5-2
C11 Z04 6Z04
C12
Z04 6Z83
C13
Z03 6ZC4
C14
Z04 6Z04
C16
Z03 6Z06
C17 Z03 6ZC6
C18 Z03 6Z06
iSBC 80/30
2-13. JUMPER CONFIGURATION
The iSBC 80/30 includes a variety of jumper-selectable
options to allow the user
to configure the board for his
parficular applicatio'n. Table 2-4 summarizes these
jumper-selectable options and lists
the- grid reference
locations
of the jumpers as shown in figure 5-1 (parts
location diagram) and figure 5-2 (schematic diagram).
Because the schematic consists
of nine sheets, grid
references
to figure 5-2 consists of four alphanumeric
characters. For example, grid reference 3ZB7 signifies
sheet 3 Zone B7.
Study table 2-5 carefully while making reference to
figures 5-1 and 5-2.
If the default (factory configured)
jumperwiring is appropriate for a particular function, no
further actions is required for thatfunction.
If, however, a
different configuration
is required, remove the default
jumper(s) and install
an optional jumpers(s) as specified.
For most options, the information in table 2-4 is suffi-
cient for proper configuration. Additional information,
where necessary for clarity,
is described in subsequent
paragraphs.
2-14. ROM/EPROM CONFIGURATION
Table 2-5 lists the jumper configurations and associated
address block for the various 'types
of compatible Intel
ROM/EPROM chips.
2-15. ON-BOARD RAM ADDRESSES
This on-board RAM can be accessed by the on-board
8085A microprocessor (CPU) as well as by other bus
masters in the system via the ~1ultibus. Addresses for on-
board 8085A access and for system access are assigned as
described in
paragraph~ 2-16 and 2-17, respectively.
Table 2-3. Line Driver and 1/0 Terminator Locations
1/0
Driver/ Fig. 5·1 Fig. 5·2
Port Bits Terminator Grid Grid
Ref. Ref
E8
0-7 None Required --
8255A
E9
0-3
A5 Z06
4ZA3
PPI 4-7
A6
Z06 4ZA3
Interface
EA
0-3
A4 Z07 4ZC3
4-7 A3
Z07 4Z83
8041/8741
1
0-3
A7 Z06 5Z03
UPI 4-7
A8
Z06 5ZC3
Interface 0-3
(Optional) 2
A10
Z05 5Z83
4-7 A11 Z05 5Z83
- TO, T1 A9 Z05
5ZC3
2-4

iSBC 80/30 Preparation for
Use
Table 2-4. Jumper Selectable Options
Function Fig.
5-1
Fig. 5-2 Description
Grid Ref. Grid Ref.
ROM/EPROM
Six jumpers accommodate one of four types of user-installed ROM or
Configuration EPROM chips.
One jumper required between two posts in each of
the following six groups of posts:
ZC3 3ZB7
112 thru 114)
ZC3 3ZC6 157 thru 159 Default jumpers accommodate Intel 2716 EPROM
ZC3 3ZB4 153 thru 156
ZD2 3ZA3 84 thru
88
or 2316E ROM chips. Refer to paragraph 2-14 if
ZD2 3ZA4
99 thru 101
reconfiguration is required.
ZD2 3ZA3 102 thru 105
On-Board RAM ZD2 3ZD7,3ZD6 One jumper wire selects
8K or 16K access and one jumper wire selects
(On-Board Access) base addressforon-board 8085A accessofon-board RAM. JumperW1
default position *A-B selects 16K access and default jumper *98-92
selects base address 4000H. Refer to paragraphs 2-15 and 2-16 if
reconfiguration is required.
On-Board RA M 16-Bit Address System: Three jumper wires select base address for
(System Access) system access:
ZB7 5ZC6 W5 (one): Must
be set to position *K-L.
ZB7 5ZB6 W4 (one):
8K or 16K access.
ZB7 5ZB5
171 thru 180 (one): Base address.
Refer
to paragraphs 2-17 and 2-18.
20-Bit Address System: Five jumper wires select base address for
system access:
ZB7 5ZC7 W6 (two): Upper or lower 512K space.
ZB7 5ZC6 W5 (one): 65K page select.
ZB7 5ZB6 W4 (one):
8K or 16K access.
ZB7 5ZB5
171 thru 180 (one): Base address.
Refer
to paragraphs 2-17 and 2-19.
Bus Clock ZB7 5ZA4 Default jumper *165-166 routes Bus Clock signal BCLKI
to the Multibus.
(Refer to table 2-13.) Remove this jumper only if another bus master
supplies this signal.
Constant Clock ZB7 5ZA4 Default jumper *167-168 routes Constant Clock signal CCLK/ to the
Multibus. (Refer to table 2-13.) Remove this jumperonly if another bus
master supplies this signal.
Bus Priority Out ZB7 8ZD2 Default jumper *169-170 routes Bus Priority Out signal BPRO/
to the
Multibus (Refer to table 2-13.) Remove this jumper only in those
systems employing a parallel priority bus resolution scheme. (Refer
to paragraph 2-27.)
Bus Priority One jumper defines one of two modes of resolving bus contention
in a
Resolution multiple bus master system:
ZB7 8ZD6 *162-163: Can request Multibus as needed.
163-164: Always requesting Multibus; .should only
be used when
iSBC 80/30 has lowest priority.
Auxiliary Backup ZB5 1ZC5,1ZB5 If auxiliary backup batteries are employed
to sustain memory during ac
Batteries power outages, remove default jumpers *W8, *W9, and *W10.
On-Board
-5V
ZB6 1ZB2 The 80/30 requires a
-5V supply for Intel 2708 EPROM chips and a
Regulator
-5V AUX input for the on-board RAM chips. The system -5V supply
is mandatory only if Intel 2708 EPROM chips are employed. If
Intel 2708 EPROM chips
are not employed and no system -5V
supply is available, the -5 AUX input to the on-board RAM chips can
be supplied by the on-board -5V regulator or by an auxiliary backup
battery.
(The on-board -5V regulator operates from the system
-12V supply.) If neither a system -5V supply nor an auxiliary backup
battery is used, enable the -5V regulator by connecting jumper*W10.
2-5

Preparation for Use
iSBC 80/30
Table 2-4. Jumper Selectable Options (Continued)
Function Fig.
5-1 Fig. 5-2 Description
Grid Ref. Grid Ref.
FailsafeTimer ZC8 1ZC6 If the on-board 8085A
CPU addresses either a system or an on-board
memory
or I/O device and that device does not return an acknow-
ledge signal, the 8085A will hang up in a wait state. A failsafe timer
is triggered during
T1 of every machine cycle and, if not retriggered
within 1
0 milli~econds, the resultant time-out pulse can be used to
allow the 8085A to exit the wait state. If this feature is desired, connect
jumper 115-116.
RAM Refresh The 8202 Memory Controller for on-board RAM
is jumper selectable as
follows to select the automatic or invisible refresh mode:
ZC4 2ZA3 *110-111: Automatic refresh (normal) mode.
110-106: Invisible refresh (on request) mode.
In the automatic refresh mode, a wait state can be imposed on the
on-board 8085A if a memory access occurs while a memory refresh
cycle is
in progress. In this case, the 8085A is forced to wait until
the refresh cycle
is complete. In the invisible refresh mode, the 8202
works around memory accesses by refreshing memory during the
instruction decode clock cycle which follows each instruction fetch.
Timer Input Input frequencies
to the 8253 Programmable Interval Timer counters
Frequency are jumper selectable
as follows:
Counter 0 (8041/8741 Event Clock)
*47-52: Same
as Counter 2.
ZD5 7ZB3 47-51: 153.6 kHz.
47-48: External Event Clock (from Port EA).
Counter 1 (Count Out)
*46-54: 1.2288 MHz.
ZD5 7ZA4 46-52: Same
as Counter 2.
46-50: Counter 0 output.
46-48: External Event Clock (from Port EA).
Jumper 46-50 effectively connects Counter 0 and 1
in series in which
the output of Counter 0 serves
as the input clock to Counter 1.
This permits lower clock rates to Counter 1 and, in turn, Counter 1
provides longer time intervals.
Counter 2 (8251A Baud Rate Clock)
ZD5 7ZB5 *53-54: 1.2288 MHz.
53-49: 2.4576 MHz.
Event Clock The Event Clock is a jumper option for Port C (Port
EA) of the 8255A
PPI. The Event Clock may be provided by the following optional
sources:
48-50: Same
as PIT Counter 0 (8041/8741 Event Clock).
ZD5 7ZB4 48-51: 153.6 kHz.
48-52: Same
as PIT Counter 2 clock.
Priority Interrupt A jumper matrix provides a wide selection of interrupts to
be interfaced
to the on-board 8085A and ,the Multibus. The matrix includes the
following jumpers (refer to paragraph 2-20):
ZC6 117 thru 134
ZC6 Sheet 7 136 thru 152
ZB6
181 thru 190
8251A Serial I/O -Sheet 6 Jumpers are used
to input the serial I/O port transmit clock, receive
Port Configuration clock, ring indicator, carrier detect, etc.,
from several sources. Refer
to paragraph 2-21.
8255A Parallel I/O -Sheet 4 Jumpers are used
to configure Ports E8, E9, and EA for the desired
Port Configuration operating mode. Refer
to. paragraph 2-22.
8041·/8741 A Universal -Sheet 5 Jumpers
are used to selectvarious input and/oroutputsignals depending
Peripheral.
Interface on the application. Refer
to paragraph 2-23.
*Default jumper connected at the factory.
2-6

iSBC 80/30
Table 2-5. ROM/EPROM Configuration Jumpers
ROM/EPROM Jumpers Address
Type Block
2708 112-113,158-159, 0000-07FF
EPROM 100-101,104-105,
or 155-154, 86-84
8308
ROM
2758 112-113,158-159, 0000-07FF
EPROM 100-101,104-103,
155-154,86-87
*2716 112-113, 157-158,
OOOO-OFFF
EPROM 100-101,104-103,
or
155-156,86-85
*2316E
ROM
2332 112-114,157-158, 0000-1 FFF
ROM 100-99,104-102,
155-153,86-85
*Default jumpers are connected for type 2716 EPROM or
2316E ROM. Disconnect and reconfigure jumpers as
necessary if installing different type ROM/EPROM.
2-16. ON-BOARD808SAACCESS. JumperWl posi-
tion B-C allows the on-board SOS5A to access SK of the
16K RAM; jumper
WI default position A-B allows
access to all 16K. For
SK access, the RAM address block
may be configured on
SK boundaries 2000, 4000, ...
EOOO; for 16K access, the RAM address block may be
configured on 16K boundaries 4000,
SOOO, or COOO.
(Address boundary 0000 is reserved for ROM/EPROM.)
Default jumper 9S -92 selects boundary 4000 for both SK
and 16K access. If only SK access is desired remove
jumper
WI from position A-B and install it id position
B-C. If a different address boundary is desired, recon-
figure the jumpers as listed in table 2-6.
2-17. SYSTEM ACCESS. The on-board RAM can be
shared by other bus masters in the system via the
Multibus.
If one or more bus masters have a 20-bit
address capability, the extended addressing jumpers
allow the onboard RAM
to reside anywhere within a
I-megabyte address space. (The on-board
SOS5A can only
access memory in the
lo~er 65K address space.) If it is
not desired to have the on-board RAM s4ared by the
system, leave default jumper IS0-179 installed. Other-
wise~ configure the jumpers for 16-bit addressing or
20-bIt addressing as described in following paragraphs.
NOTE
Addresses for system access of on-board RAM
are completely independent of addresses for on-
board SOS5A access of on-board RAM.
Preparation for Use
Table 2-6. Jumper Configuration for On-Board
808SA Access of On-Board RAM
Jumper RAM Address Block1
8KAccess
2 16K Access3
98-91 2000-3FFF
*98-92 4000-5FFF 4000-7FFF
98-93 6000-7FFF
98-94 8000-9FFF 8000-BFFF
98-95
AOOO-BFFF
98-96
COOO-DFFF
COOO-FFFF
98-97
EOOO-FFFF
NOTES:
1.
Address block 0000-1 FFF is reserved for
ROM/EPROM.
2.
Requires jumper W1 position B-C installed.
3. Requires jumper W1 position *A-B installed.
*Default jumper; disconnect if reconfiguration
is required.
2-18. 16-BITADDRESS SYSTEMS. For system access,
the
~n-board RAM is divided into eight 65K pages. In
1?~bIt add~ess systems, there is no page selection capa-
bIlIty and Jumper W5 default position K-L restricts the
addresses
to Page 0 (the only page in a 16-bit system).
(Refer
to table 2-7.)
As shown in table 2-S, the system can access either SK or
16K ~f t~e on-board RAM. Jumper W4 default posi~ion
B-A lImIts the system to SK access; jumperW4 position
B-C allows
acce!tS of all 16K of on-board RAM.
One jumper wire places the on-board RAM in the desired
SK or 16K segment of the selected 65K page. To access
SK, forexample, the SK segmentcan be placed on any SI<
boundary 0000 (1st SK), 2000 (2nd SK), 4000 (3rd
SK),
... EOOO (Sth SK). To access 16K, the 16K
segment can be placed on any 16K boundary 0000 (1st
16K), 4000 (2nd 16K),
SOOO (3rd 16K), or COOOO (4th
16K). Figure
2-1 illustrates a step-by-step sequence for
establishing RAM addresses for 16-bit address systems.
2-19. 20-BIT ADDRESS SYSTEMS. In 20-bit address
systems, the on-board RAM can reside anywhere within a
I-megabyte address space.
As shown in table 2-7 the
RAM
is first placed in the lower or upper 524K by ju~per
W6. JumperW5 then selects one of eight65K pages within
the upper or lower 524K bytes.
Next, referring to table 2-S, the system can access either
SK or 16K of the on-board RAM. Default jumper W4
position B-A limits the system
to SK access; jumper W4
position B-G allows access
of all 16K of on-board RAM.
2-7