Interphase 4538 Quick user guide
4538 PMC® T1/E1/J1
Communications Controller
Hardware Reference Manual
Document No. UG4538-001$
Print Date: 2FWREHU
Copyright Notice
©2001 by Interphase Corporation. All rights reserved.
Printed in the United States of America, 2001.
This manual is licensed by Interphase to the user for internal use only and is protected by copyright. The user is
authorized to download and print a copy of this manual if the user has purchased one or more of the Interphase products
described herein. All copies of this manual shall include the copyright notice contained herein. No part of this manual,
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Interphase Corporation
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no liability resulting from omissions, or from the use of information obtained from this manual. Interphase Corporation
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4538 Hardware Reference Manual i
Contents
List of FiguresY
List of TablesYLL
List of ExamplesL[
Using This Guide[L
Purpose[L
Audience[L
Byte Ordering and Bit Coding Convention[LL
Type Definition[LL
Code Examples[LL
Icon Conventions[LL
Text Conventions [LLL
Checking and Downloading from the
Interphase WWW/FTP Site[LY
WWW Method[LY
FTP Method[LY
CHAPTER 1 Hardware Description
Overview
4538 Hardware Structure
The PowerQUICC II
PowerQUICC II Resets
System Clocks
PCI Local Space Mapping
Interrupts
Memory Controllers
Communication Processor Module (CPM) I/O Ports
CPM TDM Busses
Bank of Clocks
Baud Rate Generator
Ethernet 10/100BaseT
TTY Console Serial Port
User-Programmable LEDs
The PCI Bridge
PowerSpan PCI Configuration Registers
PowerSpan PCI Registers
PowerSpan Processor Bus Registers
PowerSpan DMA Registers
PowerSpan Miscellaneous Registers
Contents
ii Interphase Corporation
PowerSpan I²O Registers
Interrupt Pins and Doorbell Usage
PCI to Local Interrupt (ATN)
Local to PCI Interrupt (–INTA)
Hardware and Software Resets Through the PowerSpan
Local Space Access From PCI Memory Space
Access to the FLASH EEPROM Through CompactPCI
PCI Memory Space and I/O Space Access From the PowerQUICC II
In-situ EPLDs Programming
Serial EEPROM Connected to the PowerSpan
Board Equipment Register
Vital Product Data (VPD)
Interphase-Specific Production Data and Boot Monitor Parameters
The FLASH EEPROM Boot Memory
The QuadFALC T1/E1/J1 Framer
The Ethernet Transceiver
TDM Bus Configurations
General
Multiplex Direct Mode
Independent Direct Mode
Switched Mode
Pass-Through Mode
CHAPTER 2 4538 Power-Up Initialization
Overview
PowerSpan Initialization
PowerSpan Hardware Configuration Word
PowerSpan Register Initialization Through the I²C Serial EEPROM
Other PowerSpan Initializations
PowerQUICC II Hardware Configuration Word
PowerQUICC II Initializations
PowerQUICC II System Interface Unit (SIU) Initialization
Internal Memory Map Register (IMMR)
Bus Configuration Register (BCR)
System Protection Control Register (SYPCR)
60x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL)
SIU Module Configuration Register (SIUMCR)
Bus Transfer Error Registers (TESCR1 and L_TESCR1)
Memory Controllers
SDRAM Controller and SDRAM Device Initialization
GPCM Controller Initialization
UPM Controller Programming
MPC603e Core Initialization
MMU Initialization
Cache Initialization
Communication Processor Module Initialization
I/O Port Initialization
Contents
4538 Hardware Reference Manual iii
CPM RCCR Reset
CHAPTER 3 Programming the Peripherals
Overview
PowerQUICC II CPM Initialization
Serial Interfaces and Time Slot Assigner Initialization
TDM Busses in Multiplexed Direct Mode and in Switched Mode
TDM Busses in Independent Direct Mode
TDM Busses in Pass-Through Mode
Clocks and Baud-Rate Generators
Introduction
BRGCLK
BRG7 –TTY Baud-Rate Generator
MCC Initialization
T1/E1/J1 Framer Initialization
Introduction
Master Clock Initialization
TDM Busses General Structure
Multiplexed Direct Mode
Independent Direct Mode
Switched Mode
Pass-Through Mode
Framing and Line Coding Initialization
Common Initialization
T1 Specific Initialization
E1/E1-CRC4 Common Initialization
E1 Non-CRC4 Specific Initialization
E1-CRC4 Specific Initialization
Clock Synchronization Initialization
Transmit Pulse Shape
Line LED Control
The Ethernet Port Initialization
The TTY Framer Initialization
CHAPTER 4 Accessing the 4538 on the PCI Side
PowerSpan Configuration by the PCI Host
PCI Configuration
Interrupt Pin Configuration
PCI-to-Local Window Configuration
Controlling the 4538 Hardware and Software Resets
Controlling the PCI-to-Local Interrupt
Local to PCI Interrupt (–INTA)
Local Space Access From PCI Memory Space
Access to the FLASH EEPROM Through PCI
FLASH EEPROM Programming Algorithms
Serial EEPROM Connected to the PowerSpan
Contents
iv Interphase Corporation
In Situ EPLD Programming
Optimizing the PCI Bus Utilization
Effective Ordering of the PCI Accesses
PCI Deadlock Situations
CHAPTER 5 Connectors and Front Panel
Connector Placement
Front Panel
LED Descriptions
RJ48 Connectors J1 and J2
Ethernet 10/100 RJ45 Connector J3
TTY Serial Port J4
PMC Connectors
PMC Connectors P1 and P2
PMC Connector P4
Debug Port J5
ISP Enable Jumper JP1
Blank Card Jumper JP2
Connector Summary
Carrier Card Specification
CompactPCI Carrier Card
Custom Carrier Card
6435 Rear Transition Module
APPENDIX A Mechanical Information
PMC Card Dimensions
Carrier Card Dimension Requirements
Bibliography
Industry Standards
Telecommunication Standards
Manufacturers’Documents
Glossary
Index
4538 Hardware Reference Manual v
List of Figures
Figure 1-1. 4538 Structure....................................................................................................................................2
Figure 1-2. Local Space Mapping.........................................................................................................................6
Figure 1-3. Board CPU_LEDs............................................................................................................................13
Figure 1-4. Local Space Access From PCI Memory Space ...............................................................................23
Figure 1-5. PCI I/O or Memory Space Access from Local Space......................................................................26
Figure 1-6. TDM Busses General Structure .......................................................................................................35
Figure 1-7. General Clock Structure (Framer 1 & 2) .........................................................................................36
Figure 1-8. General Clock Structure (Framer 3 & 4) .........................................................................................37
Figure 1-9. TDM Busses in Multiplex Direct Mode ..........................................................................................39
Figure 1-10. Clocks in Multiplex Direct Mode (Framer 1 & 2)...........................................................................40
Figure 1-11. Clocks in Multiplex Direct Mode (Framer 3 & 4)...........................................................................41
Figure 1-12. TDM Busses in Independent Direct Mode ......................................................................................45
Figure 1-13. Clocks in Independent Direct Mode (Framer 1 & 2).......................................................................46
Figure 1-14. Clocks in Independent Direct Mode (Framer 3 & 4).......................................................................47
Figure 1-15. TDM Busses in Switched Mode ......................................................................................................49
Figure 1-16. Clocks in Switched Mode (Framer 1 & 2).......................................................................................50
Figure 1-17. Clocks in Switched Mode (Framer 3 & 4).......................................................................................51
Figure 1-18. TDM Busses in Pass-Through Mode (1->2 & 3->4 Example)........................................................54
Figure 1-19. TDM Busses in Pass-Through Mode (2->1 & 4->3 Example)........................................................55
Figure 1-20. Clocks in Pass-Through Mode (Framer 1 & 2)................................................................................56
Figure 1-21. Clocks in Pass-Through Mode (Framer 3 & 4)................................................................................57
Figure 3-1. Mapping of Four 2 MHz Streams into an 8 MHz Stream................................................................76
Figure 5-1. Connectors on the Component Side.................................................................................................95
Figure 5-2. Connectors and LEDs on the Solder Side........................................................................................95
Figure 5-3. Connectors and Leds on front panel ...............................................................................................96
Figure 5-4. TTY connector : 2.5mm stereo jack plug ........................................................................................98
Figure 5-5. 4538 Connectors ............................................................................................................................107
Figure 5-6. 8-Port 6435 Rear Transition Module Layout.................................................................................110
List of Figures
vi Interphase Corporation
4538 Hardware Reference Manual vii
List of Tables
Table 1-1. PCI Local Space Mapping ........................................................................................................................5
Table 1-2. Local Interrupts ........................................................................................................................................7
Table 1-3. PowerQUICC II Memory Controller Machine Usage .............................................................................7
Table 1-4. CPM Port A Usage ...................................................................................................................................8
Table 1-5. CPM Port B Usage ...................................................................................................................................8
Table 1-6. CPM Port C Usage ...................................................................................................................................9
Table 1-7. CPM Port D Usage ...................................................................................................................................9
Table 1-8. CPM SI1 TDM Busses Wiring ...............................................................................................................10
Table 1-9. CPM SI2 TDM Busses Wiring ...............................................................................................................10
Table 1-10. CPM Bank of Clocks Usage ...................................................................................................................11
Table 1-11. CPM Baud Rate Usage ...........................................................................................................................11
Table 1-12. Ethernet Signals on the CPM .................................................................................................................11
Table 1-13. Asynchronous Console Serial Port Wiring ............................................................................................12
Table 1-14. User-Programmable LED Control Ports ................................................................................................13
Table 1-15. PCI Configuration Registers ..................................................................................................................14
Table 1-16. PowerSpan PCI Registers .......................................................................................................................15
Table 1-17. PowerSpan Processor Bus Registers ......................................................................................................16
Table 1-18. PowerSpan DMA Registers ...................................................................................................................17
Table 1-19. PowerSpan Miscellaneous Registers ......................................................................................................18
Table 1-20. PowerSpan I²O Registers .......................................................................................................................19
Table 1-21. PowerSpan Interrupt Pin Usage .............................................................................................................20
Table 1-22. Serial EEPROM Mapping ......................................................................................................................27
Table 1-23. Board Equipment Register Layout .........................................................................................................27
Table 1-24. Hardware Configuration Register Field Descriptions ............................................................................28
Table 1-25. FLASH EEPROM Mapping ...................................................................................................................29
Table 1-26. GCM Register Programming (MCLK=12.500 MHz) ............................................................................31
Table 1-27. Transmit Pulse Shape Programming ......................................................................................................31
Table 1-28. QuadFALC Multifunction Port Usage ...................................................................................................32
Table 1-29. Ethernet LEDs ........................................................................................................................................33
Table 1-30. TDM and Synchronization Signals in Multiplex Direct Mode ..............................................................38
Table 1-31. TDM and Synchronization Signals in Independent Direct Mode ..........................................................42
Table 1-32. TDM and Synchronization Signals in Switched Mode ..........................................................................48
Table 1-33. TDM and Synchronization Signals in Pass Through Mode ...................................................................52
Table 2-1. PowerSpan Register Initialization Values in the Serial EEPROM ........................................................60
Table 2-2. PowerQUICC II Memory Controller Machine Usage ...........................................................................65
Table 2-3. CPM Port Register initialization Values ................................................................................................67
Table 3-1. GCM Register Programming .................................................................................................................75
Table 3-2. Channel Phase Programming in Multiplexed System Data Streams .....................................................77
Table 3-3. QuadFALC RCLK Reference Source for DCO-R .................................................................................77
Table 3-4. Common T1/E1/E1-CRC4 Initialization ...............................................................................................82
Table 3-5. T1 Specific Initialization ........................................................................................................................82
Table 3-6. E1/E1-CRC4 Common Initialization .....................................................................................................82
Table 3-7. E1 Non-CRC4 Specific Initialization .....................................................................................................83
Table 3-8. E1-CRC4 Specific Initialization. ............................................................................................................83
Table 3-9. Slave Mode Initialization .......................................................................................................................83
Table 3-10. Master Mode Initialization .....................................................................................................................83
Table 5-1. RJ48 Connectors J1 and J2 .....................................................................................................................97
Table 5-2. Ethernet 10/100 RJ45 Connector ...........................................................................................................97
List of Tables
viii Interphase Corporation
Table 5-3. J4 TTY Serial Connector ....................................................................................................................... 98
Table 5-4. PMC Connector P1 ................................................................................................................................98
Table 5-5. PMC Connector P2 .............................................................................................................................. 100
Table 5-6. PMC Connector P4 .............................................................................................................................. 103
Table 5-7. J5 Debug Port ...................................................................................................................................... 106
Table 5-8. CompactPCI J3 Pin-Out ...................................................................................................................... 107
Table 5-9. CompactPCI J5 Pin-Out ...................................................................................................................... 108
Table 5-10. T1/E1/J1 RJ48 Connector .................................................................................................................... 111
4538 Hardware Reference Manual ix
List of Examples
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List of Examples
xInterphase Corporation
4538 Hardware Reference Manual xi
Using This Guide
Purpose
This 4538 Hardware Reference Manual is designed for software developers in Interphase
customer organizations who intend to develop embedded software and/or host drivers for
the 4538 T1/E1/J1 communications controller.
The 4538 is delivered with an Interphase Boot Firmware located in the FLASH memory.
This firmware initializes and configures the 4538 hardware at each boot. It also includes
built-in self testsanda monitor. Software developerscan decide to keep the Interphase Boot
Firmware and develop an operational firmware that will start after the completion of this
Interphase Boot Firmware. This solution is recommended for the following reasons:
• PowerQUICCII and 4538 initialhardwareconfiguration codeis already developed
and validated by Interphase in the boot firmware.
• Interphase Boot Firmware provides several ways to download and execute
developer’s operational firmware.
• Interphase Boot Firmware can be used during the life of the product for operational
firmware updates and field unit tests.
However, if the software developers decide to re-develop their own Boot Firmware, this
manual describes in detail the 4538 Hardware and provides information relative to its
initialization and configuration.
NOTES
To install the 4538 Communications Controller in your CompactPCI Machine, please
refer to the 4538 Board Installation and Maintenance Guide. Different cautions and
warnings are described to avoid damage to your communications controller.
All the booting process and software elements composing the Interphase Boot
Firmware are described in the 4538 Built-In Self test and Monitor Users Guide. Refer
to this document when using Boot Firmware.
Audience
This guide was written assuming that readers have extensive knowledge of the C
programming language and of methods for developing and installing software drivers.
Byte Ordering and Bit Coding Convention
xii Interphase Corporation
Byte Ordering and Bit Coding Convention
The PCI bus uses the Little Endian Byte ordering: byte 0 in a 32-bit word is the Least
Significant Byte (LSB) from an arithmeticpoint of view and is noted D(7:0).The PowerPC
architecture uses the Big Endian Byte ordering: byte 0 in a 32-bit word is the Most
Significant Byte (MSB) from an arithmetic point of view and is noted D(31:24).
The PowerPC architecture uses the very unusual Little Endian Bit convention, where bit 0
is on the left and is the most significant bit. Unless otherwise noted, this document does not
use this convention. Instead, it uses the classical bit coding convention, where bit 0 (on the
right) is the least significant bit and bit i is the 2iweight bit. This is the Big Endian Bit
convention. This coding convention applies to data, addresses, and bit fields. In the
following figure, MSB means Most Significant Byte and LSB Least Significant Byte:
The standard C convention is used to identify the numeric format of arithmetical values:
•No prefix for decimal values
•0x prefix for a hexadecimal value
For example 0x12 = 18.
Type Definition
Only a few basic types are used:
•byte: unsigned, coded as 8 bits
•word: unsigned, coded as two contiguous bytes, most significant first
•dword: unsigned, coded as two contiguous words, most significant first
Code Examples
This document provides several algorithm descriptions presented in PowerPC assembly
language and in C language.
Icon Conventions
Icons draw your attention to especially important information:
NOTE
The Note icon indicates important points of interest related to the current subject.
0 % / %
4538 Hardware Reference Manual xiii
CAUTION
The Caution icon brings to your attention those items or steps that, if not properly
followed, could cause problems in your machine’s configuration or operating
system.
WARNING
The Warning icon alerts you to steps or procedures that could be hazardous to your
health, cause permanent damage to the equipment, or impose unpredictable results
on the surrounding environment.
Text Conventions
The following conventions are used in this manual. Computer-generated text is shown in
typewriter font. Examples of computer-generated text are: program output (such as the
screendisplayduring the software installationprocedure), commands,directory names, file
names, variables, prompts, and sections of program code.
Computer-generated text example
Commands to be entered by the user are printed in bold Courier type. For example:
cd /usr/tmp
Pressing the return key (¤Return) at the end of the command line entry is assumed,
when not explicitly shown. For example:
/bin/su
is the same as:
/bin/su ¤Return
Required user input, when mixed with program output, is printed in bold Courier type.
References to UNIX programs and manual page entries follow the standard UNIX
conventions.
When a user command, system prompt, or system response is too long tofit on a single line,
it will be shown as
Do you want the new kernel moved into
\vmunix?[y]
with a backslash at either the beginning of the continued line or at the end of the previous
line.
Checking and Downloading from the Interphase WWW/FTP Site
xiv Interphase Corporation
Checking and Downloading from the
Interphase WWW/FTP Site
The latest production software drivers, firmware, and documentation (in Adobe Acrobat
PDF or text format) for our current products are available on our WWW / FTP site.
Interphase recommends our customers visit the web site often to verify that they have the
latest version of driver, firmware, or documentation.
WWW Method
1. Access the following web page:
http://www.iphase.com
2. Move the mouse (or other pointer) and click on the Products option. A menu will
appear on the left side with Telecom and Server I/O options. Choose the
appropriate menu item.
3. A new web page with a list of the currently offered products will appear. Choose
the correct communications controller for your system bus and configuration needs
by clicking on the product number (i.e. 4531S, 6535, 4575, etc.).
4. The Product Description page appears for that product number. At the left side of
the page is a list showing further information web pages for that product. Choose
the SW Downloads item.
5. A new web page appears with a list of the latest released drivers available for that
adapter based on the operating system. Click on the line that describes your driver
requirement. Depending on your browser configuration, the driver will now
download to your system. If this doesn’t work correctly, try to ‘right-click’on the
proper driver and choose an option that will save the file to your local file system.
FTP Method
1. From your command line, enter following:
ftp://ftp.iphase.com
2. At the Login: prompt, enter anonymous
3. At the Password: prompt, enter your E-mail address.
4. At the ftp prompt, enter binary
5. Enter cd pub
6. To list all the available product technology directories, enter dir. The 00README.txt
file in each directory gives a description of the files and subdirectories in that
directory.
7. To access the directory for the technology that you require, enter cd followed by
the appropriate directory name. Most technology directories also have bus and
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