ITE IT6506 Operating instructions

IT6506 Programming Guide
Ver 1.02
Tseng Jau-Chih
ITE Tech. INC.
Last Update Date: 2013/11/12

History

-i
Index
Chap 1 Introduce .......................................................................................................... 1
Chap 2 IT6506 Initial..................................................................................................... 4
Initial Register Setting ...................................................................................................................4
Chap 3 Event of IT6506 ................................................................................................ 6
Chap 4 Link Configuration ............................................................................................ 8
Hot Plug ........................................................................................................................................8
System status................................................................................................................................8
IT6506 Capacity Configuring.........................................................................................................8
Detecting a Tx...............................................................................................................................8
Training .........................................................................................................................................8
Train Fail .......................................................................................................................................8
Chap 5 Video Programming.......................................................................................... 9
Video Input Readback...................................................................................................................9
Video Output Programming.........................................................................................................10
Output RGB444 video ............................................................................................................. 11
Output YCbCr444 video .......................................................................................................... 11
Output YCbCr422 video sync seperated................................................................................. 11
Output YCbCr422 video sync embedded................................................................................12
Output YCbCr422 video sync embedded CCIR656 ................................................................12
Color Converting .....................................................................................................................13
Enable Video Output ................................................................................................................... 14
Chap 6 Audio Programming........................................................................................ 15
Audio Input Information............................................................................................................... 15
Configure Audio Output............................................................................................................... 16
Audio Error..................................................................................................................................16
Chap 9 Registers ........................................................................................................ 19
Bank 0 : reg05[3] = ‘0’, reg05[0] = ‘0’ ..........................................................................................19
Bank 1 : Reg05[3][0] = ‘0’ ‘1’ .......................................................................................................31
Bank 2 : (reg5[3] = ‘1’, reg5[0] = ‘0’)............................................................................................ 37

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -1- 2013/11/12
Chap 1 Introduce
The IT6506 is a high-performance DisplayPort 1.1a receiver, fully compliant with DisplayPort
1.1a,
HDCP 1.3 specifications. The IT6506 with its Deep Color capability (up to 36-bit) ensures
robust reception of high-quality uncompressed video content, along with state-of-the-art
uncompressed and compressed digital audio content.
Aside from the various video output formats supported, the IT6506 also receives and provides
up to 8 channels of I
2
S digital audio outputs, with sampling rate up to 192kHz and sample size
up to 24 bits, facilitating direct connection to industry-standard low-cost audio DACs. Also, an
S/PDIF output is provided to support up to compressed audio of 192kHz frame rate.
Each IT6506 comes preprogrammed with an unique HDCP key, in compliance with the HDCP
1.3 standard so as to provide secure transmission of high-definition content. Users of the
IT6506 need not purchase any HDCP keys or ROMs.
Features
•Compliance with DisplayPort Specification V1.1a at 1.62/2.7 Gbps data rate (Low bit
rate/High bit rate)
•Support flexible 1/2/4 lanes configurations; Full 10.8Gbps data rate support(4 lanes at
2.7Gbps)
•Support DPCD Rev.1.1
•Support HDCP 1.3 with HDCP key embedded
•Support Spread Spectrum Clocking up to 0.5% down-spread to reduce EMI
•Support Source Connection Detection through AUX channel DC levels
•Support up to WQXGA(2560X1600) VESA display format
•Support Digital Video Output in 18/24/30/36(deep color) bits format with separate
Sync control
•Support Pixel component format with RGB; YCbCr 422; YCbCr 444
•Support Bit depth per color with 6/8/10/12 bits
•Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces
with programmable coefficients.
•Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2
•Dithering for conversion from 12-bit component to 10-bit/8-bit
•S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio up to 192kHz frame
rate
•Support 8-channel, uncompressed LPCM I2S audio with sample rates of 32~192 kHz
and sample sizes of 16~24 bits
•Automatic Audio Error detection with soft mute function, preventing annoying harsh
output sound due to audio error or hot-unplug

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -2- 2013/11/12
•Automatic loss of signal detection for Link management
•Intelligent, programmable power management
•144-pin LQFP (20mm x 20mm) package
Pin Diagram
17
18
19
20
21
22
23
24
25
37383940414243444546474849505152535455565758596061
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
26
27
28
29
30
31
32
33
34
35
6263646566676869707172
IT6506
Displayport RX Chip
LQFP-144
(Top View)
I2S2
I2S0
DCAUXN DCAUXP RX3N RX3P RX2N RX2P AVCC AGND RX1N RX1P AVCC RX0N RX0P DVDD18 PGND PVCC ASPGND ASPVCC RXAUXP RXAUXN XTALIN XTALOUT INT# PCADR
I2S3
ENTEST PGND PVCC
I2S1
WS
SCLK
EMEM_VPP
PCSCL PCSDA
QB2
QB3
QB6
QB7
QB8
QB9
QB5
QB4
IVSS
HPD
IVDD
IVDD
MCLK
SPDIF
OVDD
OVSS
OVDD
OVSS
QA20
QA21
QA26
QA27
QA28
IVDD
IVSS
QA30
QA31
OVDD
OVSS
QA22
QA23
QA24
QA25
QA32
QA35
DVSS18 DVDD18 AGND AVCC DVSS18
QA33
QA34
36
QA29
SYSRSTN
11
12
13
14
97
98
OVSS
QB10
QB11 QA16
QA17
QA18
QA19
95
OVDD
96
OVDD QB21 QB20
1
2
3
4
5
6
7
8
9
144143142141140139138137136135134133132131130129128127126125124123122121120
101
102
103
104
105
106
107
108
119118117116115114113112111110109
QB14
QB15
QB16
QB17
QB18
QB19
DDCSDA
DDCSCL
IVDD
IVSS
VSYNC HSYNC IVDD PCLK IVSS DE QA0 QA1 QA4 QA5 OVDD OVSS QA2 QA3 QB35 OVSS QB26 QB27 IVDD IVSS QB28 QB29 QB30 QB31 QB32 QB33 QB34 OVSS QB23 OVDD QB22
QA8
QA9
QA10
QA11
QA12
QA13
QA14
QA15
IVDD
IVSS
99
100
QA6 QA7
10
15
16
IT6506 provides internal register accessed via PCSCL (pin 71) and PCSDA (pin 70) with slave
address 0xB0 where PCADR (pin68) is low, or 0xB2 where PCADR (pin68) is high under
100KHz speed.
The terms listed in the below table are using in future chapters:
Term Description Example
RegXX Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in ban 0.
Reg05 – access with I
2
C slave
address 0xB0/0xB2,
sub-address 0x05.

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -3- 2013/11/12
Reg1XX
Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in ban 1.
Reg1C0 – access with I
2
C
slave address 0xB0/0xB2,
sub-address 0xC0.
Reg2XX Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in ban 2.
The register 0x00~0x0F are common for all banks, and the bank switching using as following:
bank 0 – reg05[3][0] = ‘0’ ‘0’
bank 1 – reg05[3][0] = ‘0’ ‘1’
bank 2 – reg05[3][0] = ‘1’ ‘0’

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -4- 2013/11/12
Chap 2 IT6506 Initial
IT6506 initial can be separated into two parts. The first part is to reset the physical layer of
IT6506. The second part is to reset the logical part of IT6506.
Initial Register Setting
The following table is the setting sequence for each step. The Bit Mask means the bit to
update on each step, and the Bit Value means the updating part of each step.
Reg
Bit Mas
Bit Value
0xEA
0xFF
0xFF
0xEA
0xFF
0x1
0
0xEB
0xFE
0xFE
0x1B3
0xFE
0xFE
0x1B3
0xFE
0x00
0x1B2
0xFF
4
0x1B2
0x0
5
1
0x1B5
0xFF
0x14
0x1B7
0xFF
0x33
0x1B8
0xFF
0x03
0x1CD
0xFF
0x80
0x1D2
0xFF
0x8
8
0x1D3
0xFF
0x69
0xEA
0x05
0x05
0xEA
0x05
0x04
0xEE
0x01
0x01
0x21
0xFF
0x0A
0x22
0xFF
0x64
0x2F
0xFF
0x7B
0xFD
0x05
4
0x31
0x40
0x40
0x32
0xFF
0xFF
0xB2
0x41
1
0xB7
0xFF
0x10
0xB8
0xFF
0x08
0xB9
0xFF
0x10
0xBA
0xFF
0x08
0xBB
0xFF
0x30
0xBC
0xFF
0x60
0xBD
0xF0
0x00
0xC0
0xFF
0x00
0xC1
0xBF
0xB
F
0xC2
0xFF
0x8C
0xC3
0xFF
0x7A
0xCC
0xFF
0xC5
0xCD
0xFF
0xA8
0xE3
0x80
0x80
0xEB
0x8F
0xF
0xEC
0x26
0x
2
6
0xEF
0x24
0x24
0xF1
0x40
0x40
0xFC
0xFF
0x21
0xD2
0xFF
0xE0
0xF6
0xFF
0x4C
0x1A5
0xFF
0xC8
0x1A2
0x10
0x00
0x1B1
0x04
0x04
0x1B1
0x78
0x00
0x170
0x0C
0x04
0xE4
0xFF
0
x00

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -5- 2013/11/12
0xE6
0xFF
0x00
0xE9
0xFF
0x00
0xE5
0xFF
0x07
0xE7
0xFF
0xFF
0xE8
0xFF
0xFF
0xC9
0x09
0x09
0xED
0xC0
0x80
0xEE
0x02
0x00
0xEE
0xFC
0xFC
0xC9
0x10
0x10
0xF7
0x01
0x00

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -6- 2013/11/12
Chap 3 Event of IT6506
The events of IT6506 will activate the bits in reg06, where each bit corresponded to a group of
event shows in the table reg07~reg0C.
Reg
Name
Bit
Descrioption
Type
06
Reserved
7:6
------------------------------------------
RO
IntGroup5
5
Group Reg0Ch Int
RO
IntGroup4
4
Group Reg0Bh Int
RO
IntGroup3
3
Grou
p Reg0Ah Int
RO
IntGroup2
2
Group Reg09h Int
RO
IntGroup1
1
Group Reg08h Int
RO
IntGroup0
0
Group Reg07h Int
RO
The event of IT6506 shows on the register Reg07~Reg0C, as the following table, where write
to one will clear the bits.
Reg
Name
Bit
Descr
ioption
Type
07
LSVBIDInt
7
VBID majority error interrupt
W1C
LSNAudInt
6
NAud majority error interrupt
W1C
LSMAudInt
5
M
a
ud majority error interrupt
W1C
LSMVidInt
4
Mvid majority error interrupt
W1C
RegAFUflow
3
A
udio fifo under flow
RO
RegAFOf
low
2
A
udio fifo over flow
RO
RegVFUflow
1
video fifo under flow
RO
RegVFOflow
0
video fifo over flow
RO
08
LSAudMuteEnd
7
Audio mute end interrupt
W1C
LSAudMuteStart
6
Audio mute start
interrupt
W1C
LSVidMuteEnd
5
Video mute end interrupt
W1C
L
SVidMuteStart
4
Video mute start interrupt
W1C
AutoAudMute
3
W
rite 1 will gen
REGHWMuteAACClr
W1C
RefAuxURLen
2
AUX receive un
-
support length interrupt
W1C
RefAuxURCmd
1
AUX receive un
-
support command interrupt
W1C
RefAuxSynErr
0
AUX receive sync l
ength error interrupt
W1C
09
LSNoSPDInfo
7
No SPD InfoFrame interrupt
W1C
LSNoMpegInfo
6
No Mpeg InfoFrame interrupt
W1C
LSNoAudInfo
5
No Audio InfoFrame interrupt
W1C
LSNoAVIInfo
4
No AVI InfoFrame interrupt
W1C
LSL3ECCInt
3
Lane 3 (2 nibble erro
r) ECC interrupt
W1C
LSL2ECCInt
2
Lane 2 (2 nibble error) ECC interrupt
W1C
LSL1ECCInt
1
Lane 1 (2 nibble error) ECC interrupt
W1C
LSL0ECCInt
0
Lane 0 (2 nibble error) ECC interrupt
W1C
0A
RefL3SymUnL IRQ
7
Lane 3 Symbol lose loc interrupt
W1C
Re
fL2SymUnL IRQ
6
Lane 2 Symbol lose loc interrupt
W1C
RefL
1
SymUnL IRQ
5
Lane 1 Symbol lose loc
interrupt
W1C
RefL
0
SymUnL IRQ
4
Lane 0 Symbol lose loc interrupt
W1C
RefLn TrnFalIRQ
3
Lin Training fail interrupt
W1C
RefSymUnAlgnIRQ
2
Symbol lose a
lignment interrupt
W1C
RefLn TrnDnIRQ
1
Lin Training done interrupt
W1C
RefLn TrnStrIRQ
0
Lin Training start interrupt
W1C
0B
RefAuthDnIRQ
7
Authentication done interrupt
W1C
RefAuthStartIRQ
6
Authentication start interrupt
W1C
RefLCFailIRQ
5
Li
n Integrity Chec fail interrupt
W1C
RefRiRdyIRQ
4
R0 ready interrupt
W1C
RefA svFailIRQ
3
Illegal A sv interrrupt
W1C
RefHPDRstNIRQ
2
HPD Reset interrupt
W1C
RefD3EntryInt
1
DPCD 00600h[1:0] have been changed to 10
from other values
W1C
RefD0En
tryInt
0
DPCD 00600h[1:0] have been changed to 01
from other values
W1C
0C
Reserved
7
------------------------------------------
RO

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -7- 2013/11/12
LSNewGenP t
6
New Mpeg InfoFrame interrupt
W1C
LSNewSPDInfo
5
New SPD InfoFrame interrupt
W1C
LSNewMpegInfo
4
New Mpe
g InfoFrame interrupt
W1C
LSNewAudInfo
3
New Audio InfoFrame interrupt
W1C
LSNewAVIInfo
2
New AVI InfoFrame interrupt
W1C
LSNewVidFormat
1
New Video format interrupt
W1C
RefI2CHangInt
0
I2C may hanging ( stay the same state too
long )
W1C
0D
LSL32
NibbleErr
7
Lane 3 ECC 2 nibble error
W1C
LSL22NibbleErr
6
Lane 2 ECC 2 nibble error
W1C
LSL12NibbleErr
5
Lane 1 ECC 2 nibble error
W1C
LSL02NibbleErr
4
Lane 0 ECC 2 nibble error
W1C
LSL31NibbleErr
3
Lane 3 ECC 1 nibble error
W1C
LSL21NibbleErr
2
Lane 2 ECC 1 nibble error
W1C
LSL11NibbleErr
1
Lane 1 ECC 1 nibble error
W1C
LSL01NibbleErr
0
Lane 0 ECC 1 nibble error
W1C
Where interrupt mask is in RegE4~RegE9, and the bits are one-to-one mapping to
reg07~reg0C:
Reg
Name
Bit
Description
Type
Defa
ult
Value
E4
RegIntMas
[7:0]
7:0
Interrupt Mas [7:0]
For register 07 ( one to one mapping )
R/W
11111111
E5
RegIntMas
[15:8]
7:0
Interrupt Mas [15:8]
For register 08
R/W
11111111
E6
RegIntMas
[23:16]
7:0
Interrupt Mas [23:16]
For Register 09
R/W
1111
1111
E7
RegIntMas
[31:24]
7:0
Interrupt Mas [31:24]
For Register 0A
R/W
11111111
E8
RegIntMas
[39:32]
7:0
Interrupt Mas [39:32]
For Register 0B
R/W
11111111
E9
RegIntMas [47]
7
Reserved For
future
use
R/W
1
RegIntMas [46:40]
6:0
For Resister 0C[6:0]
R/W
1111111