ITE IT6506 Operating instructions

IT6506 Programming Guide
Ver 1.02
Tseng Jau-Chih
ITE Tech. INC.
Last Update Date: 2013/11/12

History

-i
Index
Chap 1 Introduce .......................................................................................................... 1
Chap 2 IT6506 Initial..................................................................................................... 4
Initial Register Setting ...................................................................................................................4
Chap 3 Event of IT6506 ................................................................................................ 6
Chap 4 Link Configuration ............................................................................................ 8
Hot Plug ........................................................................................................................................8
System status................................................................................................................................8
IT6506 Capacity Configuring.........................................................................................................8
Detecting a Tx...............................................................................................................................8
Training .........................................................................................................................................8
Train Fail .......................................................................................................................................8
Chap 5 Video Programming.......................................................................................... 9
Video Input Readback...................................................................................................................9
Video Output Programming.........................................................................................................10
Output RGB444 video ............................................................................................................. 11
Output YCbCr444 video .......................................................................................................... 11
Output YCbCr422 video sync seperated................................................................................. 11
Output YCbCr422 video sync embedded................................................................................12
Output YCbCr422 video sync embedded CCIR656 ................................................................12
Color Converting .....................................................................................................................13
Enable Video Output ................................................................................................................... 14
Chap 6 Audio Programming........................................................................................ 15
Audio Input Information............................................................................................................... 15
Configure Audio Output............................................................................................................... 16
Audio Error..................................................................................................................................16
Chap 9 Registers ........................................................................................................ 19
Bank 0 : reg05[3] = ‘0’, reg05[0] = ‘0’ ..........................................................................................19
Bank 1 : Reg05[3][0] = ‘0’ ‘1’ .......................................................................................................31
Bank 2 : (reg5[3] = ‘1’, reg5[0] = ‘0’)............................................................................................ 37

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -1- 2013/11/12
Chap 1 Introduce
The IT6506 is a high-performance DisplayPort 1.1a receiver, fully compliant with DisplayPort
1.1a,
HDCP 1.3 specifications. The IT6506 with its Deep Color capability (up to 36-bit) ensures
robust reception of high-quality uncompressed video content, along with state-of-the-art
uncompressed and compressed digital audio content.
Aside from the various video output formats supported, the IT6506 also receives and provides
up to 8 channels of I
2
S digital audio outputs, with sampling rate up to 192kHz and sample size
up to 24 bits, facilitating direct connection to industry-standard low-cost audio DACs. Also, an
S/PDIF output is provided to support up to compressed audio of 192kHz frame rate.
Each IT6506 comes preprogrammed with an unique HDCP key, in compliance with the HDCP
1.3 standard so as to provide secure transmission of high-definition content. Users of the
IT6506 need not purchase any HDCP keys or ROMs.
Features
•Compliance with DisplayPort Specification V1.1a at 1.62/2.7 Gbps data rate (Low bit
rate/High bit rate)
•Support flexible 1/2/4 lanes configurations; Full 10.8Gbps data rate support(4 lanes at
2.7Gbps)
•Support DPCD Rev.1.1
•Support HDCP 1.3 with HDCP key embedded
•Support Spread Spectrum Clocking up to 0.5% down-spread to reduce EMI
•Support Source Connection Detection through AUX channel DC levels
•Support up to WQXGA(2560X1600) VESA display format
•Support Digital Video Output in 18/24/30/36(deep color) bits format with separate
Sync control
•Support Pixel component format with RGB; YCbCr 422; YCbCr 444
•Support Bit depth per color with 6/8/10/12 bits
•Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces
with programmable coefficients.
•Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2
•Dithering for conversion from 12-bit component to 10-bit/8-bit
•S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio up to 192kHz frame
rate
•Support 8-channel, uncompressed LPCM I2S audio with sample rates of 32~192 kHz
and sample sizes of 16~24 bits
•Automatic Audio Error detection with soft mute function, preventing annoying harsh
output sound due to audio error or hot-unplug

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ITE Tech. INC. -2- 2013/11/12
•Automatic loss of signal detection for Link management
•Intelligent, programmable power management
•144-pin LQFP (20mm x 20mm) package
Pin Diagram
17
18
19
20
21
22
23
24
25
37383940414243444546474849505152535455565758596061
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
26
27
28
29
30
31
32
33
34
35
6263646566676869707172
IT6506
Displayport RX Chip
LQFP-144
(Top View)
I2S2
I2S0
DCAUXN DCAUXP RX3N RX3P RX2N RX2P AVCC AGND RX1N RX1P AVCC RX0N RX0P DVDD18 PGND PVCC ASPGND ASPVCC RXAUXP RXAUXN XTALIN XTALOUT INT# PCADR
I2S3
ENTEST PGND PVCC
I2S1
WS
SCLK
EMEM_VPP
PCSCL PCSDA
QB2
QB3
QB6
QB7
QB8
QB9
QB5
QB4
IVSS
HPD
IVDD
IVDD
MCLK
SPDIF
OVDD
OVSS
OVDD
OVSS
QA20
QA21
QA26
QA27
QA28
IVDD
IVSS
QA30
QA31
OVDD
OVSS
QA22
QA23
QA24
QA25
QA32
QA35
DVSS18 DVDD18 AGND AVCC DVSS18
QA33
QA34
36
QA29
SYSRSTN
11
12
13
14
97
98
OVSS
QB10
QB11 QA16
QA17
QA18
QA19
95
OVDD
96
OVDD QB21 QB20
1
2
3
4
5
6
7
8
9
144143142141140139138137136135134133132131130129128127126125124123122121120
101
102
103
104
105
106
107
108
119118117116115114113112111110109
QB14
QB15
QB16
QB17
QB18
QB19
DDCSDA
DDCSCL
IVDD
IVSS
VSYNC HSYNC IVDD PCLK IVSS DE QA0 QA1 QA4 QA5 OVDD OVSS QA2 QA3 QB35 OVSS QB26 QB27 IVDD IVSS QB28 QB29 QB30 QB31 QB32 QB33 QB34 OVSS QB23 OVDD QB22
QA8
QA9
QA10
QA11
QA12
QA13
QA14
QA15
IVDD
IVSS
99
100
QA6 QA7
10
15
16
IT6506 provides internal register accessed via PCSCL (pin 71) and PCSDA (pin 70) with slave
address 0xB0 where PCADR (pin68) is low, or 0xB2 where PCADR (pin68) is high under
100KHz speed.
The terms listed in the below table are using in future chapters:
Term Description Example
RegXX Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in ban 0.
Reg05 – access with I
2
C slave
address 0xB0/0xB2,
sub-address 0x05.

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -3- 2013/11/12
Reg1XX
Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in ban 1.
Reg1C0 – access with I
2
C
slave address 0xB0/0xB2,
sub-address 0xC0.
Reg2XX Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in ban 2.
The register 0x00~0x0F are common for all banks, and the bank switching using as following:
bank 0 – reg05[3][0] = ‘0’ ‘0’
bank 1 – reg05[3][0] = ‘0’ ‘1’
bank 2 – reg05[3][0] = ‘1’ ‘0’

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -4- 2013/11/12
Chap 2 IT6506 Initial
IT6506 initial can be separated into two parts. The first part is to reset the physical layer of
IT6506. The second part is to reset the logical part of IT6506.
Initial Register Setting
The following table is the setting sequence for each step. The Bit Mask means the bit to
update on each step, and the Bit Value means the updating part of each step.
Reg
Bit Mas
Bit Value
0xEA
0xFF
0xFF
0xEA
0xFF
0x1
0
0xEB
0xFE
0xFE
0x1B3
0xFE
0xFE
0x1B3
0xFE
0x00
0x1B2
0xFF
4
0x1B2
0x0
5
1
0x1B5
0xFF
0x14
0x1B7
0xFF
0x33
0x1B8
0xFF
0x03
0x1CD
0xFF
0x80
0x1D2
0xFF
0x8
8
0x1D3
0xFF
0x69
0xEA
0x05
0x05
0xEA
0x05
0x04
0xEE
0x01
0x01
0x21
0xFF
0x0A
0x22
0xFF
0x64
0x2F
0xFF
0x7B
0xFD
0x05
4
0x31
0x40
0x40
0x32
0xFF
0xFF
0xB2
0x41
1
0xB7
0xFF
0x10
0xB8
0xFF
0x08
0xB9
0xFF
0x10
0xBA
0xFF
0x08
0xBB
0xFF
0x30
0xBC
0xFF
0x60
0xBD
0xF0
0x00
0xC0
0xFF
0x00
0xC1
0xBF
0xB
F
0xC2
0xFF
0x8C
0xC3
0xFF
0x7A
0xCC
0xFF
0xC5
0xCD
0xFF
0xA8
0xE3
0x80
0x80
0xEB
0x8F
0xF
0xEC
0x26
0x
2
6
0xEF
0x24
0x24
0xF1
0x40
0x40
0xFC
0xFF
0x21
0xD2
0xFF
0xE0
0xF6
0xFF
0x4C
0x1A5
0xFF
0xC8
0x1A2
0x10
0x00
0x1B1
0x04
0x04
0x1B1
0x78
0x00
0x170
0x0C
0x04
0xE4
0xFF
0
x00

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ITE Tech. INC. -5- 2013/11/12
0xE6
0xFF
0x00
0xE9
0xFF
0x00
0xE5
0xFF
0x07
0xE7
0xFF
0xFF
0xE8
0xFF
0xFF
0xC9
0x09
0x09
0xED
0xC0
0x80
0xEE
0x02
0x00
0xEE
0xFC
0xFC
0xC9
0x10
0x10
0xF7
0x01
0x00

IT6506 PROGRAMMING GUIDE
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Chap 3 Event of IT6506
The events of IT6506 will activate the bits in reg06, where each bit corresponded to a group of
event shows in the table reg07~reg0C.
Reg
Name
Bit
Descrioption
Type
06
Reserved
7:6
------------------------------------------
RO
IntGroup5
5
Group Reg0Ch Int
RO
IntGroup4
4
Group Reg0Bh Int
RO
IntGroup3
3
Grou
p Reg0Ah Int
RO
IntGroup2
2
Group Reg09h Int
RO
IntGroup1
1
Group Reg08h Int
RO
IntGroup0
0
Group Reg07h Int
RO
The event of IT6506 shows on the register Reg07~Reg0C, as the following table, where write
to one will clear the bits.
Reg
Name
Bit
Descr
ioption
Type
07
LSVBIDInt
7
VBID majority error interrupt
W1C
LSNAudInt
6
NAud majority error interrupt
W1C
LSMAudInt
5
M
a
ud majority error interrupt
W1C
LSMVidInt
4
Mvid majority error interrupt
W1C
RegAFUflow
3
A
udio fifo under flow
RO
RegAFOf
low
2
A
udio fifo over flow
RO
RegVFUflow
1
video fifo under flow
RO
RegVFOflow
0
video fifo over flow
RO
08
LSAudMuteEnd
7
Audio mute end interrupt
W1C
LSAudMuteStart
6
Audio mute start
interrupt
W1C
LSVidMuteEnd
5
Video mute end interrupt
W1C
L
SVidMuteStart
4
Video mute start interrupt
W1C
AutoAudMute
3
W
rite 1 will gen
REGHWMuteAACClr
W1C
RefAuxURLen
2
AUX receive un
-
support length interrupt
W1C
RefAuxURCmd
1
AUX receive un
-
support command interrupt
W1C
RefAuxSynErr
0
AUX receive sync l
ength error interrupt
W1C
09
LSNoSPDInfo
7
No SPD InfoFrame interrupt
W1C
LSNoMpegInfo
6
No Mpeg InfoFrame interrupt
W1C
LSNoAudInfo
5
No Audio InfoFrame interrupt
W1C
LSNoAVIInfo
4
No AVI InfoFrame interrupt
W1C
LSL3ECCInt
3
Lane 3 (2 nibble erro
r) ECC interrupt
W1C
LSL2ECCInt
2
Lane 2 (2 nibble error) ECC interrupt
W1C
LSL1ECCInt
1
Lane 1 (2 nibble error) ECC interrupt
W1C
LSL0ECCInt
0
Lane 0 (2 nibble error) ECC interrupt
W1C
0A
RefL3SymUnL IRQ
7
Lane 3 Symbol lose loc interrupt
W1C
Re
fL2SymUnL IRQ
6
Lane 2 Symbol lose loc interrupt
W1C
RefL
1
SymUnL IRQ
5
Lane 1 Symbol lose loc
interrupt
W1C
RefL
0
SymUnL IRQ
4
Lane 0 Symbol lose loc interrupt
W1C
RefLn TrnFalIRQ
3
Lin Training fail interrupt
W1C
RefSymUnAlgnIRQ
2
Symbol lose a
lignment interrupt
W1C
RefLn TrnDnIRQ
1
Lin Training done interrupt
W1C
RefLn TrnStrIRQ
0
Lin Training start interrupt
W1C
0B
RefAuthDnIRQ
7
Authentication done interrupt
W1C
RefAuthStartIRQ
6
Authentication start interrupt
W1C
RefLCFailIRQ
5
Li
n Integrity Chec fail interrupt
W1C
RefRiRdyIRQ
4
R0 ready interrupt
W1C
RefA svFailIRQ
3
Illegal A sv interrrupt
W1C
RefHPDRstNIRQ
2
HPD Reset interrupt
W1C
RefD3EntryInt
1
DPCD 00600h[1:0] have been changed to 10
from other values
W1C
RefD0En
tryInt
0
DPCD 00600h[1:0] have been changed to 01
from other values
W1C
0C
Reserved
7
------------------------------------------
RO

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LSNewGenP t
6
New Mpeg InfoFrame interrupt
W1C
LSNewSPDInfo
5
New SPD InfoFrame interrupt
W1C
LSNewMpegInfo
4
New Mpe
g InfoFrame interrupt
W1C
LSNewAudInfo
3
New Audio InfoFrame interrupt
W1C
LSNewAVIInfo
2
New AVI InfoFrame interrupt
W1C
LSNewVidFormat
1
New Video format interrupt
W1C
RefI2CHangInt
0
I2C may hanging ( stay the same state too
long )
W1C
0D
LSL32
NibbleErr
7
Lane 3 ECC 2 nibble error
W1C
LSL22NibbleErr
6
Lane 2 ECC 2 nibble error
W1C
LSL12NibbleErr
5
Lane 1 ECC 2 nibble error
W1C
LSL02NibbleErr
4
Lane 0 ECC 2 nibble error
W1C
LSL31NibbleErr
3
Lane 3 ECC 1 nibble error
W1C
LSL21NibbleErr
2
Lane 2 ECC 1 nibble error
W1C
LSL11NibbleErr
1
Lane 1 ECC 1 nibble error
W1C
LSL01NibbleErr
0
Lane 0 ECC 1 nibble error
W1C
Where interrupt mask is in RegE4~RegE9, and the bits are one-to-one mapping to
reg07~reg0C:
Reg
Name
Bit
Description
Type
Defa
ult
Value
E4
RegIntMas
[7:0]
7:0
Interrupt Mas [7:0]
For register 07 ( one to one mapping )
R/W
11111111
E5
RegIntMas
[15:8]
7:0
Interrupt Mas [15:8]
For register 08
R/W
11111111
E6
RegIntMas
[23:16]
7:0
Interrupt Mas [23:16]
For Register 09
R/W
1111
1111
E7
RegIntMas
[31:24]
7:0
Interrupt Mas [31:24]
For Register 0A
R/W
11111111
E8
RegIntMas
[39:32]
7:0
Interrupt Mas [39:32]
For Register 0B
R/W
11111111
E9
RegIntMas [47]
7
Reserved For
future
use
R/W
1
RegIntMas [46:40]
6:0
For Resister 0C[6:0]
R/W
1111111

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -8- 2013/11/12
Chap 4 Link Configuration
Hot Plug
IT6506 can determine the HPD to Tx side with regC9[4] = ‘1’ for plugged and ‘0’ for unplugged.
Trigger HPD interrupt with reg1F[6] to notify DP source device.
System status
The following register regC8 shows the system status of IT6506:
reg
name
bit
description
type
C8
Reserved
7:6
------------------------------------------
RegLn TrnFail
5
Lin Training fail status
RO
RegTxSense
4
Tx Sense status
RO
RegTxPwrSense
3
Tx power is on
RO
RegTxConnected
2
Tx is connected
RO
RegLn TrnDn
1
Lin Training done status
RO
RegLn TrnBusy
0
Lin Training busy status
RO
The system state transition can refer these bits to judge the status transition.
IT6506 Capacity Configuring
Set DP sink capability with the following table:
Feature
Reg Setting
Acceptable Maximum Lane Number
4
lane
s
–
reg22[2:0] = ‘100’
2 lanes –
reg22[2:0] = ‘010’
1 lane –
reg22[2:0] = ‘001’
SSC
reg22[6] =
‘
1
’
for
enabling
Enhance Framing
reg22[5] =
‘
1
’
for enabling
Detecting a Tx
regC8[4] = ‘1’, means a DP 1.1a transmitter connected.
Training
When DisplayPort transmitter start link training, regC8[0] will be read back as ‘1’. If training
done, regC8[1] = ‘1’ until next training start or fail.
After training done, the video and audio can be measuring.
Train Fail
Detecting a training fail in regC8[4] = ‘1’, the training fail.

IT6506 PROGRAMMING GUIDE
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Chap 5 Video Programming
If DP connection are built and trained, the video will be sent from DP source. Video and audio
input status are present in reg11:
11
Reserved
7:6
------------------------------------------
RO
RegAudStable
5
A
udio output stable
RO
RegVidStable
4
video output stable
RO
Video Input Readback
And begin to program the video output and pass the video parameter defined in the following
registers:
Input Video Pixel Clock is in reg11[3:0]|10[7:0]
10
RegPCl Cnt
[7:0]
7:0
PCLKCnt = the tic count of PCLK under 1024T of
27MHz reference cloc .
PCLK = 27MHz*1024/PCLKCnt
RO
11
Reserved
7:6
RO
RegAudStable
5
A
udio output stable
RO
RegVidStable
4
video output stable
RO
RegPCl Cnt
[11:8]
3:0
RO
If RegPclkCnt = 186, PCLK = 27MHz * 1024/186 = 148.6MHz
Input Video status registers:
Reg
Name
bit
Description
Type
97
LSHTotal
[7:0]
7:0
H total [7:0]
RO
98
LSHTotal
[15:8]
7:0
H total [15:8]
RO
99
LSHStart
[7:0]
7:0
H start [7:0] from H
sync start edge to H active start edge
RO
9A
LSHStart
[15:8]
7:0
H start [15:8] from Hsync start edge to H active start edge
RO
9B
LSHWidth
[7:0]
7:0
M
ain stream attribute data
-
H active width [7:0]
RO
9C
LSHWidth
[15:8]
7:0
M
ain stream attribute data
-
H
active width [15:8]
RO
9D
LSVTotal
[7:0]
7:0
M
ain stream attribute data
-
V total [7:0]
RO
9E
LSVTotal
[15:8]
7:0
M
ain stream attribute data
-
V total [15:8]
RO
9F
LSVStart
[7:0]
7:0
M
ain stream attribute data
-
V start [7:0] from Vsync start
edge to V active start edge
RO
A0
LSVStart
[15:8]
7:0
M
ain stream attribute data
-
V start [15:8] from Vsync start
edge to V active start edge
RO
A1
LSVHeight
[7:0]
7:0
M
ain stream attribute data
-
V active height [7:0]
RO
A2
LSVHeight
[15:8]
7:0
M
ain stream attribute data
-
V active height [15:8]
RO
A3
LSHSyncWidth
[7:0]
7:0
M
ain stream attribute data
-
H Sync Width [7:0]
RO
A4
LSHSyncPolarity
7
M
ain stream attribute data
-
H Sync polarity
RO
LSHSyncWidth
[14:8]
6:0
M
ain stream attribute data
-
H Sync Width[14:8]
RO
A5
LSVSy
ncWidth
7:0
M
ain stream attribute data
-
V Sync Width [7:0]
RO
A6
LSVSyncPolarity
7
M
ain stream attribute data
-
VSync polarity
RO
LSVSyncWidth
6:0
M
ain stream attribute data
-
V Sync Width[7:0]
RO
A7
LSVdBPC
7:5
M
ain stream attribute data
-
B
it depth per
color / component
000 = 6 bits
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 16 bits
101, 110, 111 = Reserved
RO
LSVdYUVColor
4
M
ain stream attribute data
-
YCbCr Colorietry
0: ITU-R BT601-5
1: ITU-R BT709-5
RO

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LSVdRange
3
M
ain stream attribute data
-
D
ynamic range
0: VESA range ( from 0 to the maximum )
1: CEA range
RO
LSVdPxlFormat
2:1
M
ain stream attribute data
-
C
omponent format
00: RGB
01: YCbCr 4:2:2
10: YCbCr 4:4:4
11: Reserved
RO
LSCLKSync
0
M
ain stream attribute data
-
Synchronous cloc
0: Lin cloc and stream cloc asynchronous
1: Lin cloc and stream cloc synchronous
RO
A8
Reserved
7:3
------------------------------------------
RO
LSStereoVdAttr
2:1
M
ain stream attribute data
-
Stereo video attribute
00: No stereo video transported
01: for progressive vide, the next frame is RIGHT eye, for
interlaced video, TOP field is RIGHT eye and BOTTOM field is
LEFT eye
10: reserved and must not be used
11: for progressive video, the next frame is LEFT eye, for
interlaced video, TOP field is LEFT eye and BOTTOM field is
RIGHT eye
RO
LSVdIFrameEven
0
M
ain stream attribute data
-
Interlaced vertical total even
0: number of lines per interlaced frame ( consisting of two
fields ) is an odd number
1: number of lines per interlaced frame ( consisting of two
fields ) is an even number
RO
Video Output Programming
Video output path control registers are listed in the following table:
Reg
Name
bit
Description
Type
Default
Value
170
Reg_LMSwap
7
1: swap output direction(MSB/LSB)
R/W
0
Reg_O16Bit
6
‘
1
’
: YCbCr422 output only 16bit width
‘0’: YCbCr422 output is 24/20 bit width.
R/W
0
Reg_OUTBit
5:4
00: output 8 bits per color channel
01:output 10 bits per color channel
10:output 12 bits per color channel
11: reserved
R/W
00
Reg_ColorDepth
3:2
00: output 8 bits 444 format
01: output 10 bits 444 format
10: output 12 bits 444 format
R/W
01
Reg_PCLKDiv2
1
‘
1
’
: output half PCLK
R/W
0
Reg_ChgSyncPol
0
‘
1
’
: output H/V sync indicated by reg171[2]/reg171[3]
‘0’: eep the original sync polarity.
R/W
0
171
Reg_PGEn
7
reserved
R/W
0
Reg_DNFreeGo
6
‘
1
’
: Dither free go.
R/W
0
Reg_EnUdFilt
5
‘
1
’
: Enable 444
↔
422 up/down filter
R/W
0
Reg_EnDither
4
‘
1
’
: Enable Dither
R/W
0
Reg_VSyncPol
3
‘
1
’
: Set V sync polarity as positive while reg170[0] as
‘
1
’
‘0’: Set V sync polarity as negative while reg170[0] as ‘1’
R/W
0
Reg_HSyncPol
2
‘
1
’
: Set H sync polarity as positive while reg170[0] as
‘
1
’
‘0’: Set YH sync polarity as negative while reg170[0] as ‘1’
R/W
0
Reg_ChSwap
1
‘
1
’
: Swap output R/B(Cr/Cb) channel
R/W
0
Reg_RBSwap
0
‘
1
’
: Swap input R/B(Cr/Cb
) channel
R/W
0
To determine the output color mode, the setting are listed as following:

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -11- 2013/11/12
Output RGB444 video
The output value should be:
bit
Value
170
Reg_LMSwap
7
0
Reg_O16Bit
6
0
Reg_OUTBit
5:4
Reg_ColorDepth
3:2
Reg_PCLKDiv2
1
0
Reg_ChgSyncPol
0
0
171
Reg_PGEn
7
0
Reg_DNFreeGo
6
x
Reg_EnUdFilt
5
x
Reg_EnDither
4
x
Reg_VSyncPol
3
x
Reg_
HSyncPol
2
x
Reg_ChSwap
1
x
Reg_RBSwap
0
x
176
Reg_SyncEmb
3
0
18F
Reg_OutDDR
7
0
Reg_2x656Cl
6
0
Reg_656FFRst
5
0
Reg_EnAVMuteRst
4
0
Reg_CSCSel
3:2
00 / 02
Reg_OutColMod
1:0
00
Output YCbCr444 video
The output value should be:
bit
Va
lue
170
Reg_LMSwap
7
0
Reg_O16Bit
6
0
Reg_OUTBit
5:4
Reg_ColorDepth
3:2
Reg_PCLKDiv2
1
0
Reg_ChgSyncPol
0
0
176
Reg_SyncEmb
3
0
171
Reg_PGEn
7
0
Reg_DNFreeGo
6
x
Reg_EnUdFilt
5
x
Reg_EnDither
4
x
Reg_VSyncPol
3
x
Reg_HSyncPol
2
x
Reg_ChSwap
1
x
Reg_RBSwap
0
x
18F
Reg_OutDDR
7
0
Reg_2x656Cl
6
0
Reg_656FFRst
5
0
Reg_EnAVMuteRst
4
0
Reg_CSCSel
3:2
00 / 03
Reg_OutColMod
1:0
10
Output YCbCr422 video sync seperated
The output value should be:
bit
Value
170
Reg_LMSwap
7
0

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -12- 2013/11/12
Reg_O16Bit
6
x
Reg_OUTBit
5:4
00
Reg_ColorDepth
3:2
00
Reg_PCLKDiv2
1
0
Reg_ChgSyncPol
0
0
176
Reg_SyncEmb
3
0
171
Reg_PGEn
7
0
Reg_DNFreeGo
6
x
Reg_EnUdFilt
5
x
Reg_EnDither
4
x
Reg_VSyncPol
3
x
Reg_HSyncPol
2
x
Reg_ChSwap
1
x
Reg_RBSwap
0
x
18F
Reg_OutDDR
7
0
Reg_2x656Cl
6
0
Reg_656FFRst
5
0
Reg_EnAVMuteRst
4
0
Reg_CSCSel
3:2
00 / 03
Reg_OutColMod
1:0
01
Output YCbCr422 video sync embedded
The output value should be:
bit
Value
170
Reg_LMSwap
7
0
Reg_O16Bit
6
0
Reg_OUTBit
5:4
00
Reg_ColorDepth
3:2
00
Reg_PCLKDiv2
1
0
Reg_ChgSyncPol
0
0
176
Reg_SyncEmb
3
1
171
Reg_PGEn
7
0
Reg_DNFreeGo
6
x
Reg_EnUdFilt
5
x
Reg_EnDither
4
x
Reg_VSyncPol
3
x
Reg_HSyncPol
2
x
Reg_ChSwap
1
x
Reg_RBSwap
0
x
1
8F
Reg_OutDDR
7
0
Reg_2x656Cl
6
0
Reg_656FFRst
5
0
Reg_EnAVMuteRst
4
0
Reg_CSCSel
3:2
00 / 02
Reg_OutColMod
1:0
00
Output YCbCr422 video sync embedded CCIR656
The output value should be:
bit
Value
170
Reg_LMSwap
7
0
Reg_O16Bit
6
0
Reg_OU
TBit
5:4
00
Reg_ColorDepth
3:2
00
Reg_PCLKDiv2
1
0
Reg_ChgSyncPol
0
0
171
Reg_PGEn
7
0
Reg_DNFreeGo
6
x
Reg_EnUdFilt
5
x

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -13- 2013/11/12
Reg_EnDither
4
x
Reg_VSyncPol
3
x
Reg_HSyncPol
2
x
Reg_ChSwap
1
x
Reg_RBSwap
0
x
176
Reg_SyncEmb
3
1
18F
Reg_Out
DDR
7
0
Reg_2x656Cl
6
1
Reg_656FFRst
5
0
Reg_EnAVMuteRst
4
0
Reg_CSCSel
3:2
00 / 02
Reg_OutColMod
1:0
00
Color Converting
If the input color and output color need a color space convert, the convert matrix are defined in
the following registers:
Reg
Name
bit
description
Type
default
173
Reg_YOffSet
7:0
R/W
00000000
174
Reg_COffSet
7:0
R/W
00000000
175
Reg_RGBOffSet
7:0
R/W
00000000
190
Reg_Matrix11V
[7:0]
7:0
CSC matrix 11 low byte
R/W
10110010
191
Reserved
7:6
----------------------------
--------------
RO
Reg_Matrix11V
[13:8]
5:0
CSC matrix 11 high bits
R/W
000100
192
Reg_Matrix1
2
V
[7:0]
7:0
CSC matrix 12 low byte
R/W
01100100
193
Reserved
7:6
------------------------------------------
RO
Reg_Matrix1
2
V
[13:8]
5:0
CSC matrix 12 high bi
ts
R/W
000010
194
Reg_Matrix1
3
V
[7:0]
7:0
CSC matrix 13 low byte
R/W
11101001
195
Reserved
7:6
------------------------------------------
RO
Reg_Matrix1
3
V
[13:8]
5:0
CSC matrix 13 high bits
R/W
000000
196
Reg_Matrix
2
1V
[7:0]
7:0
CSC matrix 21 low byte
R
/W
10010011
197
Reserved
7:6
------------------------------------------
RO
Reg_Matrix
2
1V
[13:8]
5:0
CSC matrix 21 high bits
R/W
011100
198
Reg_Matrix
22
V
[7:0]
7:0
CSC matrix 22 low byte
R/W
00010110
199
Reserved
7:6
------------------------------------
------
RO
Reg_Matrix
22
V
[13:8]
5:0
CSC matrix 22 high bits
R/W
000100
19A
Reg_Matrix
23
V
[7:0]
7:0
CSC matrix 23 low byte
R/W
01010110
19B
Reserved
7:6
------------------------------------------
RO
Reg_Matrix
23
V
[13:8]
5:0
CSC matrix 23 high bits
R/W
0
11111
19C
Reg_Matrix
31
V
[7:0]
7:0
CSC matrix 31 low byte
R/W
01001001
19D
Reserved
7:6
------------------------------------------
RO
Reg_Matrix
31
V
[13:8]
5:0
CSC matrix 31 high bits
R/W
011101
19E
Reg_Matrix
32
V
[7:0]
7:0
CSC matrix 32 low byte
R/W
10011
111
19F
Reserved
7:6
------------------------------------------
RO
Reg_Matrix
32
V
[13:8]
5:0
CSC matrix 32 high bits
R/W
011110
1A0
Reg_Matrix
33
V
[7:0]
7:0
CSC matrix 33 low byte
R/W
00010110
1A1
Reserved
7:6
------------------------------------------
R
O
Reg_Matrix
33
V
[13:8]
5:0
CSC matrix 33 high bits
R/W
000100
To setting the matrix, depends the input color and output color mapping:
Color space converting table
RGB to YUV
YUV to RGB
RGB to YUV
601
RGB to YUV 709
YUV to RGB
601
YUV to RGB
709
re
g
16~ 235
0 ~ 255
16~ 235
0 ~ 255
16~ 235
0 ~ 255
16~ 235
0 ~ 255
Reg_CSCSel[1:0]
18F[3:2]
10
10
10
10
11
11
11
11
Reg_YoffSet[7:0]
1
73
0x00
0x10
0x00
0x10
0x00
0x10
0x00
0x10
Reg_CoffSet[7:0]
1
74
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
Reg_RGBOffSet[7
:0]
1
75
0x00
0x10
0x00
0x10
0x00
0x10
0x00
0x10
Reg_Matrix11V[13:0]
190
0xB2
0x09
0xB8
0xE5
0x00
0x4F
0x00
0x4F
191
0x04
0x04
0x05
0x04
0x08
0x09
0x08
0x09

IT6506 PROGRAMMING GUIDE
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Reg_Matrix12V[13:0]
192
0x64
0x0E
0xB4
0x78
0x6A
0x81
0x53
0xBA
193
0x02
0x02
0x01
0x01
0x3A
0
x39
0x3C
0x3B
Reg_Matrix13V[13:0]
194
0xE9
0xC8
0x93
0x81
0x4F
0xDF
0x89
0x4B
195
0x00
0x00
0x00
0x00
0x3D
0x3C
0x3E
0x3E
Reg_Matrix21V[13:0]
196
0x93
0x0E
0x49
0xCE
0x00
0x4F
0x00
0x4F
197
0x3C
0x3D
0x3C
0x3C
0x08
0x09
0x08
0x09
Reg_Matrix22V[13:0]
198
0x18
0x84
0x18
0x84
0xF7
0xC2
0x51
0x56
199
0x04
0x03
0x04
0x03
0x0A
0x0C
0x0C
0x0E
Reg_Matrix23V[13:0]
19A
0x56
0x6E
0x9F
0xAE
0x00
0x00
0x00
0x00
19B
0x3F
0x3F
0x3F
0x3F
0x00
0x00
0x00
0x00
Reg_Matrix31V[13:0]
19C
0x49
0xAC
0xD9
0x49
0x00
0x4F
0x00
0x4F
19D
0x3D
0x3D
0x3C
0x3D
0x08
0x09
0x08
0x09
Reg_Matrix32V[13:0]
19E
0x9F
0xD0
0x10
0x33
0x00
0x00
0x00
0x00
19F
0x3E
0x3E
0x3F
0x3F
0x00
0x00
0x00
0x00
Reg_Matrix33V[13:0]
1A0
0x18
0x84
0x18
0x84
0xDB
0x1E
0x87
0xE7
1A1
0x04
0x03
0x04
0x
03
0x0D
0x10
0x0E
0x10
Enable Video Output
Set Reg35[3] as zero to enable video output.
To enable video IO, regEB[5:4] = ‘00’
To enable video data output, in single pixel mode, regEE[7:2] = ‘111000’; if under dual pixel
mode, regEE[7:2] = ‘000000’ .

IT6506 PROGRAMMING GUIDE
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Chap 6 Audio Programming
RegEA[2] = ‘0’, the audio program is available.
The audio related registers are listed as following table:
Audio Control Register
reg
Name
bit
description
type
Default
88
LSAudStrID
7:0
Audio stream pac et ID
RO
89
LSAudStrCType
6:3
Audio s
tream coding type
RO
LSAudStrChCnt
2:0
Audio stream channel count
RO
F6
RegWs_sel
7
I2S word select switch
0: left -> right, 1:right->left
R/W
0
RegACINC
6
R/W
0
RegMCLKSel
5:4
R/W
01
RegARDec
3:2
R/W
00
RegAPLLGain
1:0
R/W
01
F7
RegI2s_m
ode
7:6
I2S mapping mode select
00:i2s, 01:right, 10:left, 11:raw 60958
R/W
00
RegAudVolCtrl
5:4
A
udio
volume
control
R/W
00
RegHWAudMuteClrMode
3
A
udio hardware mute clear enable
R/W
0
RegBiphasemode
2
S
PDIF output enable
R/W
0
RegHWMuteClr
1
A
udi
o hardware mute clear
R/W
0
RegHWMuteEn
0
A
udio hardware mute enable
R/W
0
F8
RegI2S_CH3SEL
7:6
I2S channel 3 output source select
R/W
11
RegI2S_CH
2
SEL
5:4
I2S channel 2 output source select
R/W
10
RegI2S_CH
1
SEL
3:2
I2S channel 1 output source sele
ct
R/W
01
RegI2S_CH
0
SEL
1:0
I2S channel 0 output source select
R/W
00
F9
RegHWMuteRate
[7:0]
7:0
A
udio hardware mute rate low byte
R/W
001000
00
FA
RegI2s_width
7:3
I2S
word
length select
R/W
11000
RegHWMuteRate
[10:8]
2:0
A
udio hardware mute rate high
bits
R/W
000
FB
Reserved
7:6
------------------------------------------
RO
RegFSdec
3:0
Sample frequency indicated in
IEC60958
-
3 p11
bit 24~27 .
Sample frequency of software indicated
27..24
--------
0000 44.1 KHz
1000 88.2 KHz
1100 176.4 KHz
0110 24 Khz
0010 48Khz
1010 96Khz
1110 192KHz
0011 32KHz
0000 sampling frequency not indicated.
RO
The output value can be decided in the initial stage, and only enable audio output while the
audio stable in Reg35[1].
Audio Input Information
Audio is stable when reg10[5] = ‘1’. If no audio stable, and no overflow/underflow interrupt
arriving, there is no audio.
If audio input change or invalid, the audio FIFO overflow/underflow interrupt responds in
reg07[3][2]. When audio change and invalid, reset audio (regEA[2] = ‘1’) and wait for audio
input stable again.

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -16- 2013/11/12
Audio channel number is presented on reg89[2:0], and sample frequency is presented on
regFB[3:0].
Configure Audio Output
When audio input is available, following the steps described below to configure audio output.
1. regEA[2] = ‘0’.
2. reg1B1[2] = ‘0’
3. reg1B3[2] = ‘1’, regEA[2] = ‘1’
4. reg1B3[2] = ‘0’, regEA[2] = ‘0’
5. If mini mode, set regF5[7] = ‘1’, otherwise, set is as ‘0’.
6. Enable audio output from IT6505:
•If require SPDIF output, set regEB[3] = ‘0’.
•If require I2S for 5~8 channel audio, set regEB[2][1] = ‘0’ ‘0’
•If only require I2S audio with 1~4 channel, set regEB[2][1] = ‘1’ ‘0’
Audio Error
If audio input have error, audio will be automatic mute by IT6506. The interrupt of audio
overflow/underflow will be activated. When audio error, reset the audio circuit with regEA[2] =
‘1’, then reprogram the audio with previous sequence.

IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -17- 2013/11/12
DPCD
Offset
Name
Coun
t
Reg
map
Reg
Mod
Funcgtion
68000
BKSV
5
130
HDCP register
s are located in DPCD address
0x68000~0x6803A, which are mapping to IT6504 ban 1
register 30~6A.
Those registers are read only, and the register should update by
other registers.
68005
R0
’
2
135
68007
AKSV
5
137
6800C
An
8
13C
68014
V
’
H1
4
14
4
224
225
226
227
The V' calculation should do the SHA
-
1 calculation via software.
No hardware way to calculate.
The calculation of V' (reg224~reg237) need KSVList
(reg15C~reg16A),
68018
V
’
H2
4
148
228
229
22A
22B
6801C
V
’
H3
4
14C
22C
22D
22E
22F
6
8020
V
’
H4
4
150
230
231
232
233
68024
V
’
H5
4
154
234
235
236
237
68028
BCaps
1
158
bit 1
–
REPEATER
RegCF[2] RegSetRepeater = this bit
bit 0 – HDCP_CAPABLE
RegB2[0] RegCPDesired
68029
BStatus
1
159
bit 2
–
lin ingtegrity_fail
–
loss of cipher s
ynchronizationi.
bit 1 – R0 Available
bit 0 – Ready – HDCP repeater KSV FIFO ready.
Bstatus[2], LINK_INTEGRITY_FAILURE, is indicated by the HW.
Bstatus[1], R0'_AVALILABLE, is indicated by the HW.
Bstatus[0], READY, is programed by RegCF[1], RegSetVReady.
6802A
BInfo
1
15A
238
239
bit 11
–
MAX_CASCADE_EXCEEDED
bit [10:8] – DEPTH
bit [7] – MAX_DEV_EXCEEDED
bit[6:0] – Downstream counter
6802C
KSV
FIFO
15
15C
RegCF[0] – CPReady set.
RegCF[1] – write ‘1’ to trigger 68029[0] as ‘1’, and need to clear immediatly.
Reg
Name
Type
Description
1E3
invM0[7:0]
R/O
inverse of M0
1E4
invM0[15:8]
R/O
1E5
invM0[23:16]
R/O
1E6
invM0[31:24]
R/O
1E7
invM0[39:32]
R
/O
1E8
invM0[47:40]
R/O
1E9
invM0[55:48]
R/O
1EA
invM0[63:56]
R/O
210~214
KSV0
R/W
215~219
KSV1
R/W
21A~21E
KSV2
R/W
21F~223
KSV3
R/W
224~237
VH
R/W