ITE IT6605 Operating instructions

深圳市金合讯科技有限公司，0755-36853282，18664341585
IT6605 HDMI 1.4 3D Receiver
Programming Guide
Ver 1.00
Tseng, Jau-Chih
ITE Tech.
Last Update Date: 2010/12/07

深圳市金合讯科技有限公司，0755-36853282，18664341585
History
2010/08/10 – Created by Tseng, Jau-chih
2010/08/11 – Added Audio Part.
2010/12/07 – Added HDCP part.

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-i
Index
Chap 1 Introduction ..................................................................................................................1
Chap 2 Initial Progress .............................................................................................................2
Initial Progress..............................................................................................................................................2
Initial Value List ...........................................................................................................................................2
Chap 3 Video Output.................................................................................................................4
Video Output Flow .......................................................................................................................................4
Video Path ....................................................................................................................................................5
Video Input Selection ...................................................................................................................................5
Video Output Configuration .........................................................................................................................6
Color Space Matrix.......................................................................................................................................7
Video I/O and Video Data I/O Tristate..........................................................................................................8
Event of Video Process.............................................................................................................................9
Video input mode resolution.......................................................................................................................10
Video CDR Reset........................................................................................................................................10
Chap 4 Audio Output...............................................................................................................11
Audio Control Registers .............................................................................................................................11
HDMI Audio Input Status...........................................................................................................................12
Audio Output Configure.............................................................................................................................13
Default Setting .......................................................................................................................................13
I2S mode and word length......................................................................................................................13
Output LPCM Audio on I2S Channel.........................................................................................................14
Output LPCM Audio on SPDIF Channel....................................................................................................14
Output NLPCM Audio on I2S Channel......................................................................................................14
Output NLPCM Audio on SPDIF Channel.................................................................................................15
Output High Bit Rate on I2S Channel ........................................................................................................15
Output High Bit Rate on SPDIF Channel...................................................................................................15
Output LPCM/NLPCM Audio with Force Fs setting..................................................................................15
Error Handling............................................................................................................................................16
Chap 5 HDMI Infoframe.........................................................................................................17
Chap 6 HDCP Support............................................................................................................19
HDCP Repeater setting...............................................................................................................................19
HDCP registers for repeater function .....................................................................................................21
HDCP Debug Status...............................................................................................................................22
Chap 7 3D Support..................................................................................................................23
Part 2 – Software Release Code Reference.....................................................................................26
Chap 8 Introduce.....................................................................................................................26
Chap 9 Flow............................................................................................................................27
Chap 10 Data Type....................................................................................................................30
Chap 11 Sample Code Required Interface................................................................................31
Chap 12 Software Interface.......................................................................................................32

深圳市金合讯科技有限公司，0755-36853282，18664341585
IT6605 PROGRAMMING GUIDE
ITE Tech. -1- 2010/12/07
Chap 1 Introduction
The IT6605 is a dual-port HDMI 1.4 receiver. The IT6605 with its Deep Color capability (up to 36-bit)
ensures robust reception of high-quality uncompressed video content, along with state-of-the-art
uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital
televisions and projectors.
Aside from the various video output formats supported, the IT6605 also receives and provides up to 8
channels of I2S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits,
facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is
provided to support up to compressed audio of 192kHz frame rate. SuperAudio Compact Disc (SACD)
is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports.
Each IT6605 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.2
standard so as to provide secure transmission of high-definition content. Users of the IT6605 need not
purchase any HDCP keys or ROMs.
To program IT6605 need using I2C access the PCSDA (pin26) and PCSCL (pin27) with the frequency
under 100KHz. The I2C address for accessing internal registers are 0x90 or 0x92 depends on the
PCADR (pin105) value.
To access the IT6605 internal registers should by the following protocol:
Read:
<I2C start>-<0x90|w >-<register index>-<I2C repeater start>-<0x90|r>-<data>(-…-<data>)-<I2C Stop>
Write:
<I2C start>-<0x90|w >-<register index>-<data>(-…-<data>)-<I2C Stop>
In the following document, the register with index will present as Reg<idx>.
Eg: Reg05 means the register with index 0x05.

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Chap 2 Initial Progress
The first step of initial IT6605 is to reset the chip.
Activate SYSRSTN (pin100) with low voltage or write reg05[4] = ‘1’, will reset the chip.
When SYSRSTN is high voltage and reg05[4] = ‘0’, IT6605 is under normal operating mode.
Initial Progress
Set HPD (HDMI Connection Pin19) to low (if possible).
Reg06 = 0x00 to power on all modules.
Reg07[3:2] = ‘11’ to turn off the termination.
Reg05 = 0xA1
Reg16 = 0x0F
Reg17 = 0x07
Reg18 = 0x07
Reg8C = 0x00 (5~8 is for initial interrupt mask setting)
Load the default value.
Configure the HDCP repeater setting
Receiver mode, reg73[7:4] = ‘0000’
Repeater mode, reg73[7:4] = ‘1000’
Delay about 500ms to make sure the HPD off enough.
Reg07[3:2] = ‘00’
Set HPD to high (if possible).
Initial Value List
reg05 = 0x20
reg08 = 0xAE
reg1D = 0x20
reg3B=0x40
reg56=0x01
reg68=0x03
reg6B=0x11
Reg6C=0x00
Reg93=0x43
Reg94=0x4F
Reg95=0x87

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Reg96=0x33
Reg97=0x0E
Reg9B=0x01
Reg1A/Reg1B/Reg1C/Reg3D[7:6] for the output video format, refer to Video Output.
Reg75/Reg76/Reg78 for the output audio format, refer to Audio Output.

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IT6605 PROGRAMMING GUIDE
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Chap 3 Video Output
IT6605 receive the HDMI or DVI video input, and output up to 30 bit TTL with numerous format, this
chapter describe how to configure the video path and video output.
Video Output Flow
IT6605 output video when it got a valid video input.
7 RXPLL_LOCK HDMI PLL locked
6 RXCK_Speed ‘1’ – Lower than 80MHz
‘0’ – Higher than 80MHz
5 RXCK_VALID ‘1’ – RX CLK Valid
4 HDMI_MODE ‘1’ – HDMI Mode
‘0’ – DVI Mode
Only reliable when SCDT on.
3 P1_PWR5V_DET (For CAT6023/IT6605)
‘1’ for HDMI input port 1 with
5V presented
2 SCDT ‘1’ – Sync Detected.
‘0’ – Otherwise.
1 VCLK_DET ‘1’ – VCLK Detect
‘0’ – Otherwise
10 Sys_state RO
0 PWR5V_DET ‘1’ - HDMI input port 0 with 5V
present.
The following steps are for getting the valid video output:
IT6605 should detect 5V in corresponding HDMI port.
IT6605 gets valid SCDT (with SCDT status bit present and no SCDT off interrupt present).
Configure the video path of IT6605.
Reset video FIFO (reg1C[1] = ‘1’→‘0’).
Turn off the video I/O and video data tri-state.

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Video Path
The video path of IT6605 are defined with video input, color space converting, and video output signal
format, as the figure:
Up/Down
Filter
HDMI
Input
Color
Space
Convert
DVI
Input
Up/Down
Filter
444 to 422
converting
422 to 444
converting
YCbCr444
YCbCr422
RGB 444
YCbCr422
Embedded
Sync
YCbCr422
Embedded
Sync
CCIR656
Force Indicate
Input Color mode
to RGB444
HDMI input contain up to 36 bits (which IT6605 supported) RGB444, YCbCr444, or YCbCr422
TMDS input with AVI infoframe indicated. DVI input supports only RGB444 video input. The input
color are indicated by reg20 or AVI infoframe, and convert to output color space by color space
converting matrix (CSC Matrix), then output by color mapping registers and output format controls
registers
1B Video_map W/R
6
5
4
3
2
1
0
chSyncpol
Swap_O16b
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
Swap_RB
0000000 Referring to the map table of Emily.
1C Video_Ctrl1 W/R 7
6
5
4
3
2
1
0
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
0x00 Default: dithering and up/dn filter is enabled
2x656CLK:
1:an 2x 656CLK is generated by PLL
0:no 2x656 CLK
The detail step are describe in following section.
Video Input Selection
When SCDT and RXCK_Valid are both present, the video input is reliable. If the HDMI_MODE bit is
‘0’, the input is an DVI input mode and default treated as 24bit RGB444 video input, otherwise the
input mode should be explained as an HDMI mode withAVI infoframe supported. If theAVI infoframe
is not presented, some testing case ask HDMI Rx to receive the input video as an RGB444 mode.

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20 CSC_CTRL W/R 7
6
5
4
3:2
1:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
0x00
Forcecolmod:
0:color mode auto adjusted according to AVI
info
1: color mode is forced by register
For DVI mode, the register setting should be reg20[4] = ‘1’to ignore the AVI Infoframe bit value, and
set reg20[3:2] = ‘00’ as RGB444 mode.
For HDMI mode, to refer the AVI infoframe color mode, reg20[4] should be ‘0’ that IT6605 will refer
the AVI infoframe PB[1][6:5] as input color mode.
The receivedAVI infoframe of IT6605 is stored in regAD ~ regBAwith 13 bytes.
AB AVI_leng RO
AC AVI_VER RO
AD AVI_DB0 RO
AE AVI_DB1 RO
AF AVI_DB2 RO
B0 AVI_DB3 RO
B1 AVI_DB4 RO
B2 AVI_DB5 RO
B3 AVI_DB6 RO
B4 AVI_DB7 RO
B5 AVI_DB8 RO
B6 AVI_DB9 RO
B7 AVI_DB10 RO
B8 AVI_DB11 RO
B9 AVI_DB12 RO
BA AVI_DB13 RO
Where Y1/Y0 are defined in CEA861/B spec, as following figure:
IT6605 will refer the input color space by regAE[6:5] or reg20[3:2] by reg20[4] selection, to decide the
decoding of input colors.
Video Output Configuration
The video output format are controlled by reg1B and reg1C, and the output selection are controlled as

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following table:
1B Video_map W/R
6
5
4
3
2
1
0
chSyncpol
Swap_O16b
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
Swap_RB
0000000 Referring to the map table of Emily.
1C Video_Ctrl1 W/R 7
6
5
4
3
2
1
0
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
0x00 Default: dithering and up/dn filter is enabled
2x656CLK:
1:an 2x 656CLK is generated by PLL
0:no 2x656 CLK
Reg1B
Video_map Reg1C Video_Ctrl1
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
chSyncpol Swap_O16b Swap_Ch422 Swap_OutRB Swap_ML Swap_Pol Swap_RB DNFreeGo SyncEmb EN_Dither EnUdFilt OutDDR 2x656CLK 656FFRst EnAVMuteRst
Sync separated
RGB444 XX X
Sync separated
YCbCr444 XX X
Sync separated
24 bit YCbCr422 X X
Sync separated
16 bit YCbCr422 √X X √√ √
Sync Embedded
16 bit YCbCr 422 √X X √√√√
Sync Embedded
8 bit YCbCr 422
(CCIR656) √X X √√√√√
√: Must set
X : Depends on the output mapping.
The above setting only decide the output signal format, the output color space are defined in the reg3D,
for determining the output:
Reg Name Type Bit Name Default value Description.
3D PG_CTRL2 W/R 7:6 OutColMod 10 ‘00’ – RGB444
‘01’ – YCbCr422
‘10’ – YCbCr444
To set RGB444, YCbCr422, or YCbCr444 also need to set reg3D[7:6] value.
Usually the output configuration is fixed in one type, thus the setting could be the initial value.
Color Space Matrix
The color space register are defined in reg21~reg35, as following: