ITE IT6605 Operating instructions
深圳市金合讯科技有限公司，0755-36853282，18664341585
IT6605 HDMI 1.4 3D Receiver
Programming Guide
Ver 1.00
Tseng, Jau-Chih
ITE Tech.
Last Update Date: 2010/12/07
深圳市金合讯科技有限公司，0755-36853282，18664341585
History
2010/08/10 – Created by Tseng, Jau-chih
2010/08/11 – Added Audio Part.
2010/12/07 – Added HDCP part.
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-i
Index
Chap 1 Introduction ..................................................................................................................1
Chap 2 Initial Progress .............................................................................................................2
Initial Progress..............................................................................................................................................2
Initial Value List ...........................................................................................................................................2
Chap 3 Video Output.................................................................................................................4
Video Output Flow .......................................................................................................................................4
Video Path ....................................................................................................................................................5
Video Input Selection ...................................................................................................................................5
Video Output Configuration .........................................................................................................................6
Color Space Matrix.......................................................................................................................................7
Video I/O and Video Data I/O Tristate..........................................................................................................8
Event of Video Process.............................................................................................................................9
Video input mode resolution.......................................................................................................................10
Video CDR Reset........................................................................................................................................10
Chap 4 Audio Output...............................................................................................................11
Audio Control Registers .............................................................................................................................11
HDMI Audio Input Status...........................................................................................................................12
Audio Output Configure.............................................................................................................................13
Default Setting .......................................................................................................................................13
I2S mode and word length......................................................................................................................13
Output LPCM Audio on I2S Channel.........................................................................................................14
Output LPCM Audio on SPDIF Channel....................................................................................................14
Output NLPCM Audio on I2S Channel......................................................................................................14
Output NLPCM Audio on SPDIF Channel.................................................................................................15
Output High Bit Rate on I2S Channel ........................................................................................................15
Output High Bit Rate on SPDIF Channel...................................................................................................15
Output LPCM/NLPCM Audio with Force Fs setting..................................................................................15
Error Handling............................................................................................................................................16
Chap 5 HDMI Infoframe.........................................................................................................17
Chap 6 HDCP Support............................................................................................................19
HDCP Repeater setting...............................................................................................................................19
HDCP registers for repeater function .....................................................................................................21
HDCP Debug Status...............................................................................................................................22
Chap 7 3D Support..................................................................................................................23
Part 2 – Software Release Code Reference.....................................................................................26
Chap 8 Introduce.....................................................................................................................26
Chap 9 Flow............................................................................................................................27
Chap 10 Data Type....................................................................................................................30
Chap 11 Sample Code Required Interface................................................................................31
Chap 12 Software Interface.......................................................................................................32
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Chap 1 Introduction
The IT6605 is a dual-port HDMI 1.4 receiver. The IT6605 with its Deep Color capability (up to 36-bit)
ensures robust reception of high-quality uncompressed video content, along with state-of-the-art
uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital
televisions and projectors.
Aside from the various video output formats supported, the IT6605 also receives and provides up to 8
channels of I2S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits,
facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is
provided to support up to compressed audio of 192kHz frame rate. SuperAudio Compact Disc (SACD)
is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports.
Each IT6605 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.2
standard so as to provide secure transmission of high-definition content. Users of the IT6605 need not
purchase any HDCP keys or ROMs.
To program IT6605 need using I2C access the PCSDA (pin26) and PCSCL (pin27) with the frequency
under 100KHz. The I2C address for accessing internal registers are 0x90 or 0x92 depends on the
PCADR (pin105) value.
To access the IT6605 internal registers should by the following protocol:
Read:
<I2C start>-<0x90|w >-<register index>-<I2C repeater start>-<0x90|r>-<data>(-…-<data>)-<I2C Stop>
Write:
<I2C start>-<0x90|w >-<register index>-<data>(-…-<data>)-<I2C Stop>
In the following document, the register with index will present as Reg<idx>.
Eg: Reg05 means the register with index 0x05.
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Chap 2 Initial Progress
The first step of initial IT6605 is to reset the chip.
Activate SYSRSTN (pin100) with low voltage or write reg05[4] = ‘1’, will reset the chip.
When SYSRSTN is high voltage and reg05[4] = ‘0’, IT6605 is under normal operating mode.
Initial Progress
Set HPD (HDMI Connection Pin19) to low (if possible).
Reg06 = 0x00 to power on all modules.
Reg07[3:2] = ‘11’ to turn off the termination.
Reg05 = 0xA1
Reg16 = 0x0F
Reg17 = 0x07
Reg18 = 0x07
Reg8C = 0x00 (5~8 is for initial interrupt mask setting)
Load the default value.
Configure the HDCP repeater setting
Receiver mode, reg73[7:4] = ‘0000’
Repeater mode, reg73[7:4] = ‘1000’
Delay about 500ms to make sure the HPD off enough.
Reg07[3:2] = ‘00’
Set HPD to high (if possible).
Initial Value List
reg05 = 0x20
reg08 = 0xAE
reg1D = 0x20
reg3B=0x40
reg56=0x01
reg68=0x03
reg6B=0x11
Reg6C=0x00
Reg93=0x43
Reg94=0x4F
Reg95=0x87
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Chap 3 Video Output
IT6605 receive the HDMI or DVI video input, and output up to 30 bit TTL with numerous format, this
chapter describe how to configure the video path and video output.
Video Output Flow
IT6605 output video when it got a valid video input.
7 RXPLL_LOCK HDMI PLL locked
6 RXCK_Speed ‘1’ – Lower than 80MHz
‘0’ – Higher than 80MHz
5 RXCK_VALID ‘1’ – RX CLK Valid
4 HDMI_MODE ‘1’ – HDMI Mode
‘0’ – DVI Mode
Only reliable when SCDT on.
3 P1_PWR5V_DET (For CAT6023/IT6605)
‘1’ for HDMI input port 1 with
5V presented
2 SCDT ‘1’ – Sync Detected.
‘0’ – Otherwise.
1 VCLK_DET ‘1’ – VCLK Detect
‘0’ – Otherwise
10 Sys_state RO
0 PWR5V_DET ‘1’ - HDMI input port 0 with 5V
present.
The following steps are for getting the valid video output:
IT6605 should detect 5V in corresponding HDMI port.
IT6605 gets valid SCDT (with SCDT status bit present and no SCDT off interrupt present).
Configure the video path of IT6605.
Reset video FIFO (reg1C[1] = ‘1’→‘0’).
Turn off the video I/O and video data tri-state.
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Video Path
The video path of IT6605 are defined with video input, color space converting, and video output signal
format, as the figure:
Up/Down
Filter
HDMI
Input
Color
Space
Convert
DVI
Input
Up/Down
Filter
444 to 422
converting
422 to 444
converting
YCbCr444
YCbCr422
RGB 444
YCbCr422
Embedded
Sync
YCbCr422
Embedded
Sync
CCIR656
Force Indicate
Input Color mode
to RGB444
HDMI input contain up to 36 bits (which IT6605 supported) RGB444, YCbCr444, or YCbCr422
TMDS input with AVI infoframe indicated. DVI input supports only RGB444 video input. The input
color are indicated by reg20 or AVI infoframe, and convert to output color space by color space
converting matrix (CSC Matrix), then output by color mapping registers and output format controls
registers
1B Video_map W/R
6
5
4
3
2
1
0
chSyncpol
Swap_O16b
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
Swap_RB
0000000 Referring to the map table of Emily.
1C Video_Ctrl1 W/R 7
6
5
4
3
2
1
0
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
0x00 Default: dithering and up/dn filter is enabled
2x656CLK:
1:an 2x 656CLK is generated by PLL
0:no 2x656 CLK
The detail step are describe in following section.
Video Input Selection
When SCDT and RXCK_Valid are both present, the video input is reliable. If the HDMI_MODE bit is
‘0’, the input is an DVI input mode and default treated as 24bit RGB444 video input, otherwise the
input mode should be explained as an HDMI mode withAVI infoframe supported. If theAVI infoframe
is not presented, some testing case ask HDMI Rx to receive the input video as an RGB444 mode.
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20 CSC_CTRL W/R 7
6
5
4
3:2
1:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
0x00
Forcecolmod:
0:color mode auto adjusted according to AVI
info
1: color mode is forced by register
For DVI mode, the register setting should be reg20[4] = ‘1’to ignore the AVI Infoframe bit value, and
set reg20[3:2] = ‘00’ as RGB444 mode.
For HDMI mode, to refer the AVI infoframe color mode, reg20[4] should be ‘0’ that IT6605 will refer
the AVI infoframe PB[1][6:5] as input color mode.
The receivedAVI infoframe of IT6605 is stored in regAD ~ regBAwith 13 bytes.
AB AVI_leng RO
AC AVI_VER RO
AD AVI_DB0 RO
AE AVI_DB1 RO
AF AVI_DB2 RO
B0 AVI_DB3 RO
B1 AVI_DB4 RO
B2 AVI_DB5 RO
B3 AVI_DB6 RO
B4 AVI_DB7 RO
B5 AVI_DB8 RO
B6 AVI_DB9 RO
B7 AVI_DB10 RO
B8 AVI_DB11 RO
B9 AVI_DB12 RO
BA AVI_DB13 RO
Where Y1/Y0 are defined in CEA861/B spec, as following figure:
IT6605 will refer the input color space by regAE[6:5] or reg20[3:2] by reg20[4] selection, to decide the
decoding of input colors.
Video Output Configuration
The video output format are controlled by reg1B and reg1C, and the output selection are controlled as
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following table:
1B Video_map W/R
6
5
4
3
2
1
0
chSyncpol
Swap_O16b
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
Swap_RB
0000000 Referring to the map table of Emily.
1C Video_Ctrl1 W/R 7
6
5
4
3
2
1
0
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
0x00 Default: dithering and up/dn filter is enabled
2x656CLK:
1:an 2x 656CLK is generated by PLL
0:no 2x656 CLK
Reg1B
Video_map Reg1C
Video_Ctrl1
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
chSyncpol
Swap_O16b
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
Swap_RB
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
Sync separated
RGB444 XX X
Sync separated
YCbCr444 XX X
Sync separated
24 bit YCbCr422 X X
Sync separated
16 bit YCbCr422 √X X √√ √
Sync Embedded
16 bit YCbCr 422 √X X √√√√
Sync Embedded
8 bit YCbCr 422
(CCIR656) √X X √√√√√
√: Must set
X : Depends on the output mapping.
The above setting only decide the output signal format, the output color space are defined in the reg3D,
for determining the output:
Reg Name Type Bit Name Default value Description.
3D PG_CTRL2 W/R 7:6 OutColMod 10 ‘00’ – RGB444
‘01’ – YCbCr422
‘10’ – YCbCr444
To set RGB444, YCbCr422, or YCbCr444 also need to set reg3D[7:6] value.
Usually the output configuration is fixed in one type, thus the setting could be the initial value.
Color Space Matrix
The color space register are defined in reg21~reg35, as following:
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20 CSC_CTRL W/R 7
6
5
4
3:2
1:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
0x00
Forcecolmod:
0:color mode auto adjusted according to AVI info
1: color mode is forced by register
21 CSC_YOFF W/R 7:0 0x10
22 CSC_COFF W/R 7:0 0x80
23 CSC_RGBOFF W/R 7:0 0x00
24 CSC_MTX11_L W/R 7:0 0xb2
25 CSC_MTX11_H W/R 5:0 000100
26 CSC_MTX12_L W/R 7:0 0x64
27 CSC_MTX12_H W/R 5:0 000010
28 CSC_MTX13_L W/R 7:0 0xE9
29 CSC_MTX13_H W/R 5:0 000000
2A CSC_MTX21_L W/R 7:0 0x93
2B CSC_MTX21_H W/R 5:0 011100
2C CSC_MTX22_L W/R 7:0 0x16
2D CSC_MTX22_H W/R 5:0 000100
2E CSC_MTX23_L W/R 7:0 0x56
2F CSC_MTX23_H W/R 5:0 011111
30 CSC_MTX31_L W/R 7:0 0x49
31 CSC_MTX31_H W/R 5:0 011101
32 CSC_MTX32_L W/R 7:0 0x9f
33 CSC_MTX32_H W/R 5:0 011110
34 CSC_MTX33_L W/R 7:0 0x16
35 CSC_MTX33_H W/R 5:0 000100
And the value of color space converting setting are as following table:
RGB to YUV YUV to RGBColor space converting table RGB to YUV
601 RGB to YUV 709 YUV to RGB
601 YUV to RGB
709
reg 16~ 235 0 ~ 255 16~ 235 0 ~ 255 16~ 235 0 ~ 255 16~ 235 0 ~ 255
Reg_CSCSel[1:0] 20[1:0] 10 10 10 10 11 11 11 11
Reg_YoffSet[7:0] reg21 0x00 0x10 0x00 0x10 0x00 0x10 0x00 0x10
Reg_CoffSet[7:0] reg22 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80
Reg_RGBOffSet[7:0] reg23 0x00 0x10 0x00 0x10 0x00 0x10 0x00 0x10
Reg_Matrix11V[13:0] reg24 0xB2 0x09 0xB8 0xE5 0x00 0x4F 0x00 0x4F
reg25 0x04 0x04 0x05 0x04 0x08 0x09 0x08 0x09
Reg_Matrix12V[13:0] reg26 0x64 0x0E 0xB4 0x78 0x6A 0x81 0x53 0xBA
reg27 0x02 0x02 0x01 0x01 0x3A 0x39 0x3C 0x3B
Reg_Matrix13V[13:0] reg28 0xE9 0xC8 0x93 0x81 0x4F 0xDF 0x89 0x4B
reg29 0x00 0x00 0x00 0x00 0x3D 0x3C 0x3E 0x3E
Reg_Matrix21V[13:0] reg2A 0x93 0x0E 0x49 0xCE 0x00 0x4F 0x00 0x4F
reg2B 0x3C 0x3D 0x3C 0x3C 0x08 0x09 0x08 0x09
Reg_Matrix22V[13:0] reg2C 0x18 0x84 0x18 0x84 0xF7 0xC2 0x51 0x56
reg2D 0x04 0x03 0x04 0x03 0x0A 0x0C 0x0C 0x0E
Reg_Matrix23V[13:0] reg2E 0x56 0x6E 0x9F 0xAE 0x00 0x00 0x00 0x00
reg2F 0x3F 0x3F 0x3F 0x3F 0x00 0x00 0x00 0x00
Reg_Matrix31V[13:0] reg30 0x49 0xAC 0xD9 0x49 0x00 0x4F 0x00 0x4F
reg31 0x3D 0x3D 0x3C 0x3D 0x08 0x09 0x08 0x09
Reg_Matrix32V[13:0] reg32 0x9F 0xD0 0x10 0x33 0x00 0x00 0x00 0x00
reg33 0x3E 0x3E 0x3F 0x3F 0x00 0x00 0x00 0x00
Reg_Matrix33V[13:0] reg34 0x18 0x84 0x18 0x84 0xDB 0x1E 0x87 0xE7
reg35 0x04 0x03 0x04 0x03 0x0D 0x10 0x0E 0x10
Video I/O and Video Data I/O Tristate
The video output I/O and video data I/O have tristate control to disable the video output. Whenever the
AV mute detected, video output should be disabled.
IT6605 implement the automatic mute mechanism, as the following registers:
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20 CSC_CTRL W/R 7
6
5
4
3:2
1:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
0x00
Forcecolmod:
0:color mode auto adjusted according to AVI info
1: color mode is forced by register
89 TriState_Ctrl W/R 7
6
5
4
3:0
DisVAutomute
TriVdIO
Tri_vdo
Tri_SPDIF
Tri_I2S
0x80 Would be removed if not necessary
If reg89[6] = ‘1’, all video clock, H/V sync and data are tri-stated. When reg89[7] = ‘1’, AVMute will
not affect the video output, otherwise whenAVMute = ‘1’, the video output is tri-stated automatically.
If reg89[7] = ‘1’, and AVMute (reg65[2] represent the AVMute status transmit by HDMI general packet)
switched from ‘1’to ‘0’, the video enable should following the procedure:
reg1B[1] = ‘1’
reg1B[1] = ‘0’
reg89[6] = ‘1’
reg89[6] = ‘0’
reg20[7] = ‘1’
reg20[7] = ‘0’
Then the video output will not be tri-stated and the output is available.
Event of Video Process
There are several flags about video status, defined in reg15(interrupt status 0) and reg8B(interrupt
status 3), as following:
Reg
Offset Reg_Name W/R Bits Status Description
0x13 Interrupt0 RO 5
4
3
2
1
0
VidMode_Chg
HDMIMode_Chg
SCDTOFF
SCDTON
Pwr5VOff
Pwr5Von
Video mode change
HDMI/DVI mode swap change
Video stable is off
Video stable is on
Selected port 5V is off
Selected port 5V is on
0x14 Interrupt
Mask 0 R/W 5
4
3
2
1
0
VidMode_Chg
HDMIMode_Chg
SCDTOFF
SCDTON
Pwr5VOff
Pwr5Von
1 : enable the int signal by the event.
0x8B Interrupt3 RO 7
6
5
4
3
2
1
0
CLKCHG_DET
rxckon_Det
HDCPoff_det
Symerr_det
CD_det
Genpkt_det
ISRC2_Det
ISRC1_Det
Rx clock change detect Int
Rx clock on detect Int
0x8C Interrupt
mask 3 R/W 7
6
5
4
3
2
1
0
CLKCHG_DET
HDCPoff_det_mask
rxckon_Det_mask
Symerr_det
CD_det
Genpkt_det
ISRC2_Det
ISRC1_Det
1 : enable the int signal by the event.
When the bit in reg13 or reg8B[7:6] raised, set reg19[0] = ‘1’→‘0’ will clear it include the INT signal.
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Above event can be referred as video input status change status, the status in reg10 should be referred
together when handle the video mode interrupt.
Video input mode resolution
IT6605 provided the input video status registers including the video mode information, the information
are located in reg58~reg65, as the following table:
0x58 Vid_mode RO 3
2
1
0
PxVideoStable
vidfield
vidinterlacemode
VidModeChg
Indicate if video signal is stable
Video field number in interlaced mode
Indicate video is in interlaced mode
Indicate if a video mode change occurs
0x59 Vid_HTotal_L RO 7:0 The total pixel count of a line [7:0]
0x5A Vid_HTotal_H RO 7:4
3:0 Vid_HAct[11:8]
Vid_Htotal[11:8] The active pixel count of a line[11:8]
The total pixel count of a line [11:8]
0x5B Vid_HAct_L RO 7:4 Vid_HAct[7:0] The active pixel count of a line[7:0]
0x5C Vid_Hsync_Wid_L RO 7:4 Vid_Hsync_Wid[7:0] The width of Hsync [7:0]
0x5D Vid_HSync_Wid_H RO 7:4
3:0 Vid_H_Ft_Porch[11:8]
Vid_Hsync_Wid[11:8] The width of Hsync front porch [11:8]
The width of Hsync [11:8]
0x5E Vid_H_Ft_Porch_L RO 7:0 Vid_H_Ft_Porch[7:0] The width of Hsync front porch [7:0]
0x5F Vid_VTotal_L RO 7:0 Vid_VTotal[7:0] The total line count of a field [7:0]
0x60 Vid_VTotal_H RO 7:4
3:0 Vid_Vact[10:8]
Vid_Vtotal[10:8] The active line count of a field [10:8]
The total line count of a field [10:8]
0x61 Vid_Vact_L RO 7:0 Vid_Vact[7:0] The active line count of a field [7:0]
0x62 Vid_Vsync2DE RO 7:0 Video sync to DE[7:0] The width of vsync back porch
0x63 Vid_V_Ft_Porch RO 7:0 Vid_V_Ft_Porch[7:0] The width of vsync front porch
0x64 Vid_pixel_CNT RO 7:0 Count of crystal clock on each 128 pixels
0x65 Vid_input_st RO
7:4
2
1
0
Pix_rep
Avmute
Vsync_in_po
Hsync_in_po
Video input status
0000 : no repetition
0001: pixel sent 2 times
0011: pixel sent 4 times
HDMI is in Avmute state
Vsync input polarity
Hsync input polarity
When the video input is valid, the firmware can read for the video mode information.
Video CDR Reset
Before enable the video output, the software need to read reg85 for clearing video error count, and wait
more one millisecond for collecting the video error count in reg9A. Then read reg9Ato check if it is
0xFF.
If reg9A is 0xFF, then set reg05[7] = ‘1’-> ‘0’, then wait the video stable again.
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Chap 4 Audio Output
HDMI audio exists in the packages of data island, appended in the blank of video data. Therefore,
audio could only exist with video playback. If the video is not ready, there is no audio.
IT6605 support LCPM audio from 32KHz to 192KHz, 2 channels to 8 channels, compress audio with
data rate up to 32bits * 192KHz, High bit rate audio such as TrueHD or DTS-HD audio, and one-bit
audio (DSD).
Audio Control Registers
Following table lists the control registers of audio used on IT6605.
reg Name typ
e bit bit Name Description Default
7 Ws_sel 1:invert channel A and channel B select 0
6:2 I2S_Width I2S word length, only effective in right justified
mode;
Maximum value is 24 means of 24 bits, value is the
length of word length
11000
0x75 I2S_Ctrl W/
R
1:0 I2S_Mode I2S output mode:
00:32 bit I2S left justified mode, 1T delay
01:32 bit I2S right justified mode
10:32 bit I2S left justified mode, 0T delay
11:undefined
00
7:6 I2S_Ch3Sel I2S channel 6 and channel 7 map:
00: map to HDMI channel 0 and channel 1
01: map to HDMI channel 2 and channel 3
10: map to HDMI channel 4 and channel 5
11: map to HDMI channel 6 and channel 7
11
5:4 I2S_Ch2Sel I2S channel 4 and channel 5 map:
00: map to HDMI channel 0 and channel 1
01: map to HDMI channel 2 and channel 3
10: map to HDMI channel 4 and channel 5
11: map to HDMI channel 6 and channel 7
10
3:2 I2S_Ch1Sel I2S channel 2 and channel 3 map:
00: map to HDMI channel 0 and channel 1
01: map to HDMI channel 2 and channel 3
10: map to HDMI channel 4 and channel 5
11: map to HDMI channel 6 and channel 7
01
0x76 I2S_Map W/
R
1:0 I2S_Ch0Sel I2S channel 0 and channel 1 map:
00: map to HDMI channel 0 and channel 1
01: map to HDMI channel 2 and channel 3
10: map to HDMI channel 4 and channel 5
11: map to HDMI channel 6 and channel 7
00
7 Audck_BBen Enable NLPCM output from SPDIF
6 Force_FS Force Audio FS mode
5 Reserved
4 Aud_info_force Force Audio setting from Aud info frame
3 Avmute_value Avmute value when software Avmute is
enabledSoftware forced-Avmute mode
2 Force_avmute Software forced-Avmute mode
1
0x77 Audio_Ctrl W/
R
0
0x20
7 OSC_En 1:use crystal clock input as audio PLL reference
0:use pixel clock as audio PLL reference 1
6 OSCSel 1:selected when crystal is of 27MHz 1
4 Force_CTS Software force to set CTS value 0
3 Force_CTSMODE use CTS for audio FIFO adjustment 0
0x78 MCLK_Ctrl W/
R
2:0 Mclksel
Mclk output clock multiple number
000:128FS ;001:256FS;
010:384FS ;011:512FS;
100:640FS ;101:768FS;
110:894FS ;111:1024FS;
001
0x7E FS_SET W/
R 3:0 FS_SET Software set sampling frequency
0000:44.1KHz; 0010:48KHz;
0011:32 KHz; 1000:88.2KHz;
0010
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1010:96 KHz; 1100:176.4KHz; 1110:192KHz
0x7F N_Rcv1 RO 7:0 N_DEC[7:0] Audio N parameter decoder value [7:0]
0x80 N_Rcv2 RO 7:0 N_DEC[15:8] Audio N parameter decoder value [15:8]
0x81 N_Rcv3 RO 7:4
3:0 CTS_DEC[3:0]
N_DEC[19:16] Audio CTS parameter decoder value [3:0]
Audio N parameter decoder value [19:6]
0x82 CTS_Rcv2 RO 7:0 CTS_DEC[11:4] Audio CTS parameter decoder value [11:4]
0x83 CTS_Rcv3 RO 7:0 CTS_DEC[19:12] Audio CTS parameter decoder value [19:12]
7:4
GCP_CD
Color depth decoder value in GCP
0: default (24bits)
4: 24bits
5: 30bits
6:36bits
7:48bits
0x84 CD
FS
RO
3:0 F_DEC Audio FS(sample Freq.) decoder value
0000:44.1KHz; 0010:48KHz;
0011:32 KHz; 1000:88.2KHz;
1010:96 KHz; 1100:176.4KHz; 1110:192KHz
0x87 HWMute_Ctrl W/
R 6
5
4
3
HWForceMute
HWAudFFMuteClr
HWMuteClr
HWMuteEn
HWForceMute:
0: mute control by channel status
1: mute anyway
FIFO mute clear
Clear H/W mute
H/W Mute enable
0001000
0x89 TriState_Ctrl W/
R 7
6
5
4
3
2
1
0
DisVAutomute
Tri_VDIO
Tri_VIO
Tri_SPDIF
Tri_I2S3
Tri_I2S2
Tri_I2S1
Tri_I2S0
Video output Auto Mute Disable
tristate video Data output buffer
tristate video Control output buffer
tristate Audio SPDIF output buffer
tristate Audio I2S3 output buffer
tristate Audio I2S2 output buffer
tristate Audio I2S1 output buffer
tristate Audio I2S0 output buffer
0x80
0x8A Audio_chanSt RO
7
6
5
4
3
2
1
0
Audio_on
HBRAudio
DSDAudio
Audio_layout
Audio_src3_valid
Audio_src2_valid
Audio_src1_valid
Audio_src0_valid
Audio received status
Audio is ON
Audio type is High Bit rate
Audio type is DSD
Audio layout is 1 or 0
HDMI Audio source 3 valid Flag
HDMI Audio source 2 valid Flag
HDMI Audio source 1 valid Flag
HDMI Audio source 0 valid Flag
0x8E Pkt_type_H
Ori_sampF RO 3:0
7:4 Received packet type high bits
Original sampling frequency
HDMI Audio Input Status
IT6605 shows the input audio status in reg8A. When reg8A[7] = ‘1’, it means IT6605 received audio
sample packages, HBR audio packages, or DSD audio packages. reg8A[6] present if IT6605 got a
HBR audio input. reg8A[5] represent if IT6605 got a DSD audio input.
Audio Present
reg8A[7]
HBR reg8A[6]
DSD reg8A[5]
NLPCM
reg9C[1]
HD audio
(HBR) 1 1 0 1
One-bit audio
(DSD) 1 0 1 x
Compressed audio
(NLPCM < 192KHz) 1 0 0 1
LPCM audio 1 0 0 0
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The input audio channel status are responding in the reg84,reg8E,reg9C~reg9F, as following table:
reg Name type bit bit Name Description Default
0x84 FS 3:0 F_DEC Audio FS(sample Freq.) decoder value
0000:44.1KHz; 0010:48KHz;
0011:32 KHz; 1000:88.2KHz;
1010:96 KHz; 1100:176.4KHz; 1110:192KHz
0x8E Ori_sampF RO 7:4 Audio Channel Status[39:36]
Original sampling frequency
1111:44.0KHz; 1101:48KHz;
1100:32 KHz; 0111:88.2KHz;
0101:96 KHz; 0011:176.4KHz; 0001:192KHz
9C Audio_Ch_
status0 RO 7:6 Audio Channel status
decoder value [7:0] ‘00’ – mode 0 for following byte.
Other – reserved.
5:3 D[1] = 0
‘000’ – 2 channel without pre-emphasis
‘001’ – 2 channel with 50μs/15μs pre-emphasis.
‘010’ – reserved
‘011’ – reserved
D[1] = 1
‘000’ – Default state for other application than linear
PCM.
2 0 - Software for copyright asserted.
1 - Software for no copyright is asserted.
1 0 – Audio word world represents LPCM samples.
1 – Audio word used for other purpose
0 reserved.
9D Audio_Ch_
status1 RO Category code. Audio Channel status decoder value [15:8] 0x00
9E Audio_Ch_
status2 RO 7:4 Channel Number
Audio Channel status decoder value [23:16]
“0000” – Do not take into account.
“0001” – 1
3:0 Source Number
‘0000’ – do not take into account
‘0001’ – left channel for stereo format
‘0010 – right channel for stereo format.
9F Audio_Ch_
status3 RO 7:4 Sample Word Length Audio Channel status decoder value [35:32]
3:2 reserved Audio Channel status decoder value [31:30]
1:0 Clock accurance Audio Channel status decoder value [28:29]
Software can judge the audio information by the register value.
Audio Output Configure
Default Setting
Reg75 – depends on the DSP configuration.
Reg76 – 0xE4.
Reg77[7] – ‘1’ for accepting the NLPCM on I2S.
Reg78 = 0xC1
Reg7E[6:4] = ‘111’.
Reg88[4] = ‘0’for output HBR audio on I2S0~I2S3, ‘1’for output to SPDIF.
I2S mode and word length
If chose the I2S as output audio, IT6605 provide three types of I2S output format:
32bit I2S output with 1T delay, MSB fist, Left Justify.
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32bit I2S output with MSB fist, Right Justify.
32bit I2S output with 0T delay, MSB fist, Left Justify.
The word length of each sample are controlled by reg75[6:2] with actual value from 16 to 24.
And reg75[7] is control when WS is ‘0’which channel is carried.
Output LPCM Audio on I2S Channel
When detected the input audio is an LPCM audio, and wish output it on I2S channel, use the
procedure:
Reg05[2] = ’1’→’0’
Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
reg89[3:0] = ’0000’ (depends on your I2S source number)
Output LPCM Audio on SPDIF Channel
Reg05[2] = ’1’→’0’
Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
reg89[4] = ’0’
Output NLPCM Audio on I2S Channel
Reg77[7] = ’1’
Reg05[2] = ’1’→’0’
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Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
reg89[0] = ’0’ (depends on your I2S source number)
Output NLPCM Audio on SPDIF Channel
Reg05[2] = ’1’→’0’
Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
reg89[4] = ’0’ (depends on your I2S source number)
Output High Bit Rate on I2S Channel
Reg88[4] = ’0’
Reg78[2:0] = ’000’
Reg05[2] = ’1’→’0’
Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
reg89[3:0] = ’0000’
Output High Bit Rate on SPDIF Channel
Reg88[4] = ’1’
Reg78[2:0] = ’000’
Reg05[2] = ’1’→’0’
Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
reg89[3:0] = ’0000’ (depends on your I2S source number)
Output LPCM/NLPCM Audio with Force Fs setting
For some audio input contains wrong information thus the IT6605 could not detect the correct sample
frequency, you could use “force Fs Setting” to fix the audio problem.
Reg77[6] = ’1’
Reg87[4][3] = ‘1’‘1’ →‘0’‘1’
Reg05[2] = ’1’→’0’
Reg7E[2:0] ←Given fixed frequency. (write at first time)
Reg7E[2:0] ←Given fixed frequency. (write at 2nd time)
Reg7E[2:0] ←Given fixed frequency. (write at 3rd time)
Reg7E[2:0] ←Given fixed frequency. (write at 4th time)
Clear the audio error interrupt status.
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Error Handling
IT6605 provide two interrupt flag to indicate the audio error:
Reg Reg_Name W/R Bits Status Description
0x15 Interrupt2 RO 4
3 AutoAudMute
AudFIFOErr Audio Auto Mute Flag
Audio FIFO error Flag
When detect the interrupt by these two flag while the video on state, reconfigure the audio output
procedure described above, then it could be clear.
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Chap 5 HDMI Infoframe
IT6605 received the HDMI package in the specified registers. There are interrupt flags for the
infoframe arrival, defined in reg14 interrupt status 1:
Reg Reg_Name Bits Status Description
0x14 Interrupt1 RO 7
6
5
4
3
2
1
0
PktLeftMute
NewAudioPkt_Det
NewACPPkt_Det
NewSPDPkt_Det
NewMPEGPkt_Det
NewAVIPkt_Det
NoAVI_Rcv
PktSetMute
Left Mute Packet is received
New Audio Packet detect
New ACP Packet detect
New SPD Packet detect
New MPEG Packet detect
New AVI Packet detect
No AVI Packet is received
Set Mute Packet is received
When “new” infoframe or HDMI package arrived, the flags defined above will be raise. If there is no
AVI infoframe arrived under HDMI mode, the NoAVI_Rcv flag will be raise. The interrupt mask 1
register (reg17) defined the mask with same field.
The getting infoframes are put in the following registers:
Reg
Offset Reg_Name W/R Bits Status Description Default
0xA8 Pkt_rec_typeL W/R 7:0 Decide which kind of packet to be fully recorded on
General PKT registers. 0x83
0xA9 SRC_ver RO SPD infoFrame Version
0xAA SRC_pb25 RO SPD infoFrame Data Byte 25
0xAB AVI_leng RO AVI infoFrame Length
0xAC AVI_VER RO AVI infoFrame Version
0xAD AVI_DB0 RO AVI infoFrame Data Byte 0
0xAE AVI_DB1 RO AVI infoFrame Data Byte 1
0xAF AVI_DB2 RO AVI infoFrame Data Byte 2
0xB0 AVI_DB3 RO AVI infoFrame Data Byte 3
0xB1 AVI_DB4 RO AVI infoFrame Data Byte 4
0xB2 AVI_DB5 RO AVI infoFrame Data Byte 5
0xB3 AVI_DB6 RO AVI infoFrame Data Byte 6
0xB4 AVI_DB7 RO AVI infoFrame Data Byte 7
0xB5 AVI_DB8 RO AVI infoFrame Data Byte 8
0xB6 AVI_DB9 RO AVI infoFrame Data Byte 9
0xB7 AVI_DB10 RO AVI infoFrame Data Byte 10
0xB8 AVI_DB11 RO AVI infoFrame Data Byte 11
0xB9 AVI_DB12 RO AVI infoFrame Data Byte 12
0xBA AVI_DB13 RO AVI infoFrame Data Byte 13
0xBB AVI_DB14 RO AVI infoFrame Data Byte 14
0xBC AVI_DB15 RO AVI infoFrame Data Byte 15
0xDC Audio_Ver RO Audio infoFrame Version
0xDD Audio_DB0 RO Audio infoFrame Data Byte 0
0xDE Audio_DB1 RO Audio infoFrame Data Byte 1
0xDF Audio_DB2 RO Audio infoFrame Data Byte 2
0xE0 Audio_DB3 RO Audio infoFrame Data Byte 3
0xE1 Audio_DB4 RO Audio infoFrame Data Byte 4
0xE2 Audio_DB5 RO Audio infoFrame Data Byte 5
0xE3 Audio_leng RO Audio infoFrame Length
0xE4 MPEG_Ver RO MPEG infoFrame Version
0xE5 MPEG_leng RO MPEG infoFrame Length
0xE6 MPEG_DB0 RO MPEG infoFrame Data Byte 0
0xE7 MPEG_DB1 RO MPEG infoFrame Data Byte 1
0xE8 MPEG_DB2 RO MPEG infoFrame Data Byte 2
0xE9 MPEG_DB3 RO MPEG infoFrame Data Byte 3
0xEA MPEG_DB4 RO MPEG infoFrame Data Byte 4
0xEB MPEG_DB5 RO MPEG infoFrame Data Byte 5
0xEC ACP_HB0 RO ACP packet Header Byte 0
0xED ACP_HB1 RO ACP packet Header Byte 1
0xEE ACP_HB2 RO ACP packet Header Byte 2
0xEF ACP_DB0 RO ACP packet Data Byte 0
0xF0 ACP_DB1 RO ACP packet Data Byte 1
0xF1 ACP_DB2 RO ACP packet Data Byte 2
Table of contents
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