LAPIS Semiconductor ML7406 Guide

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October 1, 2020

FEXL7406DG-01
ML7406 Family LSIs
Hardware Design Manual
Issue Date: Dec. 25th 2018

ML7406 Family LSIs Hardware Design Manual
FEXL7406DG-01 i
Notes
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Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/

ML7406 Family LSIs Hardware Design Manual
FEXL7406DG-01 ii
Introduction
This hardware design manual contains hardware information that should be referenced when
designing ML7406 family devices (Hereafter ML7406). And also contains the measurement
conditions and example of measurement results of RF characteristics.
Target product：
ML7406y
y = C : Crystal Input
S : SPXO Input
T : TCXO Input
The following related manual is available and should be referenced as needed
ML7406 data sheet
All other company and products names are the trademarks or registered trademarks of the respective companies.

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FEXL7406DG-01 iii
Notation
Classification Notation Description
Numeric value 0xnn Represents a hexadecimal number.
0bnnnn Represents a binary number.
Address 0xnnnn_nnnn Represents a hexadecimal number. (indicates 0xnnnnnnnn)
Unit word, W 1 word = 32 bits
byte, B 1 byte = 8 bits
Mega, M 106
Kilo, K (uppercase) 210=1024
Kilo, k (lowercase) 103=1000
Milli, m 10-3
Micro, 10-6
Nano, n 10-9
Second, s (lowercase) Second
Terminology "H" level Signal level on the high voltage side; indicates the voltage level of
VIH and VOH as defined in electrical characteristics.
"L" level Signal level on the low voltage side; indicates the voltage level of
VIL and VOL as defined in electrical characteristics.
Register description
Read/write attribute: R indicates read-enabled; W indicates write-enabled.
MSB: Most significant bit in an 8-bit register (memory)
LSB: Least significant bit in an 8-bit register (memory)

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FEXL7406DG-01 iv
Table of Contents
Introduction ...................................................................................................................................................... ii
Notation ........................................................................................................................................................... iii
Table of Contents............................................................................................................................................. iv
1. Placing decoupling capacitors.................................................................................................................. 1
2. Clock Input................................................................................................................................................ 3
2.1. Crystal Oscillator circuit [ML7406C] .............................................................................................. 3
2.1.1. Circuit component values for crystal oscillator circuit ........................................................... 3
2.1.2. Notes on the crystal oscillator circuit configuration ............................................................... 4
2.2. TCXO circuit [ML7406T] .................................................................................................................. 5
2.3. SPXO circuit [ML7406S] .................................................................................................................. 5
3. PLL loop filter ........................................................................................................................................... 6
4. VCO ........................................................................................................................................................... 7
4.1. Adjusting component values for VCO tank ..................................................................................... 8
4.2. Note on the VCO tank circuit........................................................................................................... 9
5. RF matching component values..............................................................................................................11
5.1. Transmission matching circuit........................................................................................................11
5.2. Reception matching circuit............................................................................................................. 12
6. Antenna Switch ...................................................................................................................................... 13
7. Temperature measurement.................................................................................................................... 13
8. Notes on selecting external parts (recommendations) ......................................................................... 14
9. Notes on board artworks (recommendations) ....................................................................................... 14
9.1. GND ................................................................................................................................................. 14
10. Application circuit............................................................................................................................... 15
11. Bill of Materials .................................................................................................................................. 16
Revision history.............................................................................................................................................. 18

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1. Placing decoupling capacitors
Place decoupling capacitors between each power pins and GND as shown in Figure 1.1.
Figure 1.1 Power Supply Block Diagram
REG_PA(#21)
VDD_PA(#22)
VDD_REG(#1)
Including backside GND
GND
REG_OUT(#3)
PA_OUT(#20)
VBG(#2)
PA
VDD
REG_CORE(#4)
VB_EXT(#31)
VDD_VCO(#32)
VDD_CP(#27)
VDD_RF(#25)
56Ω*[2]
Each decoupling capacitors as close to an LSI pin as possible.
PA regulator
VDDIO(#9)
1.5Vregulator
Logic circuit
1000pF
0.1µF
10µF
1000pF
0.1µF
1000pF
0.1µF
1000pF
1000pF
0.1µF
10µF
100pF
1000pF
1µF
1000pF
0.1µF
1000pF
0.1µF
0.1µF
L3*[1]
100pF
1μF
0.01μF
1μF

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*[1] The supply voltage for the PA_OUT pin (#20) should be provided the DC bias through the inductor
(L3).
*[2] The noise coming from the VDD_VCO pin (#32) will increases the phase noise level. The Adjacent
Channel Power Ratio (ACPR) and spurious performance may be improved by adjusting a resister value
(56Ω).
Notes the following when placing decoupling capacitors:
1. The VDD and GND traces should be wider than other signal line traces to reduce the resister element.
2. Decoupling capacitor should be placed as close to an LSI pin as possible.
3. The smaller capacitor should be closer to an LSI pin than other capacitors.
4. VDDIO (#9), VDD_PA (#22), VDD_REG (#1) pins connected to the VDD share the trace. and placing
a 10μF decoupling capacitor. A 10uF capacitor is recommended tantalum capacitor because it has low
leak current. If it doesn’t care leak current, any kind capacitor could be used.
5. A 10 µF decoupling capacitor should be placed to both the REG_OUT (#3) pin to stabilize 1.5V
regulator.
6. It is recommended to place a 1000 pF multilayer ceramic capacitor in parallel with a 10 µF tantalum
capacitor to both the REG_OUT (#3) pin
7. The VBG (#2) pin is a reference voltage output pin of band-gap reference circuit. Placing a 0.1μF
multilayer ceramic capacitor to the VBG (#2) pin to reduce the noise from the band-gap reference
circuit.
8. In general, ceramic capacitors have specific temperature and voltage characteristics. Select the best
capacitor for the operating voltage and temperature of your specific application. It is recommended that
decoupling capacitor use a CH (temperature compensating) or a B (high dielectric constant type) of
temperature characteristics.
9. ML7406 support low power consumption mode (SLEEP MODE). In this mode, the consumption current
of the LSI is around 0.9μA. Therefore the leak current of decoupling capacitors will impact on the
consumption current of your specific circuit. It is recommended to select the low leak current capacitor
to develop low consumption circuit board and system.

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2. Clock Input
2.1. Crystal Oscillator circuit [ML7406C]
Figure 2.1 shows a configuration example of the crystal oscillator circuit.
Capacitors should be connected to XIN (#5) and XOUT (#6) pins to stabilize 26MHz crystal oscillator circuit. To
determine the component values, the oscillator circuit evaluation on your designing board is required, since the
stray capacitor of the board will be influenced.
Amplitude level, oscillation margin, frequency accuracy and oscillator circuit start-up time should be considered
and evaluated.
Figure 2.1 Crystal Oscillator circuit configurations
2.1.1. Circuit component values for crystal oscillator circuit
It is recommended to ask your oscillator manufacturer to evaluate the matching component values on the
assembled board. The following tables show the matching component values with LAPIS Semiconductor RF
board as reference.
Table 2.1.1 Representative matching component values
Oscillator
Type
Frequency
(MHz)
Equivalent
series resister
max[Ω]
Load
capacitor
(pF)
Component
Values
Operating Condition
C1(pF)
C2(pF)
Power supply
voltage range
VDDIO(V)
Temperature
range
( C)
FCX-05
26
100
7
2.7
2.7
1.8 to 3.6
-40 to +85
NX2520SA
26
60
8
1
1
1.8 to 3.6
-40 to +85
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.
XIN(#５)
C1
X’tal
XOUT(#６)
C2

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2.1.2. Notes on the crystal oscillator circuit configuration
Note the following when designing the crystal oscillator circuit.
1. The capacitors value of C1 and C2 depends on the crystal oscillator specification.
2. C1 and C2 should be placed as close as possible to the XIN (#5) and the XOUT (#6) pins to suppress
parasitic LCR and stabilize the oscillator.
3. The 26 MHz reference clock should keep accuracy within ±20ppm under all condition including
temperature variations, power supply voltage variation and aging changes.
4. Do not place the crystal oscillator circuit across other signal lines.
5. Do not trace signal lines where large current flow around the crystal oscillator circuit.
6. For the oscillator circuit capacitors, make sure the potential of the ground points is always equal to that
of the GND. Do not connect the capacitors to GNDs where large current flow.
7. Do not take oscillation signals from the oscillator circuit.
8. Oscillation frequency is changed by variation value of ESR (Equivalent Series Resistance) in crystal.
Oscillation frequency can be adjusted by [OSC_ADJ2] register (B0 0x63).

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2.2. TCXO circuit [ML7406T]
Please use a TCXO that satisfy the following specification.
Output load: 10kΩ//10pF
Output level: 0.8Vpp to 1.5Vpp
Frequency accuracy: below ±20ppm
The ML7406T has integrated bias circuit and the DC bias is applied to the TCXO (#6) pin. A 1000pF capacitor
should be placed on the TCXO line as following.
In ML7406T, #5 pins is N.C. pin, then it should be open.
Figure 2.2.1 External oscillator circuit (TCXO) configurations
2.3. SPXO circuit [ML7406S]
Please use a SPXO that satisfy the following specification.
Output load: 15pF
Output level: CMOS Level (digital I/O input)
Frequency accuracy: following application specification
No need coupling capacitor as following.
In ML7406S, #5 pins is N.C. pin, then it should be open.
Figure 2.3.1 External oscillator circuit (SPXO) configurations
TCXO
26MHz
1000pF
TCXO(#6)
VB
N.C.(#5)
SPXO
26MHz
SPXO(#6)
N.C.(#5)

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3. PLL loop filter
Figure 3.1 shows a configuration example of the PLL loop filter circuit. To satisfy phase noise feature, the
recommend values are showed in Figure 4.1.
It is recommended to select the components with flat temperature characteristics and temperature coefficient is
managed. Capacitors, do not select high dielectric type and semiconductor type, so there is low accuracy and
non-linear temperature characteristics.
In order to prevent noise, the loop filter components (C2, R3 and C3) should be placed as close to the LP (#26)
pin as possible, recommends within 5 mm. Do not trace signal lines that become a noise source like a reference
clock line, around the loop filter.
Figure 3.1 PLL loop filter circuit configurations
LP(#26)
C2
10pF
R3
13kΩ
C3
3300pF

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4. VCO
Figure 4.1 shows a configuration example of the VCO tank circuit. VCO oscillator frequency calculated as
follows:
LC
F
 2
1

The L in the above equation will be the sum of the inductor L1, the line inductance of the PCB and the internal
inductance of the ML7406. And the C will be the sum of the capacitor C1, the line capacitor of the PCB and the
internal capacitor (including calibration capacitor) of the ML7406.
Figure 4.1 VCO tank circuit configurations
IND1(#28)
Variable capacitor
Amplifier
C1
L1
IND2(#30)
Variable capacitor
for calibration

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4.1. Adjusting component values for VCO tank
Adjustment procedure of the VCO tank components is as below:
1. Execute the VCO calibration with the following condition.
Set the frequency to the center of usingfrequency range.
In the idle state with the room temperature.
2. Adjust the L1 and C1 values so that the calibration value obtained by [VCO_CAL] register (B0 0x6E)
becomes close to “64” (decimal).
Reducing one or both L1 and C1 values if decreasing the VCO_CAL value.
Increasing one or both L1 and C1 values if increasing the VCO_CAL value.
[Note] In order to lock the PLL, the VCO_CAL value is required to be in the range from 1 to 126 (decimal) under
all conditions.
The frequency range that PLL can lock, VCO phase noise and the temperature feature depend on the L1, C1
values. It is recommended to evaluate these characteristics when L1 and C1 values is fixed.
Table 4.1.1 Representative component values for operating frequency
868MHz band
L1
4.7nH
C1
4.3pF
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.

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4.2. Note on the VCO tank circuit
Note the following when designing the VCO tank circuit.
1. In order to stable VCO oscillation, the VCO tank components (L1 and C1) should be placed as close to the
IND1 (#28) and IND2 (#30) pins as possible, recommends within 2 mm. Since the line inductance and
capacitance of PCB will effect to the oscillation frequency.
2. ML7406 maximum output power is more than 20mW. As shown in the Figure 4.2.1, high output will flow
on the transmission path from PA_OUT (#20) pin. If this output affects on VCO tank circuit, it may cause
the PLL unlock. In Rx, signal radiated from VCO tank, may affect receiving characteristics.
So be careful the followings:
2.1. VCO tank inductor L1 and PA choke inductor L3 or LNA matching inductor L2 should be placed so that
their positional relationship becomes the 90 degrees to avoid their coupling (Refer to Figure 4.2.2).
2.2. L1 and L3 or L2 should be placed close to their connect pins of ML7406. They should not be placed
close to each other..
2.3. RF maching circuit should not be close to the L1.
Figure 4.2.1 Notes on the VCO tank circuit
IND1 (#28)
REG_PA (#21)
PA_OUT (#20)
PA
Regulator
VCO
Matching
Network
PA
L3
20mW
Interference signal
IND2 (#30)
L1
C1
LNA_P (#24)
LNA
Matching
Network
ANT
_SW
L2

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Figure 4.2.2 Recommended placement of L1 and L2 or L3
L2 or L3 and L6 should be placed so that
their positional relationship with the 90
degrees in order to avoid their coupling.
L2/
L3
L1

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5. RF matching component values
Table 5.1 shows the measured impedance of the PA_OUT (#20) pin and the LNA_P (#24) pin at 868MHz. These
impedances were measured at LSI pins without matching circuits. Please adjust matching circuit so that the
impedance at the antenna edge is 50 Ω. These impedances are presented as a reference.
Table 5.1 Measured RF impedance at 868MHz operation
R+jX [Ω]
Tx (PA_OUT pin)
13dBm
19.23 –j43.57
10dBm
T.B.D.
0dBm
14.82 –j53.80
Rx (LNA_P pin)
34.35 –j112.6
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.
5.1. Transmission matching circuit
Figure 6.1.1 shows the transmission maching circuit configuraltions. The REG_PA (#28) pin provides the DC
bias to the PA_OUT(#27) pin. This DC bias should be provided through the inductor (L6). The parallel resonant
circuit (L8,C48) and series resonant circuits (L9,C49 and L11,C51) are the trap filter to suppress harmonics.
Figure 5.1.1 Transmission matching circuit configurations
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.
PA_OUT (#20)
L3
4.1nH
C45
100pF
L6
6.2nH
L5
3.6nH
C47
0.9pF
C48
1.0pF
C44
2.4pF
REG_PA (#21)
C38
100pF
C37
1µF
Blue line is 50Ω
line
ANTENNA

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5.2. Reception matching circuit
Figure 5.2.1 shows the reception maching circuit configuraltions. T-type matching circuit consists of C41, C42
and L4.
Figure 5.2.1 Reception matching circuit configurations
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.
LNA_P (#24)
C42
0.7pF
C41
100pF
L2
13nH
Blue line is 50Ω
line
ANTENNA

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6. Antenna Switch
Figure 6.1 shows the antenna switch configuration for using 2-diversity function. When the 2-diversity function
is not used, a DPDT switch IC is replaced by a SPDT. A antenna switch can be controlled by some GPIO pins. In
default, GPIO2 (#18) pin connect to #2 pin on DPDT switch, and GPIO3 (#19) pin connect to #5 pin on DPDT
switch.
Figure 6.1 Antenna switch circuit configurations for 2-diversity
7. Temperature measurement
ML7406 has thermometer. When using the implemented thermometer, place a 75kΩ resister between A_MON
(#23) pin and the ground.It is recommended to use a high accuracy resistor with well temperature characteristics.
When the implemented thermometer is not used, leave the A_MON (#23) pin to “OPEN”.
Figure 7.1 A_MON (#23) configurations for using implemented thermometer
A_MON (#23)
R1
75kΩ
PA_OUT (#27)
LNA_P (#30)
GPIO2 (#18)
GPIO3 (#19)
SMA2(ANT2)
SMA1(ANT1)
IC2
μPG2164T5N
1
C39
1000pF
C40
1000pF
C51
1000pF
C52
1000pF
GND
4
6
5
2
3
RX
Matching
Network
TX
Matching
Network

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8. Notes on selecting external parts (recommendations)
Anntenna
It is recommended to use an antenna with the specifications shown in Table 8.1.
Select an antenna with the best directive characteristics for your specific operating, environmental and
installation condition. Since antennas are affected by installation conditions such as GND, external factors should
always be taken into account.
It is recommended to ask the manufacturer of the selected antenna for installation details in relation to various
factors, including the shape and stray capacitance of the board to be used.
Table 8.1 Antenna
Frequency band
868MHz band
VSWR
2.0MAX
Nominal Impedance
50Ω
Inductors
Use inductors with high Q. It is recommended to use LQW15AN series (manufactured by Murata Manufacturing
Co. Ltd) or equivalent.
Capacitors
Use capacitors with a CH (temperature compensating) or a B (high dielectric constant type) of temperature
characteristics. It is recommended to use capacitors of 0 ± 60 ppm/°C or less for areas that affect high frequency
characteristics.
Resistors
Use resistors for which the resistance variation are small when the temperature changes.
9. Notes on board artworks (recommendations)
9.1. GND
About IC’s back side GND pad, the number of through-hole to board GND plane should be placed more than 12.
And drawing GND line width should be more wide as much as possible. Almost of L2 layer should be GND plane
for double-layerd board.