Epiq Solutions Sidekiq X2 Instructions for use

Sidekiq™ X2
RF Transceiver • High Performance
HARDWARE USER MANUAL
V1.0 - NOVEMBER 11, 2020

Sidekiq™ X2 | Hardware User Manual
CHANGELOG
Revision Date Description Author
0.1 2017-08-10 Pre-release draft, initial version Barry L
0.2 2017-09-07 Subtandital updates in content; Added full pin map; Added Rx pre-select filter plot Barry L
0.3 2017-09-15 Updates after internal review; ready for public release Barry L
0.4 2020-03-09 Updated sections 7.1, 7.3, 8, 8.7, 8.8, 10.2, 10.3, 11, table12. Added table 3,
sections 13, 14 Barry L
1.0 2020-11-11 Markdown conversion, table updates Barry L

Sidekiq™ X2 | Hardware User Manual
DISCLAIMER
Epiq Solutions is disclosing this document (“Documentation”) as a general guideline for development. Epiq
Solutions expressly disclaims any liability arising out of your use of the Documentation. Epiq Solutions
reserves the right, at its sole discretion, to change the Documentation without notice at any time. Epiq
Solutions assumes no obligation to correct any errors contained in the Documentation, or to advise you of any
corrections or updates. Epiq Solutions expressly disclaims any liability in connection with technical support or
assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS
DISCLOSED TO YOU “AS IS” WITH NO WARRANTY OF ANY KIND. EPIQ SOLUTIONS MAKES NO
OTHER WARRANTIES, WHETHER EXPRESSED, IMPLIED, OR STATUTORY, REGARDING THE
DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT WILL
EPIQ SOLUTIONS BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR
INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR
USE OF THE DOCUMENTATION.

Sidekiq™ X2 | Hardware User Manual
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TABLE OF CONTENTS
Introduction
Legal Considerations
Proper Care and Handling
References
Terms and Definitions
Hardware Overview
Hardware Specification
RF Receiver Specification (Rx1, Rx2, ObsRx)
RF Transmitter Specification (Tx1, Tx2)
Clock/Synchronization Specification
Hardware Specification
Hardware Interfaces
Tri-Color Status LED
J1 (Rx2)
J2 (Rx1)
J3 (ObsRx)
J4 (Tx1)
J5 (Tx2)
Input - 10 MHz
PPS Input
RF Shield + Heatsink
VITA 57.1 HPC Connector
Supplemental Heat Transfer Surface
FMC Pin Map
FMC Low Pin Count (LPC) Section
FMC High Pin Count (HPC) Section
Basic Usage in a Host System
Host System Compatibility
Operating System Compatibility
Power Consumption
Thermal Dissipation
JTAG Access on Sidekiq
Sidekiq X2 Mechanical Outline
Sidekiq X2 Thunderbolt 3 Platform
Overview
Basic Usage the Sidekiq X2 Thunderbolt 3 Platform

Sidekiq™ X2 | Hardware User Manual
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Accessing JTAG on the Sidekiq X2 Thunderbolt 3 Platform
Appendix A - Sidekiq X2 Statement of Volatility
Appendix B - Failure Rate & MTBF

Sidekiq™ X2 | Hardware User Manual Introduction
Epiq Solutions Proprietary Page 6
This document provides an overview and usage details of Epiq Solutions' Sidekiq X2 multichannel
RF transceiver card [1], a VITA 57.1 compliant FPGA mezzanine card (FMC) utilizing the high pin
count (HPC) interface. Sidekiq X2 provides the entire "antenna-to-bits" high performance RF signal
chain in a single card, allowing a customer to radically shorten their typical RF platform development
cycle. Sidekiq X2 can interface to any FMC HPC host system, where an FPGA and additional follow
on processing would be executed. Epiq Solutions provides an FPGA reference design as well as
software drivers, libraries, and test applications to demonstrate the usage of Sidekiq X2 interfaced to
a COTS FMC host platform with a PCIe interface to a host computing system. This reference design,
as well as the software drivers, libraries, and test applications, can then be ported to other FMC host
carrier systems for custom deployment scenarios.
The following topics will be discussed:
Overview of the Sidekiq X2 hardware interfaces
Sidekiq X2 usage/integration options
Sidekiq X2 example usage in the FMC host platform reference design
All documentation and support for Sidekiq X2 is provided through Epiq Solutions' support website
[2], please note that it is necessary to register prior to accessing the relevant information for your
purchase.
INTRODUCTION

Sidekiq™ X2 | Hardware User Manual Legal Considerations
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The Sidekiq X2 is distributed all over the world. Each country has its own laws governing reception
and transmission of radio frequencies. Each user of Sidekiq X2 and associated software is solely
responsible for insuring that it is used in a manner consistent with the laws of the jurisdiction in
which it is used. Many countries, including the United States, prohibit the transmission and reception
of certain frequency bands, or receiving certain transmissions without proper authorization. Again,
the user is solely responsible for the user's own actions.
LEGAL CONSIDERATIONS

Sidekiq™ X2 | Hardware User Manual Proper Care and Handling
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Each Sidekiq X2 card is fully tested by Epiq Solutions before shipment, and is guaranteed functional
at the time it is received by the customer, and ONLY AT THAT TIME. Improper use of the Sidekiq X2
card can cause it to become non-functional. In particular, a list of actions that may cause damage to
the hardware include the following:
Handling the unit without proper static precautions (ESD protection) when the housing is
removed or opened up
Inserting or removing Sidekiq X2 from a host system when power is applied to the host system
Connecting a transmitter to the RX port without proper attenuation
Executing custom software and/or an FPGA bitstream that was not developed according to
guidelines
The above list is not comprehensive, and experience with the appropriate measures for handling
electronic devices is required.
PROPER CARE AND HANDLING

Sidekiq™ X2 | Hardware User Manual References
Epiq Solutions Proprietary Page 9
1. Sidekiq X2 Product Page
https://epiqsolutions.com/rf-transceiver/sidekiq-x2
2. Epiq Solutions Support Page
https://support.epiqsolutions.com
3. VITA website
https://www.vita.com
4. Analog Devices' AD9371 Wideband Transceiver Product Page
http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters-
receivers/wideband-transceivers-ic/ad9371.html
5. HiTech Global's Product Page for the HTG-K800 FPGA PCIe Carrier Card
http://www.hitechglobal.com/Boards/Kintex-UltraScale.htm
REFERENCES

Sidekiq™ X2 | Hardware User Manual Terms and Definitions
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Term Definition
A/D Analog to Digital converter
D/A Digital to Analog converter
dB Decibel
dBm Decibels (dB) with reference to one milliwatt (mW).
ESD ElectroStatic Discharge
FMC FPGA Mezzanine Card
FPGA Field Programmable Gate Array
GPS Global Positioning System
HPC High Pin Count (a variant of the VITA 57.1 electrical interface)
I/Q In-Phase / Quadrature Phase
JTAG Joint Test Action Group
KHz Kilohertz
LED Light Emitting Diode
LFM Linear Feet per Minute
LNA Low Noise Amplifier
LPC Low Pin Count (a variant of the VITA 57.1 electrical interface)
MHz Megahertz
MMCX Micro-Miniature Coaxial RF Connector
ObsRx Observation Receiver
PC Personal Computer
PDK Platform Development Kit
PPS Pulse Per Second
RF Radio Frequency
Rx Receive
SDK Software Development Kit
SDR Software Defined Radio
SMP Sub-Miniature push-on RF connector
SSH Secure SHell
TERMS AND DEFINITIONS

Sidekiq™ X2 | Hardware User Manual Terms and Definitions
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SSMC A smaller version of the SubMiniature type C RF connector
TCXO Temperature Compensated Crystal Oscillator
Tx Transmit
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
VITA The standards body governing a variety of electro-mechanical specifications for computing systems (see [3] for
details).
Table 1: Terms and Definitions

Sidekiq™ X2 | Hardware User Manual Hardware Overview
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Sidekiq X2 is a high performance multichannel RF transceiver card providing a complete "antenna-
to-bits" solution in a VITA 57.1 FPGA mezzanine card (FMC) form factor. Sidekiq X2 leverages
Analog Devices' AD9371 wideband transceiver RFIC [4] to provide the core functionality of the card.
The capability of the card is further enhanced with on-board circuitry to extend the RF tuning range,
provide RF pre-select filtering on the RF receivers, support external synchronization inputs, and
other features only found on Sidekiq X2. The key highlights of Sidekiq X2 are enumerated below:
VITA 57.1 FMC compliant card providing a high pin count (HPC) interface
RF tuning range from 1 MHz to 6 GHz
Phase coherent RF receiver pair with common LO
Third independently tunable RF receiver
Phase coherent RF transmitter pair with common LO
Supports RF channel bandwidths up to 100 MHz
16-bit A/D converters supporting sample rates up to 122.88 Msamples/sec
14-bit D/A converters supporting sample rates up to 245.76 Msamples/sec
Seven-band RF pre-select filters on all RF receivers
On-board 10 MHz TCXO reference clock (0.2 PPM stability)
Accepts external 10 MHz and PPS inputs for synchronization to user provided reference signals
Weight: 2.7 oz
Power: 4-10 W (application dependent)
Size: 84.1mm x 69mm
HARDWARE OVERVIEW

Sidekiq™ X2 | Hardware User Manual Hardware Overview
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Figure 1: Sidekiq X2 card (with heatsink / RF shield installed)

Sidekiq™ X2 | Hardware User Manual Hardware Overview
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Figure 2: Sidekiq X2 block diagram

Sidekiq™ X2 | Hardware User Manual Hardware Specification
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RF Input 50 ohms (MMCX, SMP and SSMC options)
Architecture Zero-IF (direct conversion)
Tuning Range 75 MHz to 6 GHz, able to capture 1 MHz to 6 GHz
Tuning Step Size 2.3 Hz
Tuning Time ~ 1 ms to 2.5 ms, contact Epiq Solutions' support [2] for more detailed information
Typical Noise Figure 6-8 dB below 3 GHz, 8-10 dB above 3 GHz
Spurious-Free Dynamic Range ~ 70 – 80 dB typical
Typical IIP3 (at 8 dB noise figure) +5 to +10 dBm
Gain Control Range 0 to 30 dB (Rx1 and Rx2); 0-18 dB (ObsRx); 1 dB steps
Gain Control Modes Manual or AGC
A/D Converter Sample Rate Up to 122.88 Msamples/sec
A/D Converter Sample Width 16 bits
Typical I/Q Balance 70 dB
A/D JESD204b Lane Rate Up to 6.144 Gbps
# of JESD204b Lanes Utilized Rx1, Rx2: 1 lane ObsRx: 1 or 2 lanes (Fs dependent)
Max RF input signal (without
damage) +25 dBm
RF full scale input (at max gain) ~ -30 dBm to -20 dBm, (frequency dependent)
RF Pre-Select Filter Passbands Automatically selected when tuning the RF receiver; see Figure 3 for passband
details
Table 2: rx specification
RF Output 50 ohms (MMCX, SMP and SSMC options)
Architecture Zero-IF (direct conversion)
HARDWARE SPECIFICATION
RF RECEIVER SPECIFICATION (RX1, RX2, OBSRX)
RF TRANSMITTER SPECIFICATION (TX1, TX2)

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Tuning Range
Tx1: 1 MHz* to 6 GHz
Tx2: 300 MHz to 6 GHz
*Tx1 transmit frequency between 1 MHz and 300 MHz shares an LO source for block
conversion with the ObsRx port
Tuning Step Size 2.3 Hz
Tuning Time ~ 1 to 2.5 ms, contact Epiq Solutions' support [2] for more detailed information
Gain Control Range 0 to 42 dB, 1 dB steps
Max RF Transmit Output
Power
Tx1: +10 dBm to +15 dBm (<3 GHz)
+3 dBm to +10 dBm (>3 GHz)
Tx2: 0 dBm to +3 dBm (<3 GHz)
-10 dBm to 0 dBm (>3 GHz)
Typical OIP3 +26 dBm
D/A Converter Sample
Rate Up to 245.76 Msamples/sec
D/A Converter Sample
Width 14 bits
Typical I/Q Balance >60 dB
D/A JESD204b Lane
Rate Up to 6.144 Gbps
# of JESD204b Lanes
Utilized
Tx1: 1 or 2 lanes (sample rate dependent)
Tx2: 1 or 2 lanes (sample rate dependent)
Table 3: tx specification
Port 50 ohms (MMCX, SMP and SSMC options)
On Board Reference Clock 40 MHz TCXO (0.2 PPM stability) Part #: Abracon ASVTX12
External Reference Clock Input Frequency 10 MHz
External Reference Clock Input Power Range -5 dBm to +10 dBm
On Board VCXO for DEV_CLK
Software switchable between two options (both populated on board):
Option 1: 153.6 MHz (PN: Bliley BCVCB153M6)
Option 2: 100 MHz (PN: Bliley BCVCB100)
PPS Input Level Vadj logic level (1.8V or 2.5V), 5V tolerant
Table 4: clock/sync specification
CLOCK/SYNCHRONIZATION SPECIFICATION
HARDWARE SPECIFICATION

Sidekiq™ X2 | Hardware User Manual Hardware Specification
Epiq Solutions Proprietary Page 17
Component Temperature Rating -40 deg C to +85 deg C
FMC Interface Type High Pin Count
FMC Card Dimensions 84.1 mm x 69 mm
FMC Stacking Height 8.5 mm
Weight 2.7 oz
Temperature Sensor -55 deg C to +125 deg C (+/- 2 deg C resolution) P/N: Texas Instruments TMP100
FMC (12P0V) +12 V
FMC (P3V3) +3.3 V
FMC Vadj Support 1.8V or 2.5V
Table 5: hardware specification
Figure 3: Rx pre-select filter passband plot (filtering used on Rx1, Rx2, and ObsRx)

Sidekiq™ X2 | Hardware User Manual Hardware Interfaces
Epiq Solutions Proprietary Page 18
Sidekiq X2 provides is a standard VITA 57.1 compliant FMC card, and thus has a specific set of
externally accessible hardware interfaces that are available to a user when the card is integrated
into a system. Each of these hardware interfaces are enumerated in Figure 4, and are defined
below.
Figure 4: Sidekiq X2 user accessible I/O
The Tri-Color Status LED is a triple LED capable of emitting red, green, and blue light through the
front panel light pipe. This LED is controlled through three GPIO signals (one for each color)
accessible through the VITA 57.1 electrical interface. By default, this LED illuminates blue to indicate
the card is powered up.
The J1 (Rx2) interface is an SSMC jack connector that provides an RF input path for the Rx2
antenna port. This antenna port is capable of receiving signals between 1 MHz and 6 GHz. The RF
HARDWARE INTERFACES
TRI-COLOR STATUS LED
J1 (RX2)

Sidekiq™ X2 | Hardware User Manual Hardware Interfaces
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receiver associated with this antenna port shares a common LO with J2 (Rx1). The impedance of
this port is 50 ohms. This port is also referenced by its handle name (RxA2) in the libsidekiq API.
The J2 (Rx1) interface is an SSMC jack connector that provides an RF input path for the Rx1
antenna port. This antenna port is capable of receiving signals between 1 MHz and 6 GHz. The RF
receiver associated with this antenna port shares a common LO with J1 (Rx2). The impedance of
this port is 50 ohms. This port is also referenced by its handle name (RxA1) in the libsidekiq API.
The J3 (ObsRx) interface is an SSMC jack connector that provides an RF input path for the ObsRx
antenna port. This antenna port is capable of receiving signals between 1 MHz and 6 GHz, and can
be tuned independently of Rx1 and Rx2. The impedance of this port is 50 ohms. This port is also
referenced by its handle name (RxB1) in the libsidekiq API.
The J4 (Tx1) interface is an SSMC jack connector that provides an RF output path for the Tx1
antenna port. This antenna port is capable of transmitting signals between 1 MHz and 6 GHz, and
shares a common LO with J5 (Tx2). The impedance of this port is 50 ohms. This port is also
referenced by its handle name (TxA1) in the libsidekiq API.
The J5 (Tx2) interface is an SSMC jack connector that provides an RF output path for the Tx2
antenna port. This antenna port is capable of transmitting signals between 300 MHz and 6 GHz, and
shares a common LO with J4 (Tx1). The impedance of this port is 50 ohms. This port is also
referenced by its handle name (TxA2) in the libsidekiq API.
The 10 MHz Input port is an SSMC jack connector that accepts an external 10 MHz input signal for
the purpose of phase locking the on board reference clock. The acceptable signal level for this
external 10 MHz input is between -5 dBm and +10 dBm. By default, Sidekiq X2 has an internal
J2 (RX1)
J3 (OBSRX)
J4 (TX1)
J5 (TX2)
INPUT - 10 MHZ

Sidekiq™ X2 | Hardware User Manual Hardware Interfaces
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reference clock on board that is used for phase locking the system. In order to use an external 10
MHz reference input, the libsidekiq software API provides a function call to disable on the on-board
10 MHz reference and lock on to this external 10 MHz reference input.
The PPS Input port is an SSMC jack connector that accepts a pulse per second (PPS) input signal
for the purpose of providing a temporal frame of reference relative to this PPS edge. This PPS signal
is routed through a SN74LVC2G17YZPR buffer directly to the FMC electrical interface, and thus
routes directly into the FPGA on the host system. The PPS edge is expected to be a rising edge with
a fast slew rate, with a logic level high defined as any voltage between 0.85V and 5V, dependent on
Vadj (+1.8V / +2.5V). This PPS signal is used by the Sidekiq X2 FPGA reference design to latch the
digital timestamp of when the PPS edge occurs in the FPGA, and can then be queried by the
libsidekiq software API. It is also possible to coordinate other actions to take place based on the
occurrence of a PPS edge, such as starting Rx or Tx streaming.
Note: for conduction cooled applications, MMCX or SMP connectors are available. Contact Epiq
Solutions for details.
The RF shield/heatsink provides both RF isolation from spurious RF signals, while also providing a
thermal dissipation path for the card when used in convection cooled application. A minimum air flow
of TBD LFM is required to ensure that the heat generated by the card is adequately dissipated.
The VITA 57.1 HPC connector is the primary electrical interface for connecting Sidekiq X2 to a host
system. The complete pin mapping for signals accessible through this HPC interface on Sidekiq X2
is defined in the FMC High Pin Count (HPC) Section..
Note: It is assumed that the standard Sidekiq X2 FPGA reference design + libsidekiq software API
is being utilized by the host system. This reference design + software API provides all of the
infrastructure and control necessary to control the operation of the card, as well as stream data
between the card and the host system. The Sidekiq X2 FPGA reference design + libsidekiq software
API can be ported to alternate host platforms other than the PDK reference platform. Please contact
Epiq Solutions for details.
PPS INPUT
RF SHIELD + HEATSINK
VITA 57.1 HPC CONNECTOR