Lime Microsystems LMS8001 User manual

Lime Microsystems Limited
Surrey Technology Centre
Occam Road
The Surrey Research Park
Guildford, Surrey GU2 7YG
United Kingdom
Tel: [phone]
e-mail: [email protected]m
LMS8001
Reference Manual
Chip version: LMS8001A, LMS8001B
Chip revision: 1
Document version: 1.0
Document revision: 0

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Contents
1
1
Overview..........................................................................................................................1
2
2
Digital Logic Block Diagram .........................................................................................2
2.1 SPI interface...............................................................................................................3
2.2 GPIO..........................................................................................................................4
3
3
Biasing & LDOs..............................................................................................................6
4
4
Temperature Sensor.......................................................................................................7
5
5
Channel and PLL profiles..............................................................................................8
6
6
MUXSEL Macro.............................................................................................................9
7
7
Channel Control Logic.................................................................................................11
7.1 RF Channel Control Logic –LMS8001A ...............................................................11
7.2 High-Linearity Mixer (HLMIX) Control Logic –LMS8001B ...............................12
8
8
HFPLL...........................................................................................................................14
8.1 Overview..................................................................................................................14
8.2 Architecture .............................................................................................................14
8.3 Reference.................................................................................................................15
8.4 HFPLL CORE .........................................................................................................16
8.4.1 Charge-Pump....................................................................................................16
8.4.2 Loop Filter........................................................................................................17
8.4.3 Lock-Detection.................................................................................................17
8.4.4 VCO..................................................................................................................17
8.4.5 FF-DIV .............................................................................................................24
8.5 LO Distribution Network.........................................................................................25
8.6 External LO .............................................................................................................26
8.7 HFPLL Configuration..............................................................................................26
8.7.1 Digital Control Logic........................................................................................26
8.7.2 HFPLL Fast-Lock Mode ..................................................................................28
8.7.3 HFPLL Frequency Calculation.........................................................................29
9
9
Register banks...............................................................................................................31
9.1 Register bank ChipConfig (0x0000 –0x001F) .......................................................32

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9.2 Register bank BiasLDOConfig (0x0010 –0x001F)................................................34
9.3 Register bank Channel_x.........................................................................................38
9.4 Register bank HLMIXx...........................................................................................44
9.5 Register bank PLL_CONFIGURATION (0x4000 –0x401F) ................................47
9.6 Register bank PLL_PROFILE_n.............................................................................51
1
10 0
LMS8001 Package Drawing.........................................................................................56
1
11 1
LMS8001 Pinout ...........................................................................................................57

1
1
1
Overview
LMS8001 (Figure 1.1) contains four RF channels, integrated PLL with programmable LO
distribution, and auxiliary circuits, such as biasing block, integrated LDOs and a temperature
sensor.
Figure 1.1: LMS8001 Block Diagram

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2
2
Digital Logic Block Diagram
Digital logic implemented in LMS8001 is shown in Figure 2.1. It consists of SPI interface for
communication, register banks, programmable GPIO, control logic for RF channels and PLL.
There are four sets (profiles) per RF channel and eight sets (profiles) of PLL control signal
values. Profile can be selected with GPIO pins, SPI register value, or a combination,
depending on how MUXSEL macro is programmed. Additionally, each set of PLL control
signals can be programmed with fast lock values, to facilitate faster frequency settling upon
profile change, e.g. in a frequency hopping application.
In the following figures the signal name color indicates the following: blue –outside signal,
red –signal from the SPI register, and black –internal signal.

3
Figure 2.1: LMS8001 Digital Block Diagram
2.1 SPI interface
The functionality of LMS8001 is fully controlled by a set of internal registers which can be
accessed through a serial SPI port interface. Both write and read operations are supported.
The serial SPI port can be configured to run in 3 or 4 wire mode with the following pins used:
SEN SPI serial port enable, active low, output from master;
SCLK SPI serial clock, output from master;
SDIO SPI serial data in/out (Master Output Slave Input (MOSI) / Master
Input Slave Output (MISO)) in 3 wire mode,
Serial data input (MOSI) in 4 wire mode;
SDO SPI serial data out (MISO) in 4 wire mode, don’t care in 3 wire mode.
SPI serial port key features:
Operating as slave;

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Operating in SPI Mode 0 (data is captured on the clock's rising edge, while data is
shifted on the clock's falling edge);
32 serial clock cycles are required to complete write operation;
32 serial clock cycles are required to complete read operation;
Multiple write/read operations are possible without toggling serial enable signal. All
configuration registers are 16-bit wide. Write/read sequence consists of 16-bit instruction
followed by 16-bit data to write or read. MSB of the instruction bit stream is used as SPI
command where CMD = 1 for write and CMD = 0 for read. The following 15 bits are register
address, followed by 16 data bits.
Write/read cycle waveforms are shown in Figure 2.2, Figure 2.3, and Figure 2.4. Note that
write operation is the same for both 3-wire and 4-wire modes. Although not shown in the
figures, multiple byte write/read is possible by repeating instruction/data sequence while
keeping SEN low.
Figure 2.2: SPI write cycle, 3-wire and 4-wire modes
Figure 2.3: SPI read cycle, 4-wire mode (default)
Figure 2.4: SPI read cycle, 3-wire mode
Registers relevant to SPI configuration are listed in the following table.
Register
Address
Reset value
SPIConfig
0x0000
0x001F
2.2 GPIO
LMS8001 has flexible GPIO with nine individually programmable pins, whose structure is
shown in Figure 2.5. GPIO pins can be used in several ways, from basic input/output to
advanced control of RF channels and PLL. GPIO pin n direction is controlled by
GPIO_InO[n] bit of GPIOConfig_IO register. Pull-up resistor of GPIO pin n is controlled by

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GPIO_PE[n] bit of GPIOConfig_PE register. Output driver strength is controlled by
GPIO_DS[n] bit of GPIOConfig_DS register. GPIO pin n state can be read from GPIO_IN[n]
bit of GPIOInData register. When used as output, GPIO pin n can be configured to output the
value of GPIO_OUT_SPIO[n], or the value of internal signals PLL_LOCK, VTUNE_LOW,
VTUNE_HIGH or FAST_LOCK_ACT. The output selection is configured with
GPIOn_SEL[2:0] bits in registers GPIOOUT_SEL0 and GPIOOUT_SEL1.
Input signals GPIO_IN[8:0] represent the voltage level at GPIO pad, and can be used for
control of RF channel configurations (profiles). When the GPIO pin n is configured as an
input, the value read from GPIO_IN[n] is set by an external source, while it is a loopback
signal when configured as an output. Loopback feature can be used to simultaneously trigger
external event and change the RF channel and/or PLL profile.
Figure 2.5: GPIO pad structure
Registers relevant to GPIO configuration are listed in the following table.
Register
Address
Reset value
GPIOOutData
0x0004
0x0000
GPIOOUT_SEL0
0x0005
0x0000
GPIOOUT_SEL1
0x0006
0x0000
GPIOInData
0x0008
GPIOConfig_PE
0x0009
0x03FF
GPIOConfig_DS
0x000A
0x0000
GPIOConfig_IO
0x000B
0x03FF

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3
3
Biasing & LDOs
LMS8001 biasing block, shown in Figure 3.1, generates all reference currents and voltages
required for chip operation. External 10 kΩ resistor is used for calibration. Integrated LDOs
allow operation from single supply voltage, and are fully programmable. LDOs can be
individually controlled, allowing elaborate power management schemes.
Figure 3.1: LMS8001 Biasing and LDOs
Registers relevant to biasing and LDO configuration are grouped into register bank
BiasLDOConfig.

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4
4
Temperature Sensor
Integrated temperature sensor can be used for temperature compensation of RF channels. To
use the temperature sensor, bias should be enabled by setting TEMP_SENS_EN=1 and clock
by setting TEMP_SENS_CLKEN=1 in register TEMP_SENS. Temperature conversion is
started by writing 1 to TEMP_START_CONV bit, which is cleared when the conversion is
complete. Temperature conversion result can be readout from TEMP_READ[7:0].
Chip temperature can be calculated as:
Temperature [°C] ≈ T0 + T1·TEMP_READ + T2·TEMP_READ2
Where the default temperature coefficient values are:
T0 = -105.45
T1 = 1.2646
T2 = -0.000548
Accuracy of the calculated temperature value is sensitive to mismatch on chip. Without any
calibration the standard variation of the measurement accuracy is around 2 °C.
It is recommended that the single point calibration is performed, in which the coefficient T0 is
calculated. After such calibration, the measurement accuracy should be within ±1.5 °C.
Register relevant to temperature sensor configuration is TEMP_SENS in ChipConfig register
bank.

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5
5
Channel and PLL profiles
Channel and PLL control signals are grouped in signal groups, which are multiplexed
simultaneously. Each signal group has four sets of values per channel, and eight sets of values
for PLL. Collection of signal groups forms a profile. Group multiplexer control signals are
generated by MUXSEL macros, controlled by registers listed in table below.
Profile
Signal Group
Control Registers
Address
CHx
CHx_PD
CHx_PD_SEL0
CHx_BASE+0x10
CHx_PD_SEL1
CHx_BASE+0x11
CHx_LNA
CHx_LNA_SEL0
CHx_BASE+0x12
CHx_LNA_SEL1
CHx_BASE+0x13
CHx_PD
CHx_PD_SEL0
CHx_BASE+0x14
CHx_PD_SEL1
CHx_BASE+0x15
Internal value
CHx_INT_SEL
CHx_BASE+0x16
HLMIXx
HLMIXx_CONF
HLMIXx_CONF_SEL0
HLMIXx_BASE+0x8
HLMIXx_CONF_SEL1
HLMIXx_BASE+0x9
HLMIXx_LOSS
HLMIXx_LOSS_SEL0
HLMIXx_BASE+0xA
HLMIXx_LOSS_SEL1
HLMIXx_BASE+0xB
Internal value
HLMIXx_INT_SEL
HLMIXx_BASE+0xC
PLL
PLL
PLL_CFG_SEL0
0x4008
PLL_CFG_SEL1
0x4009
PLL_CFG_SEL2
0x400A
Internal value
PLL_CFG_SEL
0x400B

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6
6
MUXSEL Macro
RF channel and PLL profiles are selected by multiplexer control signals. Each bit of
multiplexer control signals is generated by MUXSEL macro, shown in Figure 6.1. Control
signal can be generated from GPIO inputs (INTERNAL=0) or from internal register
(INTERNAL=1). GPIO_IN[8:0] signals are masked (logical AND) by GPIO_MASK[8:0] and
the individual terms are ORed to form the control signal value. MUXSEL output is inverted
when control signal INVERT=1 or passed through when INVERT=0, which can be used to
control mutually exclusive configurations with a single GPIO pin.
Figure 6.1: MUXSEL macro
MUXSEL control signals GPIO_MASK, INTERNAL and INVERT are packed in a register
with structure given in table below. There are two or three registers per signal group,
depending on whether there are four or eight profiles. INTERNAL_VALUE bits for all signal
groups are in a separate register, allowing the update of control signals with a single SPI write
command.
Address
Register Name (Reset Value)
Bit
Default
Bitfield Name
Mode
Description
11
1
Group_SELn_INTERNAL
RW
Group control signals multiplexer SELn signal is generated
0 –from GPIO & Group_SELn_MASK,
1 –from Group_INT_SEL<n>

10
Address
Register Name (Reset Value)
Bit
Default
Bitfield Name
Mode
Description
10
0
Group_SELn_INVERT
RW
Invert the SELn signal of Group control signals.
0 –No inversion,
1 –Signal is inverted.
8:0
000000000
Group_SELn_MASK<8:0>
RW
GPIO mask for SELn signal of Group control signals
multiplexer.

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7
7
Channel Control Logic
There are two options of LMS8001. The difference is in the architecture of the RF channels.
Option LMS8001A contains RF channels with LNA, two mixers and power amplifier (Figure
7.1), whereas LMS8001B channel is comprised of high-linearity mixer (HLMIX) only
(Figure 7.3).
7.1 RF Channel Control Logic –LMS8001A
Structure of Channel_x(x=A,B,C,D) is shown in Figure 7.1. Input RF signal can be amplified
by LNA and mixed by MIXA or can be directly fed to mixer MIXB. At mixer output there is
a programmable 50 Ω termination resistor, which can be switched on or off. Power amplifier
(PA) can be used to further amplify the signal, or can be powered down and bypassed.
Figure 7.1: RF Channel –LMS8001A
Channel control signals are generated by digital circuit shown in Figure 7.2. Control signals
are divided into three groups, each with four sets of values, which results in total of 64

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possible configurations. Signal group multiplexer control signals are generated by MUXSEL
macro, allowing the control via GPIO pins, SPI registers, or combination of them.
Figure 7.2: RF Channel control signal multiplexing
Registers relevant to RF Channel configuration are grouped into register banks Channel_x
(x=A,B,C,D).
7.2 High-Linearity Mixer (HLMIX) Control Logic –LMS8001B
Structure of HLMIXx(x=A,B,C,D) is shown in Figure 7.3.
Figure 7.3: High-Linearity Mixer (HLMIX) –LMS8001B
Channel control signals are generated by digital circuit shown in Figure 7.4. Signal group
multiplexer control signals are generated by MUXSEL macro, allowing the control via GPIO
pins, SPI registers, or combination of them.

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Figure 7.4: HLMIX control signal multiplexing
Registers relevant to HLMIX configuration are grouped into register banks HLMIXx
(x=A,B,C,D).

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8
8
HFPLL
8.1 Overview
The LMS8001 up/down frequency shifter IC contains one HFPLL frequency synthesizer for
the generation of the LO signal required in four integrated RF paths. The HFPLL frequency
synthesizer uses fractional-N PLL architecture with completely integrated VCOs and loop
filter. It is fully self-contained synthesizer and requires no external parts to cover the full
specified frequency range of the device using convenient reference frequency values between
10 and 50 MHz. Besides, LMS8001 IC can use external LO signal from the dedicated input
pins.
The fundamental frequency of integrated HFPLL VCO cores ranges from 4.8 to 9.6 GHz.
Local oscillator frequencies can take values from 300 MHz to 9.6 GHz.
8.2 Architecture
Figure 8.1: LMS8001 Frequency Synthesizer

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Block diagram of the complete frequency synthesizer of the LMS8001 IC is shown in the
Figure 8.1. Three main sub-parts are indicated: reference clock buffer, HFPLL core and LO
distribution network. Details about mentioned sub-parts and its containing circuits will be
given in the following sections.
8.3 Reference
The external clock source (as TCXO for example) should be provided to the reference input
of the LMS8001 device. The LMS8001 can accept clipped sine-wave as well as CMOS levels
for the HFPLL reference clock. Diagram of the reference input circuit (XBUF) with dedicated
control signals is presented in Figure 8.2.
Figure 8.2: HFPLL Reference Clock Input Buffer
Both, DC and AC coupling topologies are supported as shown in Figure 8.3. Reference buffer
self-biasing option should be enabled for AC-coupling configuration. For continuous LO
frequency range coverage, reference frequency input should be kept between 10 and 50 MHz.
(a) DC Coupling Mode
(b) AC Coupling Mode
Figure 8.3: HFPLL Reference Clock Input Buffer Configurations

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8.4 HFPLL CORE
The HFPLL core block diagram is shown in Figure 8.4. It is classic type-II, fourth-order PLL
core which uses fractional-N technique with 3rd order noise shaping to synthesize and fine
adjust the LO frequency value. HFPLL core can also be operated in integer-N mode, which
gives the best phase noise performance at the expense of reduced frequency resolution of the
synthesizer.
Figure 8.4: HFPLL Core
Fundamental VCO core frequency covers full octave between 4.8 and 9.6 GHz. Lower
frequency sub-bands down to 300 MHz, can be synthesized by using the feed-forward divider
stages implemented in FF-DIV circuit and LO Distribution Network.
Charge pump current is programmable, as well as the loop filter components, in order to
enable PLL performance optimization for various applications.
PLL configuration for a desired LO frequency is obtained by calculating the required divider
values and VCO settings. User can get the optimal VCO configuration for a desired carrier
frequency by using the internal digital state-machine that implements the VCO frequency
calibration process (or coarse frequency tuning) in the open loop mode. On the other hand,
this state machine can be bypassed and the user can implement its own algorithm, through the
use of SPI interface and feedback information from the HFPLL core about the PLL lock status
(PLL_LOCK, VTUNE_HIGH, VTUNE_LOW) and/or results of comparing the targeted
HFPLL frequency value and VCO oscillation frequency (FREQ_HIGH, FREQ_EQUAL and
FREQ_LOW). More details will be given in the next sections.
8.4.1 Charge-Pump
The charge-pump circuit has 6b programmable pulse and 6b programmable offset currents.
The pulse current value varies from 25 μA to 1.575 mA in 25 μA steps. Offset current value
varies from 0 to 393.75 μA in 6.25 μA steps. Offset current should be used when HFPLL core
operates in fractional-N mode to improve phase-noise performance. It should not exceed 25%
of programmed pulse current value.