Lime Microsystems LMS8001 User manual

Lime Microsystems Limited
Surrey Technology Centre
Occam Road
The Surrey Research Park
Guildford, Surrey GU2 7YG
United Kingdom
Tel: [phone]
e-mail: [email protected]m
LMS8001
Reference Manual
Chip version: LMS8001A, LMS8001B
Chip revision: 1
Document version: 1.0
Document revision: 0

i
Contents
1
1
Overview..........................................................................................................................1
2
2
Digital Logic Block Diagram .........................................................................................2
2.1 SPI interface...............................................................................................................3
2.2 GPIO..........................................................................................................................4
3
3
Biasing & LDOs..............................................................................................................6
4
4
Temperature Sensor.......................................................................................................7
5
5
Channel and PLL profiles..............................................................................................8
6
6
MUXSEL Macro.............................................................................................................9
7
7
Channel Control Logic.................................................................................................11
7.1 RF Channel Control Logic –LMS8001A ...............................................................11
7.2 High-Linearity Mixer (HLMIX) Control Logic –LMS8001B ...............................12
8
8
HFPLL...........................................................................................................................14
8.1 Overview..................................................................................................................14
8.2 Architecture .............................................................................................................14
8.3 Reference.................................................................................................................15
8.4 HFPLL CORE .........................................................................................................16
8.4.1 Charge-Pump....................................................................................................16
8.4.2 Loop Filter........................................................................................................17
8.4.3 Lock-Detection.................................................................................................17
8.4.4 VCO..................................................................................................................17
8.4.5 FF-DIV .............................................................................................................24
8.5 LO Distribution Network.........................................................................................25
8.6 External LO .............................................................................................................26
8.7 HFPLL Configuration..............................................................................................26
8.7.1 Digital Control Logic........................................................................................26
8.7.2 HFPLL Fast-Lock Mode ..................................................................................28
8.7.3 HFPLL Frequency Calculation.........................................................................29
9
9
Register banks...............................................................................................................31
9.1 Register bank ChipConfig (0x0000 –0x001F) .......................................................32

ii
9.2 Register bank BiasLDOConfig (0x0010 –0x001F)................................................34
9.3 Register bank Channel_x.........................................................................................38
9.4 Register bank HLMIXx...........................................................................................44
9.5 Register bank PLL_CONFIGURATION (0x4000 –0x401F) ................................47
9.6 Register bank PLL_PROFILE_n.............................................................................51
1
10 0
LMS8001 Package Drawing.........................................................................................56
1
11 1
LMS8001 Pinout ...........................................................................................................57

1
1
1
Overview
LMS8001 (Figure 1.1) contains four RF channels, integrated PLL with programmable LO
distribution, and auxiliary circuits, such as biasing block, integrated LDOs and a temperature
sensor.
Figure 1.1: LMS8001 Block Diagram

2
2
2
Digital Logic Block Diagram
Digital logic implemented in LMS8001 is shown in Figure 2.1. It consists of SPI interface for
communication, register banks, programmable GPIO, control logic for RF channels and PLL.
There are four sets (profiles) per RF channel and eight sets (profiles) of PLL control signal
values. Profile can be selected with GPIO pins, SPI register value, or a combination,
depending on how MUXSEL macro is programmed. Additionally, each set of PLL control
signals can be programmed with fast lock values, to facilitate faster frequency settling upon
profile change, e.g. in a frequency hopping application.
In the following figures the signal name color indicates the following: blue –outside signal,
red –signal from the SPI register, and black –internal signal.

3
Figure 2.1: LMS8001 Digital Block Diagram
2.1 SPI interface
The functionality of LMS8001 is fully controlled by a set of internal registers which can be
accessed through a serial SPI port interface. Both write and read operations are supported.
The serial SPI port can be configured to run in 3 or 4 wire mode with the following pins used:
SEN SPI serial port enable, active low, output from master;
SCLK SPI serial clock, output from master;
SDIO SPI serial data in/out (Master Output Slave Input (MOSI) / Master
Input Slave Output (MISO)) in 3 wire mode,
Serial data input (MOSI) in 4 wire mode;
SDO SPI serial data out (MISO) in 4 wire mode, don’t care in 3 wire mode.
SPI serial port key features:
Operating as slave;

4
Operating in SPI Mode 0 (data is captured on the clock's rising edge, while data is
shifted on the clock's falling edge);
32 serial clock cycles are required to complete write operation;
32 serial clock cycles are required to complete read operation;
Multiple write/read operations are possible without toggling serial enable signal. All
configuration registers are 16-bit wide. Write/read sequence consists of 16-bit instruction
followed by 16-bit data to write or read. MSB of the instruction bit stream is used as SPI
command where CMD = 1 for write and CMD = 0 for read. The following 15 bits are register
address, followed by 16 data bits.
Write/read cycle waveforms are shown in Figure 2.2, Figure 2.3, and Figure 2.4. Note that
write operation is the same for both 3-wire and 4-wire modes. Although not shown in the
figures, multiple byte write/read is possible by repeating instruction/data sequence while
keeping SEN low.
Figure 2.2: SPI write cycle, 3-wire and 4-wire modes
Figure 2.3: SPI read cycle, 4-wire mode (default)
Figure 2.4: SPI read cycle, 3-wire mode
Registers relevant to SPI configuration are listed in the following table.
Register
Address
Reset value
SPIConfig
0x0000
0x001F
2.2 GPIO
LMS8001 has flexible GPIO with nine individually programmable pins, whose structure is
shown in Figure 2.5. GPIO pins can be used in several ways, from basic input/output to
advanced control of RF channels and PLL. GPIO pin n direction is controlled by
GPIO_InO[n] bit of GPIOConfig_IO register. Pull-up resistor of GPIO pin n is controlled by

5
GPIO_PE[n] bit of GPIOConfig_PE register. Output driver strength is controlled by
GPIO_DS[n] bit of GPIOConfig_DS register. GPIO pin n state can be read from GPIO_IN[n]
bit of GPIOInData register. When used as output, GPIO pin n can be configured to output the
value of GPIO_OUT_SPIO[n], or the value of internal signals PLL_LOCK, VTUNE_LOW,
VTUNE_HIGH or FAST_LOCK_ACT. The output selection is configured with
GPIOn_SEL[2:0] bits in registers GPIOOUT_SEL0 and GPIOOUT_SEL1.
Input signals GPIO_IN[8:0] represent the voltage level at GPIO pad, and can be used for
control of RF channel configurations (profiles). When the GPIO pin n is configured as an
input, the value read from GPIO_IN[n] is set by an external source, while it is a loopback
signal when configured as an output. Loopback feature can be used to simultaneously trigger
external event and change the RF channel and/or PLL profile.
Figure 2.5: GPIO pad structure
Registers relevant to GPIO configuration are listed in the following table.
Register
Address
Reset value
GPIOOutData
0x0004
0x0000
GPIOOUT_SEL0
0x0005
0x0000
GPIOOUT_SEL1
0x0006
0x0000
GPIOInData
0x0008
GPIOConfig_PE
0x0009
0x03FF
GPIOConfig_DS
0x000A
0x0000
GPIOConfig_IO
0x000B
0x03FF

6
3
3
Biasing & LDOs
LMS8001 biasing block, shown in Figure 3.1, generates all reference currents and voltages
required for chip operation. External 10 kΩ resistor is used for calibration. Integrated LDOs
allow operation from single supply voltage, and are fully programmable. LDOs can be
individually controlled, allowing elaborate power management schemes.
Figure 3.1: LMS8001 Biasing and LDOs
Registers relevant to biasing and LDO configuration are grouped into register bank
BiasLDOConfig.