Rabbit Rabbit 4000 User manual

Rabbit®4000 Microprocessor
User’s Manual
019–0152 • 070720–H

Rabbit 4000 Microprocessor User’s Manual
Rabbit Semiconductor Inc.
www.rabbit.com
Rabbit 4000 Microprocessor User’s Manual
Part Number 019-0152 • 070720–H • Printed in U.S.A.
©2006–2007 Rabbit Semiconductor Inc. • All rights reserved.
Rabbit Semiconductor reserves the right to make changes and
improvements to its products without providing notice.
Trademarks
Rabbit and Dynamic C are registered trademarks of Rabbit Semiconductor Inc.
Rabbit 4000 is a trademark of Rabbit Semiconductor Inc.
No part of the contents of this manual may be reproduced or transmitted in any form or by any means
without the express written permission of Rabbit Semiconductor.
Permission is granted to make one or more copies as long as the copyright page contained therein is
included. These copies of the manuals may not be let or sold for any reason without the express written
permission of Rabbit Semiconductor.
The latest revision of this manual is available on the Rabbit Semiconductor Web site,
www.rabbit.com, for free, unregistered download.

Table of Contents
TABLE OF CONTENTS
Chapter 1. The Rabbit 4000 Processor 1
1.1 Introduction...........................................................................................................................................1
1.2 Features.................................................................................................................................................1
1.3 Block Diagram......................................................................................................................................4
1.4 Basic Specifications..............................................................................................................................5
1.5 Comparing Rabbit Microprocessors.....................................................................................................6
Chapter 2. Clocks 9
2.1 Overview...............................................................................................................................................9
2.1.1 Block Diagram ...........................................................................................................................10
2.1.2 Registers .....................................................................................................................................10
2.2 Dependencies......................................................................................................................................11
2.2.1 I/O Pins ......................................................................................................................................11
2.2.2 Other Registers ...........................................................................................................................11
2.3 Operation ............................................................................................................................................12
2.3.1 Main Clock .................................................................................................................................12
2.3.2 Spectrum Spreader .....................................................................................................................13
2.3.3 Clock Doubler ............................................................................................................................15
2.3.4 32 kHz Clock .............................................................................................................................18
2.4 Register Descriptions..........................................................................................................................20
Chapter 3. Reset and Bootstrap 25
3.1 Overview.............................................................................................................................................25
3.1.1 Block Diagram ...........................................................................................................................25
3.1.2 Registers .....................................................................................................................................26
3.2 Dependencies......................................................................................................................................26
3.2.1 I/O Pins ......................................................................................................................................26
3.2.2 Clocks .........................................................................................................................................26
3.2.3 Other Registers ...........................................................................................................................26
3.2.4 Interrupts ....................................................................................................................................26
3.3 Operation ............................................................................................................................................27
3.4 Register Descriptions..........................................................................................................................29
Chapter 4. System Management 31
4.1 Overview.............................................................................................................................................31
4.1.1 Block Diagram ...........................................................................................................................32
4.1.2 Registers .....................................................................................................................................32
4.2 Dependencies......................................................................................................................................33
4.2.1 I/O Pins ......................................................................................................................................33
4.2.2 Clocks .........................................................................................................................................33
4.2.3 Interrupts ....................................................................................................................................33
4.3 Operation ............................................................................................................................................34
4.3.1 Periodic Interrupt .......................................................................................................................34
4.3.2 Real-Time Clock ........................................................................................................................34
4.3.3 Watchdog Timer ........................................................................................................................35
4.3.4 Secondary Watchdog Timer .......................................................................................................35
4.4 Register Descriptions..........................................................................................................................36

Rabbit 4000 Microprocessor User’s Manual
Chapter 5. Memory Management 41
5.1 Overview............................................................................................................................................41
5.1.1 Block Diagram ...........................................................................................................................43
5.1.2 Registers ....................................................................................................................................44
5.2 Dependencies .....................................................................................................................................45
5.2.1 I/O Pins ......................................................................................................................................45
5.2.2 Clocks ........................................................................................................................................45
5.2.3 Other Registers ..........................................................................................................................45
5.2.4 Interrupts ....................................................................................................................................45
5.3 Operation............................................................................................................................................46
5.3.1 Memory Management Unit (MMU) ..........................................................................................46
5.3.2 8-bit Operation ...........................................................................................................................47
5.3.3 16-bit and Page Modes ..............................................................................................................49
5.3.4 Separate Instruction and Data Space .........................................................................................52
5.3.5 Memory Protection ....................................................................................................................52
5.3.6 Stack Protection .........................................................................................................................52
5.4 Register Descriptions .........................................................................................................................53
Chapter 6. Interrupts 65
6.1 Overview............................................................................................................................................65
6.2 Operation............................................................................................................................................66
6.3 Interrupt Tables .................................................................................................................................. 66
Chapter 7. External Interrupts 69
7.1 Overview............................................................................................................................................69
7.2 Block Diagram ...................................................................................................................................69
7.2.1 Registers ....................................................................................................................................70
7.3 Dependencies .....................................................................................................................................70
7.3.1 I/O Pins ......................................................................................................................................70
7.3.2 Clocks ........................................................................................................................................70
7.3.3 Interrupts ....................................................................................................................................70
7.4 Operation............................................................................................................................................70
7.4.1 Example ISR ..............................................................................................................................70
7.5 Register Descriptions .........................................................................................................................71
Chapter 8. Parallel Port A 73
8.1 Overview............................................................................................................................................73
8.1.1 Block Diagram ...........................................................................................................................73
8.1.2 Registers ....................................................................................................................................73
8.2 Dependencies .....................................................................................................................................74
8.2.1 I/O Pins ......................................................................................................................................74
8.2.2 Clocks ........................................................................................................................................74
8.2.3 Other Registers ..........................................................................................................................74
8.2.4 Interrupts ....................................................................................................................................74
8.3 Operation............................................................................................................................................74
8.4 Register Descriptions .........................................................................................................................75
Chapter 9. Parallel Port B 77
9.1 Overview............................................................................................................................................77
9.1.1 Block Diagram ...........................................................................................................................78
9.1.2 Registers ....................................................................................................................................78
9.2 Dependencies .....................................................................................................................................78
9.2.1 I/O Pins ......................................................................................................................................78
9.2.2 Clocks ........................................................................................................................................78
9.2.3 Other Registers ..........................................................................................................................78
9.2.4 Interrupts ....................................................................................................................................79
9.3 Operation............................................................................................................................................79
9.4 Register Descriptions .........................................................................................................................79

Table of Contents
Chapter 10. Parallel Port C 81
10.1 Overview...........................................................................................................................................81
10.1.1 Block Diagram .........................................................................................................................82
10.1.2 Registers ...................................................................................................................................82
10.2 Dependencies....................................................................................................................................83
10.2.1 I/O Pins ....................................................................................................................................83
10.2.2 Clocks .......................................................................................................................................83
10.2.3 Other Registers .........................................................................................................................83
10.2.4 Interrupts ..................................................................................................................................83
10.3 Operation ..........................................................................................................................................83
10.4 Register Descriptions........................................................................................................................84
Chapter 11. Parallel Port D 87
11.1 Overview...........................................................................................................................................87
11.1.1 Block Diagram .........................................................................................................................89
11.1.2 Registers ...................................................................................................................................90
11.2 Dependencies....................................................................................................................................90
11.2.1 I/O Pins ....................................................................................................................................90
11.2.2 Clocks .......................................................................................................................................90
11.2.3 Other Registers .........................................................................................................................91
11.2.4 Interrupts ..................................................................................................................................91
11.3 Operation ..........................................................................................................................................91
11.4 Register Descriptions........................................................................................................................92
Chapter 12. Parallel Port E 97
12.1 Overview...........................................................................................................................................97
12.1.1 Block Diagram .........................................................................................................................99
12.1.2 Registers .................................................................................................................................100
12.2 Dependencies..................................................................................................................................100
12.2.1 I/O Pins ..................................................................................................................................100
12.2.2 Clocks .....................................................................................................................................100
12.2.3 Other Registers .......................................................................................................................101
12.2.4 Interrupts ................................................................................................................................101
12.3 Operation ........................................................................................................................................101
12.4 Register Descriptions......................................................................................................................102
Chapter 13. Timer A 107
13.1 Overview.........................................................................................................................................107
13.1.1 Block Diagram .......................................................................................................................109
13.1.2 Registers .................................................................................................................................110
13.2 Dependencies..................................................................................................................................110
13.2.1 I/O Pins ..................................................................................................................................110
13.2.2 Clocks .....................................................................................................................................110
13.2.3 Other Registers .......................................................................................................................110
13.2.4 Interrupts ................................................................................................................................111
13.3 Operation ........................................................................................................................................111
13.3.1 Handling Interrupts ................................................................................................................111
13.3.2 Example ISR ..........................................................................................................................111
13.4 Register Descriptions......................................................................................................................112
Chapter 14. Timer B 115
14.1 Overview.........................................................................................................................................115
14.1.1 Block Diagram .......................................................................................................................115
14.1.2 Registers .................................................................................................................................116
14.2 Dependencies..................................................................................................................................116
14.2.1 I/O Pins ..................................................................................................................................116
14.2.2 Clocks .....................................................................................................................................116
14.2.3 Other Registers .......................................................................................................................116
14.2.4 Interrupts ................................................................................................................................116

Rabbit 4000 Microprocessor User’s Manual
14.3 Operation........................................................................................................................................117
14.3.1 Handling Interrupts ................................................................................................................117
14.3.2 Example ISR ..........................................................................................................................117
14.4 Register Descriptions .....................................................................................................................118
Chapter 15. Timer C 121
15.1 Overview........................................................................................................................................121
15.1.1 Block Diagram .......................................................................................................................122
15.1.2 Registers ................................................................................................................................123
15.2 Dependencies .................................................................................................................................124
15.2.1 I/O Pins ..................................................................................................................................124
15.2.2 Clocks ....................................................................................................................................124
15.2.3 Other Registers ......................................................................................................................124
15.2.4 Interrupts ................................................................................................................................124
15.3 Operation........................................................................................................................................125
15.3.1 Handling Interrupts ................................................................................................................125
15.3.2 Example ISR ..........................................................................................................................125
15.4 Register Descriptions .....................................................................................................................126
Chapter 16. Serial Ports A – D 129
16.1 Overview........................................................................................................................................129
16.1.1 Block Diagram .......................................................................................................................131
16.1.2 Registers ................................................................................................................................132
16.2 Dependencies .................................................................................................................................133
16.2.1 I/O Pins ..................................................................................................................................133
16.2.2 Clocks ....................................................................................................................................134
16.2.3 Other Registers ......................................................................................................................134
16.2.4 Interrupts ................................................................................................................................134
16.3 Operation........................................................................................................................................135
16.3.1 Asynchronous Mode ..............................................................................................................135
16.3.2 Clocked Serial Mode .............................................................................................................136
16.4 Register Descriptions .....................................................................................................................138
Chapter 17. Serial Ports E – F 145
17.1 Overview........................................................................................................................................145
17.1.1 Block Diagram .......................................................................................................................146
17.1.2 Registers ................................................................................................................................147
17.2 Dependencies .................................................................................................................................148
17.2.1 I/O Pins ..................................................................................................................................148
17.2.2 Clocks ....................................................................................................................................148
17.2.3 Other Registers ......................................................................................................................148
17.2.4 Interrupts ................................................................................................................................149
17.3 Operation........................................................................................................................................150
17.3.1 Asynchronous Mode ..............................................................................................................150
17.3.2 HDLC Mode ..........................................................................................................................150
17.3.3 More on Clock Synchronization and Data Encoding ............................................................151
17.4 Register Descriptions .....................................................................................................................155
Chapter 18. Slave Port 161
18.1 Overview........................................................................................................................................161
18.1.1 Block Diagram .......................................................................................................................162
18.1.2 Registers ................................................................................................................................162
18.2 Dependencies .................................................................................................................................163
18.2.1 I/O Pins ..................................................................................................................................163
18.2.2 Clocks ....................................................................................................................................163
18.2.3 Interrupts ................................................................................................................................163

Table of Contents
18.3 Operation ........................................................................................................................................164
18.3.1 Master Setup ..........................................................................................................................165
18.3.2 Slave Setup .............................................................................................................................165
18.3.3 Master/Slave Communication ................................................................................................166
18.3.4 Slave/Master Communication ................................................................................................166
18.3.5 Handling Interrupts ................................................................................................................166
18.3.6 Example ISR ..........................................................................................................................166
18.3.7 Other Configurations ..............................................................................................................167
18.3.8 Timing Diagrams ...................................................................................................................168
18.4 Register Descriptions......................................................................................................................170
Chapter 19. DMA Channels 173
19.1 Overview.........................................................................................................................................173
19.1.1 Block Diagram .......................................................................................................................175
19.1.2 Registers .................................................................................................................................176
19.2 Dependencies..................................................................................................................................177
19.2.1 I/O Pins ..................................................................................................................................177
19.2.2 Clocks .....................................................................................................................................177
19.2.3 Interrupts ................................................................................................................................177
19.3 Operation ........................................................................................................................................178
19.3.1 Handling Interrupts ................................................................................................................179
19.3.2 Example ISR ..........................................................................................................................179
19.3.3 DMA Priority with the Processor ...........................................................................................179
19.3.4 DMA Channel Priority ...........................................................................................................181
19.3.5 Buffer Descriptor Modes .......................................................................................................181
19.3.5.1 Single Buffer ..................................................................................................................182
19.3.5.2 Buffer Array ...................................................................................................................182
19.3.5.3 Linked List .....................................................................................................................183
19.3.5.4 Circular Queue ...............................................................................................................184
19.3.5.5 Linked Array ..................................................................................................................184
19.3.6 DMA with Peripherals ...........................................................................................................185
19.3.6.1 DMA with HDLC Serial Ports .......................................................................................185
19.3.6.2 DMA with Ethernet ........................................................................................................185
19.3.6.3 DMA with PWM and Timer C .......................................................................................185
19.3.7 DMA Bug Workarounds (Appendix B.2) ..............................................................................185
19.3.7.1 DMA/HDLC/Ethernet Interaction ..................................................................................185
19.3.8 DMA/Block Copy Interaction ................................................................................................186
19.3.9 Single-Byte DMA Requests to internal I/O Registers ...........................................................186
19.4 Register Descriptions......................................................................................................................187
Chapter 20. 10Base-T Ethernet 201
20.1 Overview.........................................................................................................................................201
20.1.1 Block Diagram .......................................................................................................................203
20.1.2 Registers .................................................................................................................................204
20.2 Dependencies..................................................................................................................................205
20.2.1 I/O Pins ..................................................................................................................................205
20.2.2 Clocks .....................................................................................................................................205
20.2.3 Other Registers .......................................................................................................................205
20.2.4 Interrupts ................................................................................................................................205
20.3 Operation ........................................................................................................................................206
20.3.1 Setup .......................................................................................................................................206
20.3.2 Transmit .................................................................................................................................206
20.3.3 Receive ...................................................................................................................................206
20.3.4 Handling Interrupts ................................................................................................................207
20.3.5 Multicast Addressing .............................................................................................................208
20.4 Ethernet Interface Circuit................................................................................................................209
20.5 Register Descriptions......................................................................................................................210

Rabbit 4000 Microprocessor User’s Manual
Chapter 21. Input Capture 219
21.1 Overview........................................................................................................................................219
21.1.1 Input-Capture Mode ..............................................................................................................219
21.1.2 Input-Count Mode .................................................................................................................220
21.1.3 Block Diagram .......................................................................................................................220
21.1.4 Registers ................................................................................................................................221
21.2 Dependencies .................................................................................................................................222
21.2.1 I/O Pins ..................................................................................................................................222
21.2.2 Clocks ....................................................................................................................................222
21.2.3 Other Registers ......................................................................................................................222
21.2.4 Interrupts ................................................................................................................................222
21.3 Operation........................................................................................................................................223
21.3.1 Input-Capture Channel ..........................................................................................................223
21.3.2 Handling Interrupts ................................................................................................................223
21.3.3 Example ISR ..........................................................................................................................223
21.3.4 Capture Mode ........................................................................................................................224
21.3.5 Count Mode ...........................................................................................................................224
21.4 Register Descriptions .....................................................................................................................225
Chapter 22. Quadrature Decoder 231
22.1 Overview........................................................................................................................................231
22.1.1 Block Diagram .......................................................................................................................233
22.1.2 Registers ................................................................................................................................233
22.2 Dependencies .................................................................................................................................234
22.2.1 I/O Pins ..................................................................................................................................234
22.2.2 Clocks ....................................................................................................................................234
22.2.3 Other Registers ......................................................................................................................234
22.2.4 Interrupts ................................................................................................................................234
22.3 Operation........................................................................................................................................235
22.3.1 Handling Interrupts ................................................................................................................235
22.3.2 Example ISR ..........................................................................................................................235
22.4 Register Descriptions .....................................................................................................................236
Chapter 23. Pulse Width Modulator 239
23.1 Overview........................................................................................................................................239
23.1.1 Block Diagram .......................................................................................................................241
23.1.2 Registers ................................................................................................................................241
23.2 Dependencies .................................................................................................................................242
23.2.1 I/O Pins ..................................................................................................................................242
23.2.2 Clocks ....................................................................................................................................242
23.2.3 Other Registers ......................................................................................................................242
23.2.4 Interrupts ................................................................................................................................242
23.3 Operation........................................................................................................................................243
23.3.1 Handling Interrupts ................................................................................................................243
23.3.2 Example ISR ..........................................................................................................................243
23.4 Register Descriptions .....................................................................................................................244
Chapter 24. External I/O Control 247
24.1 Overview........................................................................................................................................247
24.1.1 Auxiliary I/O Bus ..................................................................................................................247
24.1.2 I/O Strobes .............................................................................................................................248
24.1.3 I/O Handshake .......................................................................................................................249
24.1.4 Block Diagram .......................................................................................................................250
24.1.5 Registers ................................................................................................................................250
24.2 Dependencies .................................................................................................................................251
24.2.1 I/O Pins ..................................................................................................................................251
24.2.2 Clocks ....................................................................................................................................251
24.2.3 Other Registers ......................................................................................................................251
24.2.4 Interrupts ................................................................................................................................251

Table of Contents
24.3 Operation ........................................................................................................................................252
24.3.1 Auxiliary I/O Bus ...................................................................................................................252
24.3.2 I/O Strobes .............................................................................................................................252
24.3.3 I/O Handshake ........................................................................................................................252
24.4 Register Descriptions......................................................................................................................253
Chapter 25. Breakpoints 263
25.1 Overview.........................................................................................................................................263
25.1.1 Block Diagram .......................................................................................................................264
25.1.2 Registers .................................................................................................................................265
25.2 Dependencies..................................................................................................................................266
25.2.1 I/O Pins ..................................................................................................................................266
25.2.2 Clocks .....................................................................................................................................266
25.2.3 Other Registers .......................................................................................................................266
25.2.4 Interrupts ................................................................................................................................266
25.3 Operation ........................................................................................................................................266
25.3.1 Handling Interrupts ................................................................................................................266
25.3.2 Example ISR ..........................................................................................................................267
25.4 Register Descriptions......................................................................................................................268
Chapter 26. Low-Power Operation 271
26.1 Overview.........................................................................................................................................271
26.1.1 Registers .................................................................................................................................272
26.2 Operation ........................................................................................................................................273
26.2.1 Unused Pins ............................................................................................................................273
26.2.2 Clock Rates ............................................................................................................................273
26.2.3 Short Chip Selects ..................................................................................................................274
26.2.4 Self-Timed Chip Selects ........................................................................................................279
26.3 Register Descriptions......................................................................................................................280
Chapter 27. System/User Mode 283
27.1 Overview.........................................................................................................................................283
27.1.1 Registers .................................................................................................................................284
27.2 Dependencies..................................................................................................................................285
27.2.1 I/O Pins ..................................................................................................................................285
27.2.2 Clocks .....................................................................................................................................285
27.2.3 Other Registers .......................................................................................................................285
27.2.4 Interrupts ................................................................................................................................286
27.3 Operation ........................................................................................................................................287
27.3.1 Memory Protection Only .......................................................................................................287
27.3.2 Mixed System/User Mode Operation ....................................................................................288
27.3.3 Complete Operating System ..................................................................................................288
27.3.4 Enabling the System/User Mode ............................................................................................289
27.3.5 System/User Mode Instructions .............................................................................................290
27.3.6 System Mode Violation Interrupt ..........................................................................................291
27.3.7 Handling Interrupts in the System/User Mode ......................................................................292
27.4 Register Descriptions......................................................................................................................294
Chapter 28. Specifications 301
28.1 DC Characteristics..........................................................................................................................301
28.2 AC Characteristics..........................................................................................................................303
28.3 Memory Access Times ...................................................................................................................304
28.3.1 Memory Reads .......................................................................................................................304
28.3.2 Memory Writes ......................................................................................................................305
28.3.3 External I/O Reads .................................................................................................................308
28.3.4 External I/O Writes ................................................................................................................309
28.3.5 Memory Access Times ...........................................................................................................311
28.4 Clock Speeds...................................................................................................................................314
28.4.1 Recommended Clock/Memory Configurations .....................................................................314

Rabbit 4000 Microprocessor User’s Manual
28.5 Power and Current Consumption...................................................................................................317
28.5.1 Sleepy Mode Current Consumption ......................................................................................318
28.5.2 Battery-Backed Clock Current Consumption ........................................................................319
Chapter 29. Package Specifications and Pinout 321
29.1 LQFP Package................................................................................................................................321
29.1.1 Pinout .....................................................................................................................................321
29.1.2 Mechanical Dimensions and Land Pattern ............................................................................322
29.2 Ball Grid Array Package................................................................................................................324
29.2.1 Pinout .....................................................................................................................................324
29.2.2 Mechanical Dimensions and Land Pattern ............................................................................325
29.3 Rabbit Pin Descriptions..................................................................................................................327
Appendix A. Parallel Port Pins with Alternate Functions 329
A.1 Alternate Parallel Port Pin Outputs.................................................................................................329
A.2 Alternate Parallel Port Pin Inputs....................................................................................................331
Appendix B. Rabbit 4000 ESD Design Guidelines and Bug Workarounds 333
B.1 ESD Sensitivity................................................................................................................................334
B.1.1 ESD Design Guidelines ..........................................................................................................334
B.2 Bugs.................................................................................................................................................335
Index 339

Chapter 1 The Rabbit 4000 Processor 1
1. THE RABBIT 4000 PROCESSOR
1.1 Introduction
Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in
small- and medium-scale single-board computers. The first microprocessors were the
Rabbit 2000 and the Rabbit 3000. The latest microprocessor is the Rabbit 4000. Rabbit
microprocessor designers have had years of experience using Z80, Z180, and HD64180
microprocessors in small single-board computers. The Rabbit microprocessors share a
similar architecture and a high degree of compatibility with these microprocessors, but
represent a vast improvement.
The Rabbit 4000 is a high-performance microprocessor with low electromagnetic interfer-
ence (EMI), and is designed specifically for embedded control, communications, and
Ethernet connectivity. The 8-bit Rabbit 4000 outperforms most 16–bit processors without
losing the efficiency of an 8–bit architecture. Extensive integrated features and glueless
architecture facilitate rapid hardware design, while a C-friendly instruction set promotes
efficient development of even the most complex applications.
The Rabbit 4000 is fast, running at up to 60 MHz, with compact code and support for up to
16 MB of memory. Operating with a 1.8 V core and 3.3 or 1.8 V I/O, the Rabbit 4000
boasts an internal 10Base-T Ethernet interface, eight channels of DMA, six serial ports with
IrDA, 40+ digital I/O, quadrature decoder, PWM outputs, and pulse capture and measure-
ment capabilities. It also features a battery-backable real-time clock, glueless memory and
I/O interfacing, and ultra-low power modes. Four levels of interrupt priority allow fast
response to real-time events. Its compact instruction set and high clock speeds give the
Rabbit 4000 exceptionally fast math, logic, and I/O performance.
1.2 Features
The Rabbit 4000 has several powerful design features that practically eliminate EMI prob-
lems, which is essential for OEMs that need to pass CE and regulatory radiofrequency
emissions tests. The amplitude of any electromagnetic radiation is reduced by the internal
spectrum spreader, by gated clocks (which prevent unnecessary clocking of unused regis-
ters), and by separate power planes for the processor core and I/O pins (which reduce
noise crosstalk). An auxiliary I/O bus can be used by designers to enable separate buses
for I/O and memory or to limit loading the memory bus to reduce EMI and ground bounce
problems when interfacing external peripherals to the processor. The auxiliary I/O bus
accomplishes this by duplicating the Rabbit's data bus on Parallel Port A, and uses Parallel

2 Rabbit 4000 Microprocessor User’s Manual
Port B to provide the processor's six or eight least significant address lines for interfacing
with external peripherals.
The high-performance instruction set offers both greater efficiency and execution speed of
compiler-generated C code. Instructions include numerous single-byte opcodes that execute
in two clock cycles, 16-bit and 32-bit loads and stores, 16-bit and 32-bit logical and arith-
metic operations, 16 × 16 multiply (executes in 12 clocks), long jumps and returns for
accessing a full 16 megabytes of memory, and one-byte prefixes to turn memory-access
instructions into internal and external I/O instructions. Hardware-supported breakpoints
ease debugging by trapping on code execution or data reads and writes.
The Rabbit 4000 requires no external memory driver or interface-logic. Its 24-bit address
bus, 8-bit or 16-bit data bus, three chip-select lines, two output-enable lines, and two
write-enable lines can be interfaced directly with up to six memory devices. Up to 1 MB
of memory can be accessed directly via the Dynamic C development software, and up to
16 MB can be interfaced with additional software development. A built-in slave port
allows the Rabbit 4000 to be used as master or slave in multi-processor systems, permit-
ting separate tasks to be assigned to dedicated processors. An 8-line data port and five
control signals simplify the exchange of data between devices. A remote cold boot enables
startup and programming via a serial port or the slave port.
The Rabbit 4000 features five 8-bit parallel ports, yielding a total of 40 digital I/O. Six
CMOS-compatible serial ports are available. All six are configurable as asynchronous
(including output pulses in IrDA format), while four are configurable as clocked serial
(SPI) and two are configurable as SDLC/HDLC. The various internal peripherals share the
parallel port’s I/O pins.
The Rabbit 4000 also offers many specialized peripherals. Two input-capture channels
each have a 16-bit counter, clocked by the output of an internal timer, that can be used to
capture and measure pulses. These measurements can be extended to a variety of functions
such as measuring pulse widths or for baud-rate autodetection. Two quadrature decoder
channels each have two inputs, as well as an 8 or 10-bit up/down counter. Each quadrature
decoder channel provides a direct interface to optical encoder units. Four independent pulse-
width modulator (PWM) outputs, each based on a 1024-pulse frame, are driven by the out-
put of a programmable internal timer. The PWM outputs can be filtered to create a 10-bit
D/A converter or they can be used directly to drive devices such as motors or solenoids.
Two external interrupt vectors can multiplex inputs from up to six external pins.
There are numerous timers available for use in the Rabbit 4000. Timer A consists of ten
8-bit counters, each of which has a programmed time constant. Six of them can be cas-
caded from the primary Timer A counter. Timer B contains a 10-bit counter, two match
registers, and two step registers. An interrupt can be generated or the output pin can be
updated when the counter reaches a match value, and the match value is then incremented
automatically by the step value. Timer C is a 16-bit counter that counts up to a program-
mable limit. It contains eight match registers, four to set the output of a parallel-port pin
and four to reset it. This allows for the creation of PWM signals (both synchronous and
variable-phase) and quadrature signals.

Chapter 1 The Rabbit 4000 Processor 3
The Rabbit 4000 also provides support for protected operating systems. Support for two
levels of operation, known as system and user modes, allow application-critical code to
operate in safety while user code is prevented from inadvertently disturbing the setup of
the processor. Memory blocks as small as 4KB can be write-protected against accidental
writes by user code, and stack over/underflows can be trapped by high-priority interrupts.
Security features were also introduced in the Rabbit 4000. Portions of the new instruction
set were introduced to dramatically increase encryption algorithm speeds, and 32 bytes of
battery-backed onchip-encryption RAM store an encryption key away from prying eyes.
The Rabbit 4000 has new peripherals — DMA access and on-chip Ethernet.
The Rabbit 4000 supports eight channels of DMA access to external memory, internal I/O
addresses, and the auxiliary I/O bus. Directing a DMA channel to or from an internal
peripheral such as a serial port or the Ethernet port automatically connects DMA enable
signals. Burst size, priority, and guaranteed cycles for the processor are all under program
control.
The Rabbit 4000 contains a fully featured 10Base-T Ethernet peripheral. Designed to
operate with the DMA peripheral, the Ethernet peripheral is fully compliant with the 802.3
Ethernet standard, including support for auto-negotiation, link detection, multicast filter-
ing, and broadcast addresses. All digital components of the 10Base-T MAC and PHY are
present inside the Rabbit 4000; all that is needed to interface to an Ethernet network is
some simple analog filtering and wave-shaping components.

4 Rabbit 4000 Microprocessor User’s Manual
1.3 Block Diagram
CPU
SYSTEM/USER
External Interface
Data
Buffer
Memory
Management/
Control
Address
Buffer Memory Chip
Interface
Parallel Ports
Port A
Port B
Port C
Port D
Port E
Global Po er
Save & Clock
Distribution
Fast
Clock
Timer A
Timer C
Real-Time
Clock
32.768 kHz
Clock Input
Watchdog
Timer
Periodic
Interrupt
External I/O
Chip Interface
External
Interrupts
/RESET
/IOWR
/IORD /BUFEN
SMODE0
SMODE1
STATUS
/WDTOUT
CLK
DATA BUS
(8 bits)
D[7:0]
(8-b t mode)
or
D[15:0]
(16-b t mode)
A[23:0]
CLKI
CLKIEN
CLK32K
INT0A, INT1A
INT0B, INT1B
/CS2, /CS1, /CS0
/OE1, /OE0
/WE1, /WE0
PA [7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
TXA, RXA, CLKA,
ATXA, ARXA
TXB, RXB, CLKB,
ATXB, ARXB
TXC, RXC, CLKC
TXD, RXD, CLKD
ADDRESS BUS
(15 bits)
RESOUT
Asynch
Serial
Synch
Serial
Asynch
Bootstrap
Synch
Bootstrap
Serial Port A
Asynch Serial IrDA
Serial Ports
B,C,D
Asynch Serial IrDA
Asynch
Serial
Synch
Serial
Serial Ports
E, F
Asynch Serial IrDA
Asynch
Serial
HDLC
SDLC
HDLC/SDLC IrDA
TXE, RXE
TCLKE, RCLKE
Slave Port
Slave Interface
SD[7:0]
SA[1:0],
/SCS, /SRD, /SWR,
/SLAVEATTN
Bootstrap Interface
TXF, RXF
TCLKF, RCLKF
Spectrum
Spreader
Clock
Doubler
Pulse Width
Modulation
PWM[3:0]
Quadrature
Decoder
QD1A, QD1B
QD2A, QD2B
AQD1A, AQD1B
AQD2A, AQD2B
Input
Capture
PC[7,5,3,1]
PD[7,5,3,1]
PE[7,5,3,1]
IrDA Bootstrap
Timer B
DMA
(8 channels)
10Base-T
Ethernet
20 MHz
/LINK, /ACT
RXD[1:0]
TXD[3:0]
DREQ0[B:A]
DREQ1[B:A]
TIMER C[3:0]
Secondary
Watchdog
VBAT RAM
(32 bytes)
battery-
backable
WAIT
ID[7:0]
IA[7:0]
I[7:0]

Chapter 1 The Rabbit 4000 Processor 5
1.4 Basic Specifications
Table 1-1. Rabbit 4000 Specifications and Features
Package 128-pin LQFP 128-ball TFBGA
Package Size 16 mm × 16 mm × 1.5 mm 10 mm × 10 mm × 1.2 mm
Operating Voltage 1.8 V DC core, 3.3 V DC I/O ring
Operating Current 0.35 mA/MHz @ 1.8 V/3.3 V
Operating Temp. -40°C to +85°C
Maximum Clock Speed 60 MHz
Digital I/O 40+ (arranged in five 8-bit ports)
Serial Ports 6 CMOS-compatible
Ethernet Port 10Base-T
Baud Rate Clock speed/8 max. asynchronous
Address Bus 20/24-bit
Data Bus 8/16-bit
Timers Ten 8-bit, one 10-bit with 2 match registers,
and one 16-bit with 8 match registers
Real-Time Clock Yes, battery backable
RTC Oscillator Circuitry External
Watchdog Timer/Supervisor Yes
Clock Modes 1×, 2×, /2, /3, /4, /6, /8
Power-Down Modes Sleepy (32 kHz)
Ultra-Sleepy (16, 8, 2 kHz)
Auxiliary I/O Bus 8 data, 8 address lines

6 Rabbit 4000 Microprocessor User’s Manual
1.5 Comparing Rabbit Microprocessors
The Rabbit 2000, Rabbit 3000, and Rabbit 4000 features are compared below.
Feature Rabbit 4000 Rabbit 3000 Rabbit 2000
Maximum Clock Speed, industrial
Maximum Clock Speed, commercial 60 MHz 60 MHz 55.5 MHz 58.8 MHz 30 MHz 30 MHz
Maximum Crystal Frequency Main
Oscillator (may be doubled internally up
to maximum clock speed) 60 MHz 30 MHz 30 MHz
32.768 kHz Crystal Oscillator External External Internal
Operating Voltage, core
Operation Voltage, I/O
1.8 V ± 10%
3.3 V or 1.8 V
± 10% 3.3 V ± 10% 5.0 V ± 10%
Maximum I/O Input Voltage 3.6 V 5.5 V 5.5 V
Current Consumption 0.35 mA/MHz
@ 3.3 V 2 mA/MHz @ 3.3 V 4 mA/MHz @ 5 V
Number of Package Pins 128 128 100
Size of Package, LQFP/PQFP
Spacing Between Package Pins 16 × 16 × 1.5 mm 0.4 mm (16 mils) 16 × 16 × 1.5 mm 0.4 mm (16 mils) 24 × 18 × 3 mm
0.65 mm (26 mils)
Size of Package, TFBGA
Spacing Between Package Pins 10 × 10 × 1.2 mm 0.8 mm 10 × 10 × 1.2 mm 0.8 mm Not available
Separate Power and Ground for I/O
Buffers (EMI reduction) Yes Yes No
Clock Spectrum Spreader Yes Yes Rabbit 2000B/C
Clock Modes 1×, 2×, /2, /3,
/4, /6, /8 1x, 2x, /2, /3 /4, /6, /8 1x, 2x, /4, /8
Powerdown Modes, sleepy
Powerdown Modes, ultra sleepy 32 kHz 16, 8, 2 kHz 32 kHz 16, 8, 2 kHz 32 kHz
Low-Power Memory Control Short and Self-Timed Chip
Selects
Short and
Self-Timed Chip
Selects None
Extended Memory Timing for High-
Frequency Operation Yes Yes Rabbit 2000C
Number of 8-bit I/O Ports 5 7 5
Auxiliary I/O Data/Address Bus Yes Yes None
Number of Serial Ports 6 6 4
Serial Ports Capable of SPI/Clocked Serial 4 (A, B, C, D) 4 (A, B, C, D) 2 (A, B)
Serial Ports Capable of SDLC/HDLC 2 (E, F) 2 (E, F) None

Chapter 1 The Rabbit 4000 Processor 7
Asynch Serial Ports With Support for
IrDA Communication 66None
Serial Ports with Support for SDLC/
HDLC IrDA Communication 22None
Maximum Asynchronous Baud Rate Clock Speed/8 Clock Speed/8 Clock Speed/32
Ethernet Port 10Base-T None None
Input Capture Units 2 2 None
Feature Rabbit 4000 Rabbit 3000 Rabbit 2000

8 Rabbit 4000 Microprocessor User’s Manual

Chapter 2 Clocks 9
2. CLOCKS
2.1 Overview
The Rabbit 4000 supports up to three separate clocks—the main clock, the 32 kHz clock,
and the 20 MHz Ethernet clock. The main clock is used to derive the processor clock and
the peripheral clock inside the processor. The 32 kHz clock is used to drive the asynchro-
nous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers.
The Rabbit 4000 has a spectrum spreader on the main clock that shortens and lengthens
clock cycles. This has the net effect of reducing the peak energy of clock harmonics by
spreading the spectral energy into nearby frequencies, which reduces EMI and facilitates
government-mandated EMI testing. Gated clocks are used whenever possible to avoid
clocking unused portions of the processor, and separate power-supply pins for the core and
I/O ring further reduce EMI from the Rabbit 4000.
The main clock can be doubled or divided by 2, 4, 6, or 8 to reduce EMI and power con-
sumption. The 32 kHz clock (which can be divided by 2, 4, 8, or 16) can be used instead of
the main clock to generate processor and peripheral clocks as low as 2 kHz for significant
power savings. Note that dividing the 32 kHz clock only affects the processor and periph-
eral clocks; the full 32 kHz signal is still provided to the peripherals (RTC and watchdog
timers) that use it directly. The periodic interrupt is automatically disabled since there is
not enough time to process it when running off the 32 kHz clock.
The Ethernet clock can be driven by the processor clock, the processor clock divided by 2,
or by the input on PE6. The Ethernet clock needs to be 20 MHz to conform to the 10Base-T
specification. See Chapter 20 for more details on the Ethernet clock.

10 Rabbit 4000 Microprocessor User’s Manual
2.1.1 Block Diagram
2.1.2 Registers
Register Name Mnemonic I/O Address R/W Reset
Global Control/Status Register GCSR 0x0000 R/W 11000000
Global Clock Modulator 0 Register GCM0R 0x000A W 00000000
Global Clock Modulation 1 Register GCM1R 0x000B W 00000000
Global Clock Double Register GCDR 0x000F R/W 00000000
NACR
Ethernet
Clock
GCSR
CPU Clock
Peripheral Clock
GOCR
Divide
by 2
CLK Pin
Divide by
2, 4, 6, 8
Divide
by 2
Clock
Doubler
Spectrum
Spreader
CLKI
Divide by
2, 4, 8, 16
CLK32K
Clock
Disable
CLKIEN
PE6
GCMxRGCDR GCSR
GPSCR
Real-Time Clock
Periodic Interrupt
Asynch. Serial Bootstrap
Watchdog Timer
MAIN CLOCK
GCSR