Maxim Dallas Semiconductor DS3171 Operating and maintenance instructions

1 REV: 110206
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
GENERAL DESCRIPTION
The DS3171, DS3172, DS3173, and DS3174
(DS317x) combine a DS3/E3 framer(s) and LIU(s) to
interface to as many as four DS3/E3 physical copper
lines.
APPLICATIONS
Access Concentrators Multiservice Access
Platform (MSAP)
SONET/SDH ADM
and Muxes
PBXs
Multiservice Protocol
Platform (MSPP)
Digital Cross Connect
Test Equipment
PDH Multiplexer/
Demultiplexer
Routers and Switches Integrated Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3171 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3171N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3172 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3172N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3173 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3173N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3174 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3174N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
Note: Add the “+” suffix for the lead-free package option.
FUNCTIONAL DIAGRAM
DS317x
DS3/E3
PORTS
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER SYSTEM
BACKPLANE
FEATURES
 Single (DS3171), Dual (DS3172), Triple
(DS3173), or Quad (DS3174) Single-Chip
Transceiver for DS3 and E3
 All Four Devices are Pin Compatible for Ease of
Port Density Migration in the Same Printed
Circuit Board Platform
 Each Port Independently Configurable
 Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
 Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
 Interfaces to 75ΩCoaxial Cable at Lengths Up to
380 meters, or 1246 feet (DS3) or 440 meters, or
1443 feet (E3)
 Uses 1:2 Transformers on Both Tx and Rx
 On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s)
 Ports Independently Configurable for DS3, E3
 Built-In HDLC Controllers with 256-Byte FIFOs
for the Insertion/Extraction of DS3 PMDL, G.751
Sn Bit, and G.832 NR/GC Bytes
 On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis
 Large Performance-Monitoring Counters for
Accumulation Intervals of at Least 1 Second
 Flexible Overhead Insertion/Extraction Ports for
DS3, E3 Framers
DS3171/DS3172/DS3173/DS3174
Single/Dual/Triple/Quad
DS3/E3 Single-Chip Transceivers
www.maxim-ic.com

DS3171/DS3172/DS3173/DS3174
2
FEATURES (CONTINUED)
 Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
 Ports can be Disabled to Reduce Power
 Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single Clock
Reference Source at One of Three Standard
Frequencies (DS3, E3, STS-1)
 Pin Compatible with the DS318x Family of
Devices and the DS316x Family of Devices
 8-/16-Bit Generic Microprocessor Interface
 Low-Power (~1.73W) 3.3V Operation (5V
Tolerant I/O)
 Small High-Density Thermally Enhanced Plastic
BGA Packaging (TE-PBGA) with 1.27mm Pitch
 Industrial Temperature Operation:
-40°C to +85°C
 IEEE1149.1 JTAG Test Port
DETAILED DESCRIPTION
The DS3171 (single), DS3172 (dual), DS3173 (triple), and DS3174 (quad) perform framing, formatting, and line
transmission and reception. These devices contain integrated LIU(s), framer/formatter for M23 DS3, C-bit DS3,
G.751 E3, G.832 E3, or a combination of the above signal formats.
Each LIU has independent receive and transmit paths. The receiver LIU block performs clock and data recovery
from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal, or can be bypassed for
direct clock and data inputs. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU
drives standard pulse-shape waveforms onto 75Ωcoaxial cable or can be bypassed for direct clock and data
outputs. The jitter attenuator can be placed in either transmit or receive data path when the LIU is enabled. The
DS3/E3 framers transmit and receive serial data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or G.832 E3
data streams. Unused functions can be powered down to reduce device power. The DS317x DS3/E3 SCTs
conform to the telecommunications standards listed in Section 4.

DS3171/DS3172/DS3173/DS3174
3
1 BLOCK DIAGRAMS
Figure 1-1 shows the external components required at each LIU interface for proper operation. Figure 1-2 shows
the functional block diagram of one channel DS3/E3 LIU.
Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device
1:2ct
1:2ct
Transmit
Receive
TXP
TXN
RXP
RXN
0.01uF 3.3V
Power
Plane
Ground
Plane
VDD
Each DS3/E3 LIU Interface
0.1uF 1uF
330
Ω
(1%)
330
Ω
(1%)
0.01uF 0.1uF 1uF
0.01uF 0.1uF 1uF
VDD
VDD
VSS
VSS
VSS
Figure 1-2. DS317x Functional Block Diagram
RLCLKn
RXPn
RXNn
TPOSn/TDATn
TNEGn
TLCLKn
Microprocessor
Interface
TXPn
TXNn
RDATn
RNEGn/ RLCVn
RST
n = port # (1-4)
D[15:0]
A[10:1]
ALE
CS
RD/DS
WR/ R/W
MODE
INT
GPIO[8:1]
WIDTH
RDY
A[0]/BSWAP
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
JTDO
JTCLK
JTMS
JTDI
JTRST
HDLC
FEAC
LLB
DLB
DS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
Trail
Trace
Buffer
ROHn
ROHCLKn
ROHSOFn
TCLKIn
RSERn
RCLKOn/RGCLKn
RSOFOn/RDENn
DS3/E3
Receive
LIU
TAIS
TUA1
Clock Rate
Adapter
CLKA
CLKB
CLKC
PLB
ALB
UA1
GEN
TSERn
B3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder
TSOFIn
TX BERT
RX BERT
TSOFOn/TDENn
TOHn
TOHCLKn TOHSOFn
TOHENn
TCLKOn/TGCLKn
DS317x

DS3171/DS3172/DS3173/DS3174
4
TABLE OF CONTENTS
1BLOCK DIAGRAMS 3
2APPLICATIONS 12
3FEATURE DETAILS 13
3.1 GLOBAL FEATURES........................................................................................................................................ 13
3.2 RECEIVE DS3/E3 LIU FEATURES .................................................................................................................. 13
3.3 RECEIVE DS3/E3 FRAMER FEATURES............................................................................................................ 13
3.4 TRANSMIT DS3/E3 FORMATTER FEATURES.................................................................................................... 13
3.5 TRANSMIT DS3/E3 LIU FEATURES ................................................................................................................ 14
3.6 JITTER ATTENUATOR FEATURES..................................................................................................................... 14
3.7 CLOCK RATE ADAPTER FEATURES ................................................................................................................. 14
3.8 HDLC OVERHEAD CONTROLLER FEATURES ................................................................................................... 14
3.9 FEAC CONTROLLER FEATURES..................................................................................................................... 14
3.10 TRAIL TRACE BUFFER FEATURES ................................................................................................................... 15
3.11 BIT ERROR RATE TESTER (BERT) FEATURES ................................................................................................ 15
3.12 LOOPBACK FEATURES ................................................................................................................................... 15
3.13 MICROPROCESSOR INTERFACE FEATURES...................................................................................................... 15
3.14 TEST FEATURES ............................................................................................................................................ 15
4STANDARDS COMPLIANCE 16
5ACRONYMS AND GLOSSARY 17
6MAJOR OPERATIONAL MODES 18
6.1 DS3/E3 SCT MODE ..................................................................................................................................... 18
6.2 DS3/E3 CLEAR CHANNEL MODE ................................................................................................................... 20
7MAJOR LINE INTERFACE OPERATING MODES 21
7.1 DS3HDB3/B3ZS/AMI LIU MODE ................................................................................................................. 21
7.2 HDB3/B3ZS/AMI NON-LIU LINE INTERFACE MODE ....................................................................................... 23
7.3 UNI LINE INTERFACE MODE........................................................................................................................... 24
8PIN DESCRIPTIONS 25
8.1 SHORT PIN DESCRIPTIONS............................................................................................................................. 25
8.2 DETAILED PIN DESCRIPTIONS......................................................................................................................... 28
8.3 PIN FUNCTIONAL TIMING ................................................................................................................................36
8.3.1 Line IO.................................................................................................................................................. 36
8.3.2 DS3/E3 Framing Overhead Functional Timing .................................................................................... 39
8.3.3 DS3/E3 Serial Data Interface............................................................................................................... 40
8.3.4 Microprocessor Interface Functional Timing ........................................................................................ 42
8.3.5 JTAG Functional Timing....................................................................................................................... 47
9INITIALIZATION AND CONFIGURATION 48
9.1 MONITORING AND DEBUGGING ....................................................................................................................... 49
10 FUNCTIONAL DESCRIPTION 50
10.1 PROCESSOR BUS INTERFACE......................................................................................................................... 50
10.1.1 8/16 Bit Bus Widths.............................................................................................................................. 50
10.1.2 Ready Signal ( RDY ) ............................................................................................................................. 50
10.1.3 Byte Swap Modes ................................................................................................................................ 50
10.1.4 Read-Write / Data Strobe Modes......................................................................................................... 50
10.1.5 Clear on Read / Clear on Write Modes ................................................................................................ 50
10.1.6 Global Write Method ............................................................................................................................ 51
10.1.7 Interrupt and Pin Modes....................................................................................................................... 51
10.1.8 Interrupt Structure ................................................................................................................................ 51
10.2 CLOCKS ........................................................................................................................................................ 52
10.2.1 Line Clock Modes................................................................................................................................. 52

DS3171/DS3172/DS3173/DS3174
5
10.2.2 Sources of Clock Output Pin Signals................................................................................................... 54
10.2.3 Line IO Pin Timing Source Selection ................................................................................................... 57
10.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 59
10.2.5 Gapped Clocks..................................................................................................................................... 60
10.3 RESET AND POWER-DOWN ............................................................................................................................ 60
10.4 GLOBAL RESOURCES..................................................................................................................................... 63
10.4.1 Clock Rate Adapter (CLAD)................................................................................................................. 63
10.4.2 8 kHz Reference Generation ............................................................................................................... 64
10.4.3 One Second Reference Generation..................................................................................................... 66
10.4.4 General-Purpose IO Pins..................................................................................................................... 66
10.4.5 Performance Monitor Counter Update Details..................................................................................... 67
10.4.6 Transmit Manual Error Insertion .......................................................................................................... 68
10.5 PER PORT RESOURCES ................................................................................................................................. 69
10.5.1 Loopbacks............................................................................................................................................ 69
10.5.2 Loss Of Signal Propagation ................................................................................................................. 71
10.5.3 AIS Logic.............................................................................................................................................. 71
10.5.4 Loop Timing Mode ............................................................................................................................... 74
10.5.5 HDLC Overhead Controller.................................................................................................................. 74
10.5.6 Trail Trace ............................................................................................................................................ 74
10.5.7 BERT.................................................................................................................................................... 74
10.5.8 SCT port pins ....................................................................................................................................... 74
10.5.9 Framing Modes .................................................................................................................................... 76
10.5.10 Line Interface Modes............................................................................................................................ 76
10.6 DS3/E3 FRAMER / FORMATTER ..................................................................................................................... 78
10.6.1 General Description ............................................................................................................................. 78
10.6.2 Features ............................................................................................................................................... 78
10.6.3 Transmit Formatter............................................................................................................................... 79
10.6.4 Receive Framer.................................................................................................................................... 79
10.6.5 C-Bit DS3 Framer/Formatter................................................................................................................ 83
10.6.6 M23 DS3 Framer/Formatter................................................................................................................. 86
10.6.7 G.751 E3 Framer/Formatter................................................................................................................. 88
10.6.8 G.832 E3 Framer/Formatter................................................................................................................. 90
10.7 HDLC OVERHEAD CONTROLLER.................................................................................................................... 96
10.7.1 General Description ............................................................................................................................. 96
10.7.2 Features ............................................................................................................................................... 96
10.7.3 Transmit FIFO ...................................................................................................................................... 97
10.7.4 Transmit HDLC Overhead Processor .................................................................................................. 97
10.7.5 Receive HDLC Overhead Processor ................................................................................................... 98
10.7.6 Receive FIFO ....................................................................................................................................... 98
10.8 TRAIL TRACE CONTROLLER............................................................................................................................ 99
10.8.1 General Description ............................................................................................................................. 99
10.8.2 Features ............................................................................................................................................... 99
10.8.3 Functional Description........................................................................................................................ 100
10.8.4 Transmit Data Storage....................................................................................................................... 100
10.8.5 Transmit Trace ID Processor ............................................................................................................. 100
10.8.6 Transmit Trail Trace Processing ........................................................................................................ 100
10.8.7 Receive Trace ID Processor .............................................................................................................. 100
10.8.8 Receive Trail Trace Processing ......................................................................................................... 101
10.8.9 Receive Data Storage ........................................................................................................................ 101
10.9 FEAC CONTROLLER ................................................................................................................................... 102
10.9.1 General Description ........................................................................................................................... 102
10.9.2 Features ............................................................................................................................................. 102
10.9.3 Functional Description........................................................................................................................ 102
10.10 LINE ENCODER/DECODER............................................................................................................................ 104
10.10.1 General Description ........................................................................................................................... 104
10.10.2 Features ............................................................................................................................................. 104
10.10.3 B3ZS/HDB3 Encoder ......................................................................................................................... 104

DS3171/DS3172/DS3173/DS3174
6
10.10.4 Transmit Line Interface ...................................................................................................................... 105
10.10.5 Receive Line Interface ....................................................................................................................... 105
10.10.6 B3ZS/HDB3 Decoder ......................................................................................................................... 105
10.11 BERT......................................................................................................................................................... 107
10.11.1 General Description ........................................................................................................................... 107
10.11.2 Features ............................................................................................................................................. 107
10.11.3 Configuration and Monitoring............................................................................................................. 107
10.11.4 Receive Pattern Detection ................................................................................................................. 108
10.11.5 Transmit Pattern Generation.............................................................................................................. 110
10.12 LIU—LINE INTERFACE UNIT......................................................................................................................... 111
10.12.1 General Description ........................................................................................................................... 111
10.12.2 Features ............................................................................................................................................. 111
10.12.3 Detailed Description ........................................................................................................................... 112
10.12.4 Transmitter ......................................................................................................................................... 112
10.12.5 Receiver ............................................................................................................................................. 113
11 OVERALL REGISTER MAP 116
12 REGISTER MAPS AND DESCRIPTIONS 119
12.1 REGISTERS BIT MAPS.................................................................................................................................. 119
12.1.1 Global Register Bit Map ..................................................................................................................... 119
12.1.2 HDLC Register Bit Map...................................................................................................................... 122
12.1.3 T3 Register Bit Map ........................................................................................................................... 124
12.1.4 E3 G.751 Register Bit Map ................................................................................................................ 124
12.1.5 E3 G.832 Register Bit Map ................................................................................................................ 125
12.1.6 Clear Channel Register Bit Map ........................................................................................................ 126
12.2 GLOBAL REGISTERS .................................................................................................................................... 127
12.2.1 Register Bit Descriptions.................................................................................................................... 127
12.3 PER PORT COMMON.................................................................................................................................... 134
12.3.1 Register Bit Descriptions.................................................................................................................... 134
12.4 BERT......................................................................................................................................................... 144
12.4.1 BERT Register Map ........................................................................................................................... 144
12.4.2 BERT Register Bit Descriptions ......................................................................................................... 144
12.5 B3ZS/HDB3 LINE ENCODER/DECODER ....................................................................................................... 152
12.5.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 152
12.5.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 153
12.6 HDLC......................................................................................................................................................... 157
12.6.1 HDLC Transmit Side Register Map.................................................................................................... 157
12.6.2 HDLC Receive Side Register Map..................................................................................................... 161
12.7 FEAC CONTROLLER ................................................................................................................................... 165
12.7.1 FEAC Transmit Side Register Map.................................................................................................... 165
12.7.2 FEAC Receive Side Register Map..................................................................................................... 167
12.8 TRAIL TRACE............................................................................................................................................... 170
12.8.1 Trail Trace Transmit Side................................................................................................................... 170
12.8.2 Trail Trace Receive Side Register Map ............................................................................................. 172
12.9 DS3/E3 FRAMER ........................................................................................................................................ 176
12.9.1 Transmit DS3 ..................................................................................................................................... 176
12.9.2 Receive DS3 Register Map................................................................................................................ 178
12.9.3 Transmit G.751 E3 ............................................................................................................................. 187
12.9.4 Receive G.751 E3 Register Map ....................................................................................................... 189
12.9.5 Transmit G.832 E3 Register Map ...................................................................................................... 195
12.9.6 Receive G.832 E3 Register Map ....................................................................................................... 198
12.9.7 Transmit Clear Channel ..................................................................................................................... 207
12.9.8 Receive Clear Channel ...................................................................................................................... 208
13 JTAG INFORMATION 210
13.1 JTAG DESCRIPTION .................................................................................................................................... 210
13.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................................. 211
13.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................................... 213

DS3171/DS3172/DS3173/DS3174
7
13.4 JTAG ID CODES......................................................................................................................................... 214
13.5 JTAG FUNCTIONAL TIMING.......................................................................................................................... 214
13.6 IO PINS ...................................................................................................................................................... 214
14 PIN ASSIGNMENTS 215
15 PACKAGE INFORMATION 218
15.1 400-LEAD TE-PBGA (27MM X 27MM, 1.27MM PITCH) (56-G6003-003) ....................................................... 218
16 PACKAGE THERMAL INFORMATION 219
17 DC ELECTRICAL CHARACTERISTICS 220
18 AC TIMING CHARACTERISTICS 222
18.1 FRAMER AC CHARACTERISTICS ................................................................................................................... 224
18.2 LINE INTERFACE AC CHARACTERISTICS ....................................................................................................... 224
18.3 MISC PIN AC CHARACTERISTICS.................................................................................................................. 225
18.4 OVERHEAD PORT AC CHARACTERISTICS...................................................................................................... 225
18.5 MICRO INTERFACE AC CHARACTERISTICS .................................................................................................... 226
18.6 CLAD JITTER CHARACTERISTICS ................................................................................................................. 229
18.7 LIU INTERFACE AC CHARACTERISTICS ........................................................................................................ 229
18.7.1 Waveform Templates ......................................................................................................................... 229
18.7.2 LIU Input/Output Characteristics........................................................................................................ 231
18.8 JTAG INTERFACE AC CHARACTERISTICS ..................................................................................................... 233
19 REVISION HISTORY 234

DS3171/DS3172/DS3173/DS3174
8
LIST OF FIGURES
Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device ........................................................... 3
Figure 1-2. DS317x Functional Block Diagram ........................................................................................................... 3
Figure 2-1. Four-Port DS3/E3 Line Card ................................................................................................................... 12
Figure 6-1. DS3/E3 SCT Mode.................................................................................................................................. 19
Figure 6-2. DS3/E3 Clear Channel Mode.................................................................................................................. 20
Figure 7-1. HDB3/B3ZS/AMI LIU Mode..................................................................................................................... 22
Figure 7-2. HDB3/B3ZS/AMI Non-LIU Line Interface Mode...................................................................................... 23
Figure 7-3. UNI Line Interface Mode ......................................................................................................................... 24
Figure 8-1. TX Line IO B3ZS Functional Timing Diagram......................................................................................... 36
Figure 8-2. TX Line IO HDB3 Functional Timing Diagram ........................................................................................ 37
Figure 8-3. RX Line IO B3ZS Functional Timing Diagram......................................................................................... 37
Figure 8-4. RX Line IO HDB3 Functional Timing Diagram ........................................................................................ 38
Figure 8-5. TX Line IO UNI Functional Timing Diagram............................................................................................ 38
Figure 8-6. RX Line IO UNI Functional Timing Diagram ........................................................................................... 39
Figure 8-7. DS3 Framing Receive Overhead Port Timing......................................................................................... 39
Figure 8-8. E3 G.751 Framing Receive Overhead Port Timing ................................................................................ 39
Figure 8-9. E3 G.832 Framing Receive Overhead Port Timing ................................................................................ 39
Figure 8-10. DS3 Framing Transmit Overhead Port Timing...................................................................................... 40
Figure 8-11. E3 G.751 Framing Transmit Overhead Port Timing ............................................................................. 40
Figure 8-12. E3 G.832 Framing Transmit Overhead Port Timing ............................................................................. 40
Figure 8-13. DS3 SCT Mode Transmit Serial Interface Pin Timing........................................................................... 41
Figure 8-14. E3 G.751 SCT Mode Transmit Serial Interface Pin Timing .................................................................. 41
Figure 8-15. E3 G.832 SCT Mode Transmit Serial Interface Pin Timing .................................................................. 41
Figure 8-16. DS3 SCT Mode Receive Serial Interface Pin Timing............................................................................ 42
Figure 8-17. E3 G.751 SCT Mode Receive Serial Interface Pin Timing ................................................................... 42
Figure 8-18. E3 G.832 SCT Mode Receive Serial Interface Pin Timing ................................................................... 42
Figure 8-19. 16-Bit Mode Write.................................................................................................................................. 43
Figure 8-20. 16-Bit Mode Read ................................................................................................................................. 43
Figure 8-21. 8-Bit Mode Write.................................................................................................................................... 44
Figure 8-22. 8-Bit Mode Read ................................................................................................................................... 44
Figure 8-23. 16-Bit Mode without Byte Swap ............................................................................................................ 45
Figure 8-24. 16-Bit Mode with Byte Swap ................................................................................................................. 45
Figure 8-25. Clear Status Latched Register on Read................................................................................................ 46
Figure 8-26. Clear Status Latched Register on Write................................................................................................ 46
Figure 8-27. RDY Signal Functional Timing Write..................................................................................................... 47
Figure 8-28. RDY Signal Functional Timing Read..................................................................................................... 47
Figure 10-1. Interrupt Structure ................................................................................................................................. 52
Figure 10-2. Internal TX Clock................................................................................................................................... 55
Figure 10-3. Internal RX Clock .................................................................................................................................. 56
Figure 10-4. Example IO Pin Clock Muxing............................................................................................................... 60
Figure 10-5. Reset Sources....................................................................................................................................... 61
Figure 10-6. CLAD Block ........................................................................................................................................... 63
Figure 10-7. 8KREF Logic ......................................................................................................................................... 65
Figure 10-8. Performance Monitor Update Logic ...................................................................................................... 68
Figure 10-9. Transmit Error Insert Logic.................................................................................................................... 69
Figure 10-10. Loopback Modes ................................................................................................................................. 70
Figure 10-11. ALB Mux.............................................................................................................................................. 70
Figure 10-12. AIS Signal Flow ................................................................................................................................... 73
Figure 10-13. Framer Detailed Block Diagram .......................................................................................................... 78
Figure 10-14. DS3 Frame Format.............................................................................................................................. 80
Figure 10-15. DS3 Subframe Framer State Diagram................................................................................................ 80
Figure 10-16. DS3 Multiframe Framer State Diagram............................................................................................... 81
Figure 10-17. G.751 E3 Frame Format ..................................................................................................................... 88
Figure 10-18. G.832 E3 Frame Format ..................................................................................................................... 91
Figure 10-19. MA Byte Format .................................................................................................................................. 91

DS3171/DS3172/DS3173/DS3174
9
Figure 10-20. HDLC Controller Block Diagram ......................................................................................................... 96
Figure 10-21. Trail Trace Controller Block Diagram .................................................................................................. 99
Figure 10-22. Trail Trace Byte (DT = Trail Trace Data)........................................................................................... 101
Figure 10-23. FEAC Controller Block Diagram........................................................................................................ 102
Figure 10-24. FEAC Codeword Format ................................................................................................................... 103
Figure 10-25. Line Encoder/Decoder Block Diagram.............................................................................................. 104
Figure 10-26. B3ZS Signatures ............................................................................................................................... 106
Figure 10-27. HDB3 Signatures............................................................................................................................... 106
Figure 10-28. BERT Block Diagram ........................................................................................................................ 107
Figure 10-29. PRBS Synchronization State Diagram.............................................................................................. 109
Figure 10-30. Repetitive Pattern Synchronization State Diagram........................................................................... 110
Figure 10-31. LIU Functional Diagram..................................................................................................................... 111
Figure 10-32. DS3/E3 LIU Block Diagram............................................................................................................... 112
Figure 10-33. Receiver Jitter Tolerance .................................................................................................................. 115
Figure 13-1. JTAG Block Diagram........................................................................................................................... 210
Figure 13-2. JTAG TAP Controller State Machine .................................................................................................. 211
Figure 13-3. JTAG Functional Timing...................................................................................................................... 214
Figure 14-1. DS3174 Pin Assignments—400-Lead PBGA ..................................................................................... 215
Figure 14-2. DS3173 Pin Assignments—400-Lead PBGA ..................................................................................... 216
Figure 14-3. DS3172 Pin Assignments—400-Lead PBGA ..................................................................................... 216
Figure 14-4. DS3171 Pin Assignments—400-Lead PBGA ..................................................................................... 217
Figure 18-1. Clock Period and Duty Cycle Definitions............................................................................................. 222
Figure 18-2. Rise Time, Fall Time, and Jitter Definitions......................................................................................... 222
Figure 18-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 222
Figure 18-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 223
Figure 18-5. To/From Hi Z Delay Definitions (Rising Clock Edge) .......................................................................... 223
Figure 18-6. To/From Hi Z Delay Definitions (Falling Clock Edge) ......................................................................... 223
Figure 18-7. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 227
Figure 18-8. Micro Interface Multiplexed Read Cycle.............................................................................................. 228
Figure 18-9. E3 Waveform Template....................................................................................................................... 230
Figure 18-10. DS3 Pulse Mask Template................................................................................................................ 231

DS3171/DS3172/DS3173/DS3174
10
LIST OF TABLES
Table 4-1. Standards Compliance ............................................................................................................................. 16
Table 7-1. HDB3/B3ZS/AMI LIU Mode Configuration Registers ............................................................................... 21
Table 7-2. HDB3/B3ZS/AMI Non-LIU Mode Configuration Registers ....................................................................... 23
Table 7-3. UNI Line Interface Mode Configuration Registers.................................................................................... 24
Table 8-1. DS3174 Short Pin Descriptions................................................................................................................ 25
Table 8-2. Detailed Pin Descriptions ......................................................................................................................... 28
Table 9-1. Configuration of Port Register Settings .................................................................................................... 49
Table 10-1. LIU Enable Table.................................................................................................................................... 54
Table 10-2. All Possible Clock Sources Based on Mode and Loopback................................................................... 54
Table 10-3. Source Selection of TLCLK Clock Signal ............................................................................................... 55
Table 10-4. Source Selection of TCLKOn (internal TX clock) ................................................................................... 56
Table 10-5. Source Selection of RCLKO Clock Signal (internal RX clock) ............................................................... 56
Table 10-6. Transmit Line Interface Signal Pin Valid Timing Source Select ............................................................. 57
Table 10-7. Transmit Framer Pin Signal Timing Source Select ................................................................................ 58
Table 10-8. Receive Line Interface Pin Signal Timing Source Select ....................................................................... 58
Table 10-9. Receive Framer Pin Signal Timing Source Select ................................................................................. 59
Table 10-10. Reset and Power-Down Sources ......................................................................................................... 62
Table 10-11. CLAD IO Pin Decode............................................................................................................................ 64
Table 10-12. Global 8 kHz Reference Source Table................................................................................................. 65
Table 10-13. Port 8 kHz Reference Source Table..................................................................................................... 65
Table 10-14. GPIO Global Signals ............................................................................................................................ 66
Table 10-15. GPIO Pin Global Mode Select Bits....................................................................................................... 66
Table 10-16. GPIO Port Alarm Monitor Select .......................................................................................................... 67
Table 10-17. Loopback Mode Selections .................................................................................................................. 69
Table 10-18. Line AIS Enable Modes........................................................................................................................ 73
Table 10-19. Payload (Downstream) AIS Enable Modes.......................................................................................... 74
Table 10-20. TSOFIn Input Pin Functions ................................................................................................................. 75
Table 10-21. TSOFOn/TDENn/Output Pin Functions................................................................................................ 75
Table 10-22. TCLKOn/TGCLKn Output Pin Functions.............................................................................................. 75
Table 10-23. RSOFOn/RDENn Output Pin Functions............................................................................................... 75
Table 10-24. RCLKOn/RGCLKn Output Pin Functions............................................................................................. 76
Table 10-25. Framing Mode Select Bits FM[2:0] ....................................................................................................... 76
Table 10-26. Line Mode Select Bits LM[2:0].............................................................................................................. 77
Table 10-27. C-Bit DS3 Frame Overhead Bit Definitions .......................................................................................... 83
Table 10-28. M23 DS3 Frame Overhead Bit Definitions ........................................................................................... 86
Table 10-29. G.832 E3 Frame Overhead Bit Definitions........................................................................................... 91
Table 10-30. Payload Label Match Status................................................................................................................. 95
Table 10-31. Pseudorandom Pattern Generation.................................................................................................... 108
Table 10-32. Repetitive Pattern Generation ............................................................................................................ 108
Table 10-33. Transformer Characteristics ............................................................................................................... 113
Table 10-34. Recommended Transformers............................................................................................................. 114
Table 11-1. Global and Test Register Address Map ............................................................................................... 117
Table 11-2. Per Port Register Address Map............................................................................................................ 118
Table 12-1. Global Register Bit Map........................................................................................................................ 119
Table 12-2. Port Register Bit Map ........................................................................................................................... 120
Table 12-3. BERT Register Bit Map ........................................................................................................................ 120
Table 12-4. Line Register Bit Map ........................................................................................................................... 121
Table 12-5. HDLC Register Bit Map ........................................................................................................................ 122
Table 12-6. FEAC Register Bit Map ........................................................................................................................ 122
Table 12-7. Trail Trace Register Bit Map................................................................................................................. 123
Table 12-8. T3 Register Bit Map.............................................................................................................................. 124
Table 12-9. E3 G.751 Register Bit Map................................................................................................................... 124
Table 12-10. E3 G.832 Register Bit Map................................................................................................................. 125
Table 12-11. Clear Channel Register Bit Map......................................................................................................... 126
Table 12-12. Global Register Map........................................................................................................................... 127

DS3171/DS3172/DS3173/DS3174
11
Table 12-13. Per Port Common Register Map ........................................................................................................ 134
Table 12-14. BERT Register Map............................................................................................................................ 144
Table 12-15. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 152
Table 12-16. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 153
Table 12-17. Transmit Side HDLC Register Map .................................................................................................... 157
Table 12-18. Receive Side HDLC Register Map ..................................................................................................... 161
Table 12-19. FEAC Transmit Side Register Map .................................................................................................... 165
Table 12-20. FEAC Receive Side Register Map ..................................................................................................... 167
Table 12-21. Transmit Side Trail Trace Register Map............................................................................................. 170
Table 12-22. Trail Trace Receive Side Register Map.............................................................................................. 172
Table 12-23. Transmit DS3 Framer Register Map .................................................................................................. 176
Table 12-24. Receive DS3 Framer Register Map ................................................................................................... 178
Table 12-25. Transmit G.751 E3 Framer Register Map .......................................................................................... 187
Table 12-26. Receive G.751 E3 Framer Register Map ........................................................................................... 189
Table 12-27. Transmit G.832 E3 Framer Register Map .......................................................................................... 195
Table 12-28. Receive G.832 E3 Framer Register Map ........................................................................................... 198
Table 12-29. Transmit Clear Channel Register Map ............................................................................................... 207
Table 12-30. Receive Clear Channel Register Map ................................................................................................ 208
Table 13-1. JTAG Instruction Codes ....................................................................................................................... 213
Table 13-2. JTAG ID Codes .................................................................................................................................... 214
Table 14-1. Pin Assignment Breakdown ................................................................................................................. 215
Table 17-1. Recommended DC Operating Conditions ............................................................................................ 220
Table 17-2. DC Electrical Characteristics................................................................................................................ 220
Table 17-3. Output Pin Drive ................................................................................................................................... 221
Table 18-1. Framer Port Timing............................................................................................................................... 224
Table 18-2. Line Interface Timing ............................................................................................................................ 224
Table 18-3. Misc Pin Timing .................................................................................................................................... 225
Table 18-4. Overhead Port Timing .......................................................................................................................... 225
Table 18-5. Micro Interface Timing .......................................................................................................................... 226
Table 18-6. DS3 Waveform Template ..................................................................................................................... 229
Table 18-7. DS3 Waveform Test Parameters and Limits ........................................................................................ 229
Table 18-8. E3 Waveform Test Parameters and Limits........................................................................................... 230
Table 18-9. Receiver Input Characteristics—DS3 Mode......................................................................................... 231
Table 18-10. Receiver Input Characteristics—E3 Mode ......................................................................................... 232
Table 18-11. Transmitter Output Characteristics—DS3 Modes .............................................................................. 232
Table 18-12. Transmitter Output Characteristics—E3 Mode .................................................................................. 232
Table 18-13. JTAG Interface Timing........................................................................................................................ 233

DS3171/DS3172/DS3173/DS3174
12
2 APPLICATIONS
• Access Concentrators
• Multiservice Access Platforms
• ATM and Frame Relay Equipment
• Routers and Switches
• SONET/SDH ADM
• SONET/SDH Muxes
• PBXs
• Digital Cross Connect
• PDH Multiplexer/Demultiplexer
• Test Equipment
• Integrated Access Device (IAD)
Figure 2-1 shows an application for the DS3174.
Figure 2-1. Four-Port DS3/E3 Line Card
Digital Cross
Connect (DCS)
DS3174
Quad
DS3/E3
SCT
T3/E3
Trans-
formers
Four
DS3/E3
Lines
DS3/E 3
Backplane
Signals
T3/E3 Line Card (#1)
DS31 74
Quad
DS3/E3
SCT
T3/E3
Trans-
formers
Four
DS3/E3
Lines
T3/E3 Line Card (#n)
DS3/E3
Backplane
Signals
DS3174
Quad
DS3/E3
SCT
T3/E3
Trans-
formers
T3/E3 Line Card (#n+1)
DS3/E3
Backplane
Singals
DS3174
Quad
DS3/E3
SCT
T3/E3
Trans-
formers
T3/E3 Line Card (#n+n)

DS3171/DS3172/DS3173/DS3174
13
3 FEATURE DETAILS
The following sections describe the features provided by the DS3171 (single), DS3172 (dual), DS3173 (triple), and
DS3174 (quad) single-chip transceivers (framers and LIUs, SCTs).
3.1 Global Features
• Supports the following transmission protocols:
• C-bit DS3
• M23 DS3
• G.751 E3
• G.832 E3
• Clear-channel serial data at line rates up to 52 Mbits/s
• Optional transmit loop timed clock(s) mode using the associated port’s receive clock(s)
• Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
• Requires only a single reference clock for all three LIU data rates using internal CLAD
• The LIU can be powered down and bypassed for direct logic IO to/from line circuits.
• Jitter attenuator can be placed in either transmit or receive path when the LIU is enabled.
• Clock, data and control signals can be inverted for a direct interface to many other devices
• Detection of loss of transmit clock and loss of receive clock
• Automatic one-second, external or manual update of performance monitoring counters
• Each port can be placed into a low-power standby mode when not being used
• Framing and line code error insertion available
3.2 Receive DS3/E3 LIU Features
• AGC/Equalizer block handles from 0 dB to 15 dB of cable loss
• Loss-of-lock PLL status indication
• Interfaces directly to a DSX monitor signal (20 dB flat loss) using built-in pre-amp
• Digital and analog Loss of Signal (LOS) detectors (ANSI T1.231 and ITU G.775)
• Per-channel power-down control
3.3 Receive DS3/E3 Framer Features
• Frame synchronization for M23 or C-bit Parity DS3, or G.751 E3 or G.832 E3
• B3ZS/HDB3/AMI decoding
• Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeros occurrences
(EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
errors, and far end block errors (FEBE)
• Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of
frame alignment (COFA), receipt of B3ZS/HDB3 codewords, DS3 application ID bit, DS3 M23/C-bit format
mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
• HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
• FEAC port for DS3 FEAC channel
• 16-byte Trail Trace Buffer port for G.832 trail access point identifier
• DS3 M23 C bits and stuff bits configurable as payload or overhead, stored in registers for software inspection
• Most framing overhead fields presented on the receive overhead port
3.4 Transmit DS3/E3 Formatter Features
• Insertion of framing overhead for M23 or C-bit parity DS3, or G.751 E3 or G.832 E3
• B3ZS/HDB3 encoding
• Generation of RDI, AIS, and DS3 idle signal
• Automatic or manual insertion of bipolar violations (BPVs), excessive zeros (EXZ) occurrences, F-bit errors, M-
bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)
• HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels

DS3171/DS3172/DS3173/DS3174
14
• FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or
two different codewords back-to-back to send DS3 Line Loopback commands
• 16-byte Trail Trace Buffer port for the G.832 trail access point identifier
• Insertion of G.832 payload type, and timing marker bits from registers
• DS3 M23 C bits configurable as payload or overhead, as overhead they can be controlled from registers or the
transmit overhead port
• Most framing overhead fields can be sourced from transmit overhead port
• Formatter bypass mode for clear channel or externally defined format applications
3.5 Transmit DS3/E3 LIU Features
• Wide 50+20% transmit clock duty cycle
• Line Build-Out (LBO) control
• Tri-state line driver outputs support protection switching applications
• Per-channel power-down control
• Output driver monitor status indication
3.6 Jitter Attenuator Features
• Fully integrated and requiring no external components
• Can be placed in transmit or receive path
• FIFO depth of 16 bits
• Standard compliant transmission jitter and wander
3.7 Clock Rate Adapter Features
• Generation of the internally needed DS3 (44.736 MHz) and E3 (34.368 MHz) clocks a from single input
reference clock
• Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz
• Internally derived clocks can be used as references for LIU and jitter attenuator
• Derived clocks can be transmitted off-chip for external system use
• Standards compliant jitter and wander requirements.
3.8 HDLC Overhead Controller Features
• Each port has a dedicated HDLC controller for DS3/E3 framer link management
• 256-byte receive and transmit FIFOs
• Handles all of the normal Layer 2 tasks including zero stuffing/de-stuffing, FCS generation/checking, abort
generation/checking, flag generation/detection, and byte alignment
• Programmable high and low water marks for the transmit and receive FIFOs
• Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the
G.832 NR or GC channels
• RX data is forced to all ones during LOS, LOF and AIS detection to eliminate false packets
3.9 FEAC Controller Features
• Each port has a dedicated FEAC controller for DS3/E3 link management
• Designed to handle multiple FEAC codewords without Host intervention
• Receive FEAC automatically validates incoming codewords and stores them in a 4-byte FIFO
• Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different
codewords back-to-back to send DS3 Line Loopback commands
• Terminates the FEAC channel in DS3 C-Bit Parity mode and optionally the Sn bit in E3 mode

DS3171/DS3172/DS3173/DS3174
15
3.10 Trail Trace Buffer Features
• Each port has a dedicated Trail Trace Buffer for E3-G.832 link management
• Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
• Insertion of the outgoing trail access point identifier from a 16-byte transmit register
• Receive trace identifier unstable status indication
3.11 Bit Error Rate Tester (BERT) Features
• Each port has a dedicated BERT tester
• Generation and detection of pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
• Pattern insertion/extraction in DS3/E3 payload or entire data stream to and from the line interface
• Large 24-bit error counter allows testing to proceed for long periods without host intervention
• Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
3.12 Loopback Features
• Analog interface loopback – ALB (transmit to receive)
• Line facility loopback – LLB (receive to transmit) with optional transmission of unframed all-one AIS payload
toward system/trunk interface
• Framer diagnostic loopback – DLB (transmit to receive) with automatic transmission of DS3 AIS or unframed
all-one AIS signal toward line/tributary interface(s)
• DS3/E3 framer payload loopback – PLB (receive to transmit) with optional transmission of unframed all-one
AIS payload toward system/trunk interface
• Simultaneous line facility loopback and framer diagnostic loopback
3.13 Microprocessor Interface Features
• Multiplexed or non-multiplexed address bus modes
• 8-bit or 16-bit data bus modes
• Byte swapping option in 16-bit data bus mode
• Read/Write and Data Strobe modes
• Ready handshake output signal
• Global reset input pin
• Global interrupt output pin
• Two programmable I/O pins per port
3.14 Test Features
• Five pin JTAG port
• All functional pins are inout pins in JTAG mode
• Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
• RAM BIST on all internal RAM
• Hi-Z pin to force all digital output and inout pins into HIZ
• TEST pin for manufacturing scan test modes

DS3171/DS3172/DS3173/DS3174
16
4 STANDARDS COMPLIANCE
Table 4-1. Standards Compliance
SPECIFICATION SPECIFICATION TITLE
ANSI
T1.102-1993 Digital Hierarchy – Electrical Interfaces
T1.107-1995 Digital Hierarchy – Formats Specification
T1.231-1997 Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring
T1.404-1994 Network-to-Customer Installation – DS3 Metallic Interface Specification
ETSI
ETS 300 686 Business TeleCommunications; 34Mbps and 140Mbits/s digital leased lines (D34U, D34S,
D140U and D140S); Network interface presentation, 1996
TBR 24 Business TeleCommunications; 34Mbit/s digital unstructured and structured lease lines;
attachment requirements for terminal equipment interface, 1997
ETS EN 300 689 Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
ETS 300 689 Business TeleCommunications (BTC); 34 Mbps digital leased lines (D34U and D34S),
Terminal equipment interface, V 1.2.1, 2001-07
IETF
RFC 2496 Definition of Managed Objects for the DS3/E3 Interface Type, January, 1999
ISO
ISO 3309:1993 Information Technology – Telecommunications & information exchange between systems –
High Level Data Link Control (HDLC) procedures – Frame structure, Fifth Edition, 1993
ITU-T
G.703 Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
G.704 Synchronous Frame Structures Used at 1544, 6312, 2048, 8488 and 44 736 kbit/s
Hierarchical Levels, July, 1995
G.751 Digital Multiplex Equipment Operating at the Third Order Bit Rate of 34,368 kbit/s and the
Fourth Order bit Rate of 139,264 kbit/s and Using Positive Justification, 1993
G.775 Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November, 1994
G.823 The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048
kbit/s Hierarchy, 1993
G.824 The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
G.832 Transport of SDH Elements on PDH Networks – Frame and Multiplexing Structures,
November, 1995
I.432 B-ISDN User-Network Interface – Physical Layer Specification, March, 1993
O.151 Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October, 1992
Q.921 ISDN User-Network Interface – Data Link Layer Specification, March 1993
Telcordia
GR-499-CORE Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2,
December 1998
GR-820-CORE Generic Digital Transmission Surveillance, Issue 1, November 1994
IEEE
IEEE Std 1149-
1990
IEEE Standard Test Access Port and Boundary-Scan Architecture, (Includes IEEE Std
1149-1993) October 21, 1993

DS3171/DS3172/DS3173/DS3174
17
5 ACRONYMS AND GLOSSARY
Definition of the terms used in this Datasheet:
• CCM – Clear Channel Mode
• CLAD – Clock Rate Adapter
• Clear Channel – A Datastream with no framing included, also known as Unframed
• FRM – Frame Mode
• FSCT – Framer Single Chip Transceiver Mode
• HDLC – High Level Data Link Control
• Packet – HDLC packet
• SCT – Single Chip Transceiver (Framer and LIU)
• SCT Mode – DS3/E3 Framer and LIU,
• Unchannelized – See Clear Channel

DS3171/DS3172/DS3173/DS3174
18
6 MAJOR OPERATIONAL MODES
The major operational modes are determined by the FM[2:0] framer mode bits and a few other control bits. Unused
features are powered down and the data paths are held in reset. The configuration registers of the unused features
can be written to and read from. The function of some IO pins change in different operational modes. The line
interface operational mode is determined by the LM[2:0] bits.
6.1 DS3/E3 SCT Mode
This mode is for standard operation that uses the device in the single chip transceiver mode. It utilizes the
framer/formatter as well as the transmit/receive LIU.
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD TLEN
PORT.CR2
JA Off, B3ZS or HDB3 001 0 0
JA RX, B3ZS or HDB3 010 0 0
JA TX, B3ZS or HDB3 011 0 0
JA Off, AMI 001 1 0
JA RX, AMI 010 1 0
JA TX, AMI 011 1 0

DS3171/DS3172/DS3173/DS3174
19
Figure 6-1. DS3/E3 SCT Mode
RLCLKn
RXPn
RXNn
TPOSn/TDATn
TNEGn
TLCLKn
Microprocessor
Interface
TXPn
TXNn
RDATn
RNEGn/ RLCVn
RST
n = port # (1-4)
D[15:0]
A[10:1]
ALE
CS
RD/DS
WR/ R/W
MODE
INT
GPIO[8:1]
WIDTH
RDY
A[0]/BSWAP
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
JTDO
JTCLK
JTMS
JTDI
JTRST
HDLC
FEAC
LLB
DLB
DS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
Trail
Trace
Buffer
ROHn
ROHCLKn
ROHSOFn
TCLKIn
RSERn
RCLKOn/RGCLKn
RSOFOn/RDENn
DS3/E3
Receive
LIU
TAIS
TUA1
Clock Rate
Adapter
CLKA
CLKB
CLKC
PLB
ALB
UA1
GEN
TSERn
B3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder
TSOFIn
TX BERT
RX BERT
TSOFOn/TDENn
TOHn
TOHCLKn TOHSOFn
TOHENn
TCLKOn/TGCLKn
DS317x

DS3171/DS3172/DS3173/DS3174
20
6.2 DS3/E3 Clear Channel Mode
This mode bypasses the framer/formatter for unchannelized datastreams that don’t include DS3 framing or E3
framing.
MODE FM[2:0]
Clear Channel 1XX
Figure 6-2. DS3/E3 Clear Channel Mode
TCLKOn/ TGCLKn
RLCLKn
RXPn
RXNn
TPOSn/TDATn
TNEGn
TLCLKn
Microprocessor
Interface
TXPn
TXNn
RDATn
RNEGn/ RLCVn
RST
n = port # (1-4)
D[15:0]
A[10:1]
ALE
CS
RD/DS
WR/ R/W
MODE
INT
GPIO[8:1]
WIDTH
RDY
A[0]/BSWAP
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
JTDO
JTCLK
JTMS
JTDI
JTRST
LLB
DLB
ROHn
ROHCLKn
ROHSOFn
TCLKIn
RSERn
RCLKOn/RGCLKn
RSOFOn/RDENn
DS3/E3
Receive
LIU
TAIS
TUA1
Clock Rate
Adapter
CLKA
CLKB
CLKC
PLB
ALB
UA1
GEN
TSERn
B3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder
TSOFIn
TX BERT
RX BERT