Mechatronics MXS3FK-DSP Quick start guide

OPERATIONAL MANUAL
FOR
SPARTAN-3 DSP TRAINER
MODEL : MXS3FK-DSP
Rev : 003
MECHATRONICS TEST EQUIPMENT (I)PVT.LTD.
B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR,
NEAR YASHAVANTRAO CHAVAN NATYAGRUH,
KOTHRUD, PUNE- 411038
PHONE : [phone]
FAX : [phone]
EMAIL : [email protected]
URL : www.mte-india.com

TABLE OF CONTENTS
PREFACE .....................................................................................................................................1
About This Manual.....................................................................................................................1
Manual Contents ....................................................................................................................................1
CHAPTER 1..................................................................................................................................2
Introduction ................................................................................................................................2
Features .................................................................................................................................................2
CHAPTER 2..................................................................................................................................5
ADC - DAC Interface .................................................................................................................5
2.1 ANALOG INPUT...............................................................................................................................5
2.2 Analog Input Connector:...................................................................................................................6
2.3 ANALOG OUTPUT...........................................................................................................................8
2.4 Analog Output Connector:................................................................................................................9
2.6 Stereo Jack Connector:....................................................................................................................9
2.7 Function Generator ........................................................................................................................10
2.8 Potentiometer Adjustments ............................................................................................................10
2.9 Jumper Settings of ADC- DAC Interface........................................................................................11
CHAPTER 3................................................................................................................................13
USB Interface ..........................................................................................................................13
3.1 Data Bus Connection .....................................................................................................................14
3.2 Control Lines: .................................................................................................................................14
3.3. FTDI Driver Installation..................................................................................................................15
CHAPTER 4................................................................................................................................17
Serial Interface.........................................................................................................................17
4.1 RS- 232 Interface ...........................................................................................................................17
CHAPTER 5................................................................................................................................19
PS/2 Mouse/Keyboard Interface..............................................................................................19
5.1 PS/2 KEYBOARD...........................................................................................................................20
5.2 Control Signal Connection..............................................................................................................21
CHAPTER 6................................................................................................................................23
VGA Interface ..........................................................................................................................23
6.1 VGA Display Theory.......................................................................................................................24
6.2 VGA signal TIMING........................................................................................................................26
CHAPTER 7................................................................................................................................27
Seven Segment LED Display ..................................................................................................27
CHAPTER 8................................................................................................................................29
Stepper Motor And Relay Interface .........................................................................................29
8.1 Stepper Motor Interface..................................................................................................................29
8.2 Relay Interface ...............................................................................................................................29
CHAPTER 9................................................................................................................................31
LCD Interface...........................................................................................................................31
9.1 Data Lines Connection ...................................................................................................................32
9.2 Control Line Interface: ....................................................................................................................32

9.3 ASCII CODE...................................................................................................................................33
CHAPTER 10..............................................................................................................................34
Switches And LEDs .................................................................................................................34
10.1 DIP Switches ................................................................................................................................34
10.2 Key Switches................................................................................................................................34
10.3 LEDS ............................................................................................................................................35
CHAPTER 11..............................................................................................................................36
Connector Details ....................................................................................................................36
11.1 IO Connectors ..............................................................................................................................36
CHAPTER 12..............................................................................................................................38
Clock and Reset Sources ........................................................................................................38
CHAPTER 13..............................................................................................................................39
SPARTAN-3 Configuration Details ..........................................................................................39
13.1 Boundary Scan mode:..................................................................................................................39
13.2 Master Serial Mode ......................................................................................................................39
13.3 Jumper Setting .............................................................................................................................39
13.4 JTAG Header: ..............................................................................................................................40
CHAPTER 14..............................................................................................................................42
Power Supplies........................................................................................................................42
14.1 Voltage Regulators.......................................................................................................................42
APPENDIX A ..............................................................................................................................43
Consolidated UCF For The Complete Board...........................................................................43
APPENDIX B ..............................................................................................................................49
Operating Instructions To Start A New Design ........................................................................49
B.1 Starting The ISE Software: ............................................................................................................49
B.2 Design Flow ...................................................................................................................................49
B.3 Design Description.........................................................................................................................50
B.4 Truth Table of Half adder: -............................................................................................................50
B.5 VHDL Code for Half adder .............................................................................................................50
B.6 Steps to implement the Half adder in the FPGA using Xilinx ISE(8.1i) .........................................51
APPENDIX C ..............................................................................................................................68
Component Diagram Details....................................................................................................68

LIST OF FIGURES
Figure 1: Block Diagram................................................................................................................3
Figure 2: FPGA – ADC DAC Interface ..........................................................................................5
Figure 3: Input Channels of ADC ..................................................................................................6
Figure 5: Reconstruction Filter ......................................................................................................9
Figure 6: Stereo Jack ..................................................................................................................10
Figure 7: Frequency Range Set ..................................................................................................10
Figure 8: USB Interface...............................................................................................................14
Figure 9: FPGA – RS232 Interface .............................................................................................17
Figure 10: PS/2 Connector..........................................................................................................19
Figure 11: PS/2 Timing Diagram.................................................................................................20
Figure 12: PS/2 Keyboard with scan codes ................................................................................21
Figure 13: FPGA –VGA Interface................................................................................................23
Figure 14: CRT Display Timing ...................................................................................................25
Figure 15: VGA Timing................................................................................................................26
Figure 16: Seven Segment Display.............................................................................................27
Figure 17: Stepper Motor Interface .............................................................................................29
Figure 18: Relay Interface...........................................................................................................30
Figure 19: LCD Interface to SPARTAN-3 FPGA.........................................................................31
Figure 20: ASCII Code for 5 x 7 LCD display..............................................................................33
Figure 21: Positional Details of On Board Connectors................................................................37
Figure 22: JTAG Mode Selection ................................................................................................40
Figure 23: JTAG Connector Details ............................................................................................41

LIST OF TABLES
Table 1: Analog Inputs ..................................................................................................................6
Table 2: ADC Interface to SPARTAN 3 FPGA..............................................................................8
Table 3: Control Inputs to ADC .....................................................................................................8
Table 4: Analog Outputs ...............................................................................................................9
Table 5: DAC Interface to FPGA...................................................................................................9
Table 6: Potentiometer adjustments ...........................................................................................10
Table 7: Jumper Setting for ADC Input .......................................................................................11
Table 8: Jumper setting for Anti Aliasing Filter............................................................................11
Table 9: Jumper Setting for Analog Output.................................................................................11
Table 10: Jumper Setting for Reconstruction Filter.....................................................................11
Table 11: Data Bus Interface to SPATAN -3 FPGA ....................................................................14
Table 12: Control Lines Interface to SPARTAN-3 FPGA ............................................................15
Table 13: RS232 Interface to SPARTAN -3 FPGA .....................................................................17
Table 14: PS/2 Connector Details...............................................................................................19
Table 15: PS/2 Bus Timing .........................................................................................................19
Table 16: Common PS/2 Keyboard Commands .........................................................................21
Table 17: LED Status ..................................................................................................................21
Table 18: PS/2 Interface to SPARTAN -3 FPGA MOUSE ..........................................................21
Table 19: VGA Interface to SPARTAN-3 FPGA..........................................................................24
Table 20: VGA signal timing........................................................................................................26
Table 21: Seven Segment Display Interface to SPARTAN-3 FPGA...........................................28
Table 22: Stepper motor Connector: J14 ....................................................................................29
Table 23: Stepper Motor and Relay Interface to FPGA ..............................................................30
Table 24: Data Line Interface to SPARTAN-3 FPGA..................................................................32
Table 25: Control Line Interface to SPARTAN-3 FPGA..............................................................32
Table 26: DIP switch Interface to SPARTAN-3 FPGA ................................................................34
Table 27: KEY switch Interface to SPARTAN-3 FPGA ...............................................................34
Table 28: LED Interface to SPARTAN-3 FPGA ..........................................................................35
Table 29: IO Connector Interface to FPGA .................................................................................36
Table 30: IO Clock-Reset Interface to FPGA ..............................................................................38
Table 31: Mode Selection Jumper Settings ................................................................................39
Table 32: Mode Selection Table .................................................................................................39
Table 33: Configuration Selection ...............................................................................................40
Table 34: Power Supply Details ..................................................................................................42

1
PREFACE
About This Manual
This manual gives operational details for all the interfaces.
Manual Contents
This manual contains following chapters:
•Chapter 1, “ Introduction ”
•Chapter 2, “ ADC And DAC Interface ”
•Chapter 3, “ USB Interface ”
•Chapter 4, “ Serial Interface ”
•Chapter 5, “ PS/2 Mouse/Keyboard Interface ”
•Chapter 6, “ VGA Interface ”
•Chapter 7, “ Seven Segment LED Display ”
•Chapter 8, ” Stepper Motor And Relay Interface ”
•Chapter 9, ” LCD Interface ”
•Chapter 10, “ Switches And LEDs ”
•Chapter 11, “ Connector Details ”
•Chapter 12, “ Clock And Reset Sources ”
•Chapter 13. “ SPARTAN -3 Configuration Details “
•Chapter 14, “ Power Supplies ”
•Appendix A Consolidated UCF for the complete Board
•Appendix B Operating Instruction to Start a New Design
•Appendix C Component Diagram Details

2
CHAPTER 1
Introduction
SPARTAN-3 based Universal DSP ProtoBoard (MXS3FK-004-DSP) provides easy to use
development platform, useful to physically verify DSP algorithms or simple digital designs
around SPARTAN -3 FPGA.
Features
Figure 1 shows the SPARTAN-3 ProtoBoard, which includes the following components and
features:
•SPARTAN -3 FPGA : 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat
Package (MXS3FK-004-DSP)
ÐThree families Spartan 3 /Spartan 3L/Spartan 3 XA.
ÐVery low cost, high-performance logic solution for high-volume, consumer-oriented
applications.
- Densities as high as 74,880 logic cells.
- Three power rails for core (1.2V), I/O’s (1.2V to 3.3V) and Auxiliary purposes (2.5V).
- 326 MHz system clock rate.
- 90 nm process technology.
ÐSelect IO™ Signaling.
- Up to 784 I/O pins.
- 622 Mb/s data transfer rate per IO.
- 18 single-ended signal standards.
- 6 differential I/O standards including LVDS, RSDS.
- Termination by Digitally Controlled Impedance.
- Double data Rate (DDR) support.
ÐLogic Resources
- Abundant Logic cells with shift register capability.
- Wide Multiplexers.
- Fast look-ahead carry logic.
- Dedicated 18 x 18 Multipliers.
ÐSelectRAM™ Hierarchical Memory.
- Up to 1,872 Kbits of total block RAM.
- Up to 520 Kbits of Distributed RAM.
ÐDigital Clock Manager (up to 4DCMs)
- Clock skew elimination.
- Frequency synthesis
- High resolution phase shifting.
ÐEight global clock lines and abundant routing.
ÐMicro Blaze™ processor, PCI and other cores.
•Analog Interface: – 12 bit AD7891 ADC and 12 bit AD7541 DAC.
ÐAnalog Input – Four channels using ADC using AD7891, (500Ksps, 12 bit).
ÐAdditional Stereo Jacks are provided for Audio Input and Audio Output.
ÐThermister interface is given to ADC channel 5.
ÐAnalog Output- Four channels using four DAC’s-AD7541. (12 bit, 100 ns conversion
time)
•Function Generator (using IC 8038)
ÐProvides Sine, Square and Triangular waveforms outputs.
ÐFrequency variable from 60-200 KHz.
ÐOne Anti-aliasing filter at the input of Analog to Digital converter.

3
ÐOne Reconstruction filter at the output of Digital to Analog converter.
Figure 1: Block Diagram
•Seven Segment Display: Four-character, seven-segment LED display.
•DIP Switches: 16 DIP switches.
•LEDs: 38 onboard LEDS

4
Ð16 output LEDs (OL 0 – OL 15).
Ð16 input LEDs (IL 0 – IL 15).
ÐDone LED.(DONE)
Ð3 Power ON LEDs (LED5V, LED3V3, LED2v5).
Ð2 Relay LEDs (RNO, RNC).
•Push Button Switches: 16 momentary-contact push button switches.
•LCD interface: 16 character 2 row LCD.
•PS/2 Keyboard & Mouse Interface:
ÐIt handles Data signal that carries a serial stream of bits from the keyboard as each key
is pressed and released.
ÐIt configures and initializes the mouse, gets the information sent by the mouse
•VGA Interface: 12 bit, 512 colours VGA display port.
ÐAdjustable width for the red, green and blue output signals.
ÐFlexible timing for the horizontal and vertical sync signals.
•Serial Interface: One RS-232 channel using MAX3223, 9 pin two channel serial interfaces.
ÐDB9 9-pin female connector (DCE connector).
ÐRS-232 transceiver/level translator using MAX3223 in SSOP package.
ÐUses straight-through serial cable to connect to computer or workstation serial port.
•USB Controller: USING USB FIFO IC FT245BM from FTDI to transfer data to / from FPGA
and host PC at up to 1Mbyte per second.
ÐSingle Chip USB Parallel FIFO bi-directional Data Transfer
ÐTransfer Data rate to 1M Byte / Sec - D2XX Drivers
ÐSimple to interface to MCU / PLD/ FPGA logic with a 4 wire handshake interface
ÐEntire USB protocol handled on-chip, no USB-specific firmware programming required.
ÐUSB Bulk or Isochronous data transfer modes
•Stepper Motor Interface: Stepper Motor interface using 12VDC, Steps/Rev-200 motor with
step angle of 1.80
•Relay Interface: NO & NC contacts are provided using Relay-12VDC.
•User selectable configuration modes.
•Free IOs: 11.
•Clock Oscillator: 4 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator
clock source.
•JTAG port: JTAG download cable (parallel III) interface.
•Power Supplies: 5 volts regulated power supply provided along with the board.
ÐOn board 3.3V, 2.5V, 1.2V regulators.
ÐFPGA supplies viz. Vccint & Vcco are generated on board.

5
CHAPTER 2
ADC - DAC Interface
SPARTAN-3 DSP ProtoBoard has a high speed, 12 bit ADC (AD 7891) and DAC (AD 7541),
surface mounted on top side of the board. A detailed interface is as shown in Figure 2
Figure 2: FPGA – ADC DAC Interface
2.1 ANALOG INPUT
Five analog input channels (In-Channel 1 to In-Channel 4 and In-Channel 5 for Thermister), as
shown in Figure 3, are provided using ADC - AD7891, with following specifications
•Input range - +10V to -10 Volts.