Mechatronics MXS3FK-DSP Quick start guide

OPERATIONAL MANUAL
FOR
SPARTAN-3 DSP TRAINER
MODEL : MXS3FK-DSP
Rev : 003
MECHATRONICS TEST EQUIPMENT (I)PVT.LTD.
B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR,
NEAR YASHAVANTRAO CHAVAN NATYAGRUH,
KOTHRUD, PUNE- 411038
PHONE : [phone]
FAX : [phone]
EMAIL : [email protected]
URL : www.mte-india.com

TABLE OF CONTENTS
PREFACE .....................................................................................................................................1
About This Manual.....................................................................................................................1
Manual Contents ....................................................................................................................................1
CHAPTER 1..................................................................................................................................2
Introduction ................................................................................................................................2
Features .................................................................................................................................................2
CHAPTER 2..................................................................................................................................5
ADC - DAC Interface .................................................................................................................5
2.1 ANALOG INPUT...............................................................................................................................5
2.2 Analog Input Connector:...................................................................................................................6
2.3 ANALOG OUTPUT...........................................................................................................................8
2.4 Analog Output Connector:................................................................................................................9
2.6 Stereo Jack Connector:....................................................................................................................9
2.7 Function Generator ........................................................................................................................10
2.8 Potentiometer Adjustments ............................................................................................................10
2.9 Jumper Settings of ADC- DAC Interface........................................................................................11
CHAPTER 3................................................................................................................................13
USB Interface ..........................................................................................................................13
3.1 Data Bus Connection .....................................................................................................................14
3.2 Control Lines: .................................................................................................................................14
3.3. FTDI Driver Installation..................................................................................................................15
CHAPTER 4................................................................................................................................17
Serial Interface.........................................................................................................................17
4.1 RS- 232 Interface ...........................................................................................................................17
CHAPTER 5................................................................................................................................19
PS/2 Mouse/Keyboard Interface..............................................................................................19
5.1 PS/2 KEYBOARD...........................................................................................................................20
5.2 Control Signal Connection..............................................................................................................21
CHAPTER 6................................................................................................................................23
VGA Interface ..........................................................................................................................23
6.1 VGA Display Theory.......................................................................................................................24
6.2 VGA signal TIMING........................................................................................................................26
CHAPTER 7................................................................................................................................27
Seven Segment LED Display ..................................................................................................27
CHAPTER 8................................................................................................................................29
Stepper Motor And Relay Interface .........................................................................................29
8.1 Stepper Motor Interface..................................................................................................................29
8.2 Relay Interface ...............................................................................................................................29
CHAPTER 9................................................................................................................................31
LCD Interface...........................................................................................................................31
9.1 Data Lines Connection ...................................................................................................................32
9.2 Control Line Interface: ....................................................................................................................32

9.3 ASCII CODE...................................................................................................................................33
CHAPTER 10..............................................................................................................................34
Switches And LEDs .................................................................................................................34
10.1 DIP Switches ................................................................................................................................34
10.2 Key Switches................................................................................................................................34
10.3 LEDS ............................................................................................................................................35
CHAPTER 11..............................................................................................................................36
Connector Details ....................................................................................................................36
11.1 IO Connectors ..............................................................................................................................36
CHAPTER 12..............................................................................................................................38
Clock and Reset Sources ........................................................................................................38
CHAPTER 13..............................................................................................................................39
SPARTAN-3 Configuration Details ..........................................................................................39
13.1 Boundary Scan mode:..................................................................................................................39
13.2 Master Serial Mode ......................................................................................................................39
13.3 Jumper Setting .............................................................................................................................39
13.4 JTAG Header: ..............................................................................................................................40
CHAPTER 14..............................................................................................................................42
Power Supplies........................................................................................................................42
14.1 Voltage Regulators.......................................................................................................................42
APPENDIX A ..............................................................................................................................43
Consolidated UCF For The Complete Board...........................................................................43
APPENDIX B ..............................................................................................................................49
Operating Instructions To Start A New Design ........................................................................49
B.1 Starting The ISE Software: ............................................................................................................49
B.2 Design Flow ...................................................................................................................................49
B.3 Design Description.........................................................................................................................50
B.4 Truth Table of Half adder: -............................................................................................................50
B.5 VHDL Code for Half adder .............................................................................................................50
B.6 Steps to implement the Half adder in the FPGA using Xilinx ISE(8.1i) .........................................51
APPENDIX C ..............................................................................................................................68
Component Diagram Details....................................................................................................68

LIST OF FIGURES
Figure 1: Block Diagram................................................................................................................3
Figure 2: FPGA – ADC DAC Interface ..........................................................................................5
Figure 3: Input Channels of ADC ..................................................................................................6
Figure 5: Reconstruction Filter ......................................................................................................9
Figure 6: Stereo Jack ..................................................................................................................10
Figure 7: Frequency Range Set ..................................................................................................10
Figure 8: USB Interface...............................................................................................................14
Figure 9: FPGA – RS232 Interface .............................................................................................17
Figure 10: PS/2 Connector..........................................................................................................19
Figure 11: PS/2 Timing Diagram.................................................................................................20
Figure 12: PS/2 Keyboard with scan codes ................................................................................21
Figure 13: FPGA –VGA Interface................................................................................................23
Figure 14: CRT Display Timing ...................................................................................................25
Figure 15: VGA Timing................................................................................................................26
Figure 16: Seven Segment Display.............................................................................................27
Figure 17: Stepper Motor Interface .............................................................................................29
Figure 18: Relay Interface...........................................................................................................30
Figure 19: LCD Interface to SPARTAN-3 FPGA.........................................................................31
Figure 20: ASCII Code for 5 x 7 LCD display..............................................................................33
Figure 21: Positional Details of On Board Connectors................................................................37
Figure 22: JTAG Mode Selection ................................................................................................40
Figure 23: JTAG Connector Details ............................................................................................41

LIST OF TABLES
Table 1: Analog Inputs ..................................................................................................................6
Table 2: ADC Interface to SPARTAN 3 FPGA..............................................................................8
Table 3: Control Inputs to ADC .....................................................................................................8
Table 4: Analog Outputs ...............................................................................................................9
Table 5: DAC Interface to FPGA...................................................................................................9
Table 6: Potentiometer adjustments ...........................................................................................10
Table 7: Jumper Setting for ADC Input .......................................................................................11
Table 8: Jumper setting for Anti Aliasing Filter............................................................................11
Table 9: Jumper Setting for Analog Output.................................................................................11
Table 10: Jumper Setting for Reconstruction Filter.....................................................................11
Table 11: Data Bus Interface to SPATAN -3 FPGA ....................................................................14
Table 12: Control Lines Interface to SPARTAN-3 FPGA ............................................................15
Table 13: RS232 Interface to SPARTAN -3 FPGA .....................................................................17
Table 14: PS/2 Connector Details...............................................................................................19
Table 15: PS/2 Bus Timing .........................................................................................................19
Table 16: Common PS/2 Keyboard Commands .........................................................................21
Table 17: LED Status ..................................................................................................................21
Table 18: PS/2 Interface to SPARTAN -3 FPGA MOUSE ..........................................................21
Table 19: VGA Interface to SPARTAN-3 FPGA..........................................................................24
Table 20: VGA signal timing........................................................................................................26
Table 21: Seven Segment Display Interface to SPARTAN-3 FPGA...........................................28
Table 22: Stepper motor Connector: J14 ....................................................................................29
Table 23: Stepper Motor and Relay Interface to FPGA ..............................................................30
Table 24: Data Line Interface to SPARTAN-3 FPGA..................................................................32
Table 25: Control Line Interface to SPARTAN-3 FPGA..............................................................32
Table 26: DIP switch Interface to SPARTAN-3 FPGA ................................................................34
Table 27: KEY switch Interface to SPARTAN-3 FPGA ...............................................................34
Table 28: LED Interface to SPARTAN-3 FPGA ..........................................................................35
Table 29: IO Connector Interface to FPGA .................................................................................36
Table 30: IO Clock-Reset Interface to FPGA ..............................................................................38
Table 31: Mode Selection Jumper Settings ................................................................................39
Table 32: Mode Selection Table .................................................................................................39
Table 33: Configuration Selection ...............................................................................................40
Table 34: Power Supply Details ..................................................................................................42

1
PREFACE
About This Manual
This manual gives operational details for all the interfaces.
Manual Contents
This manual contains following chapters:
•Chapter 1, “ Introduction ”
•Chapter 2, “ ADC And DAC Interface ”
•Chapter 3, “ USB Interface ”
•Chapter 4, “ Serial Interface ”
•Chapter 5, “ PS/2 Mouse/Keyboard Interface ”
•Chapter 6, “ VGA Interface ”
•Chapter 7, “ Seven Segment LED Display ”
•Chapter 8, ” Stepper Motor And Relay Interface ”
•Chapter 9, ” LCD Interface ”
•Chapter 10, “ Switches And LEDs ”
•Chapter 11, “ Connector Details ”
•Chapter 12, “ Clock And Reset Sources ”
•Chapter 13. “ SPARTAN -3 Configuration Details “
•Chapter 14, “ Power Supplies ”
•Appendix A Consolidated UCF for the complete Board
•Appendix B Operating Instruction to Start a New Design
•Appendix C Component Diagram Details

2
CHAPTER 1
Introduction
SPARTAN-3 based Universal DSP ProtoBoard (MXS3FK-004-DSP) provides easy to use
development platform, useful to physically verify DSP algorithms or simple digital designs
around SPARTAN -3 FPGA.
Features
Figure 1 shows the SPARTAN-3 ProtoBoard, which includes the following components and
features:
•SPARTAN -3 FPGA : 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat
Package (MXS3FK-004-DSP)
ÐThree families Spartan 3 /Spartan 3L/Spartan 3 XA.
ÐVery low cost, high-performance logic solution for high-volume, consumer-oriented
applications.
- Densities as high as 74,880 logic cells.
- Three power rails for core (1.2V), I/O’s (1.2V to 3.3V) and Auxiliary purposes (2.5V).
- 326 MHz system clock rate.
- 90 nm process technology.
ÐSelect IO™ Signaling.
- Up to 784 I/O pins.
- 622 Mb/s data transfer rate per IO.
- 18 single-ended signal standards.
- 6 differential I/O standards including LVDS, RSDS.
- Termination by Digitally Controlled Impedance.
- Double data Rate (DDR) support.
ÐLogic Resources
- Abundant Logic cells with shift register capability.
- Wide Multiplexers.
- Fast look-ahead carry logic.
- Dedicated 18 x 18 Multipliers.
ÐSelectRAM™ Hierarchical Memory.
- Up to 1,872 Kbits of total block RAM.
- Up to 520 Kbits of Distributed RAM.
ÐDigital Clock Manager (up to 4DCMs)
- Clock skew elimination.
- Frequency synthesis
- High resolution phase shifting.
ÐEight global clock lines and abundant routing.
ÐMicro Blaze™ processor, PCI and other cores.
•Analog Interface: – 12 bit AD7891 ADC and 12 bit AD7541 DAC.
ÐAnalog Input – Four channels using ADC using AD7891, (500Ksps, 12 bit).
ÐAdditional Stereo Jacks are provided for Audio Input and Audio Output.
ÐThermister interface is given to ADC channel 5.
ÐAnalog Output- Four channels using four DAC’s-AD7541. (12 bit, 100 ns conversion
time)
•Function Generator (using IC 8038)
ÐProvides Sine, Square and Triangular waveforms outputs.
ÐFrequency variable from 60-200 KHz.
ÐOne Anti-aliasing filter at the input of Analog to Digital converter.

3
ÐOne Reconstruction filter at the output of Digital to Analog converter.
Figure 1: Block Diagram
•Seven Segment Display: Four-character, seven-segment LED display.
•DIP Switches: 16 DIP switches.
•LEDs: 38 onboard LEDS

4
Ð16 output LEDs (OL 0 – OL 15).
Ð16 input LEDs (IL 0 – IL 15).
ÐDone LED.(DONE)
Ð3 Power ON LEDs (LED5V, LED3V3, LED2v5).
Ð2 Relay LEDs (RNO, RNC).
•Push Button Switches: 16 momentary-contact push button switches.
•LCD interface: 16 character 2 row LCD.
•PS/2 Keyboard & Mouse Interface:
ÐIt handles Data signal that carries a serial stream of bits from the keyboard as each key
is pressed and released.
ÐIt configures and initializes the mouse, gets the information sent by the mouse
•VGA Interface: 12 bit, 512 colours VGA display port.
ÐAdjustable width for the red, green and blue output signals.
ÐFlexible timing for the horizontal and vertical sync signals.
•Serial Interface: One RS-232 channel using MAX3223, 9 pin two channel serial interfaces.
ÐDB9 9-pin female connector (DCE connector).
ÐRS-232 transceiver/level translator using MAX3223 in SSOP package.
ÐUses straight-through serial cable to connect to computer or workstation serial port.
•USB Controller: USING USB FIFO IC FT245BM from FTDI to transfer data to / from FPGA
and host PC at up to 1Mbyte per second.
ÐSingle Chip USB Parallel FIFO bi-directional Data Transfer
ÐTransfer Data rate to 1M Byte / Sec - D2XX Drivers
ÐSimple to interface to MCU / PLD/ FPGA logic with a 4 wire handshake interface
ÐEntire USB protocol handled on-chip, no USB-specific firmware programming required.
ÐUSB Bulk or Isochronous data transfer modes
•Stepper Motor Interface: Stepper Motor interface using 12VDC, Steps/Rev-200 motor with
step angle of 1.80
•Relay Interface: NO & NC contacts are provided using Relay-12VDC.
•User selectable configuration modes.
•Free IOs: 11.
•Clock Oscillator: 4 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator
clock source.
•JTAG port: JTAG download cable (parallel III) interface.
•Power Supplies: 5 volts regulated power supply provided along with the board.
ÐOn board 3.3V, 2.5V, 1.2V regulators.
ÐFPGA supplies viz. Vccint & Vcco are generated on board.

5
CHAPTER 2
ADC - DAC Interface
SPARTAN-3 DSP ProtoBoard has a high speed, 12 bit ADC (AD 7891) and DAC (AD 7541),
surface mounted on top side of the board. A detailed interface is as shown in Figure 2
Figure 2: FPGA – ADC DAC Interface
2.1 ANALOG INPUT
Five analog input channels (In-Channel 1 to In-Channel 4 and In-Channel 5 for Thermister), as
shown in Figure 3, are provided using ADC - AD7891, with following specifications
•Input range - +10V to -10 Volts.

6
•In-Channel 1 and In-Channel 2 can take external analog inputs either from the PUT terminal
or audio inputs from the stereo jacks provided.
•In-Channel 3 takes an external analog input from the PUT terminal.
Figure 3: Input Channels of ADC
•In-Channel 4 takes an external analog input from the PUT terminal, user has the option of
cascading the onboard Anti-Aliasing Filter (a low pass Analog filter) to his input. Figure 4
shows Anti Aliasing Filter
•Channel 5 takes input from Thermister.
Note - AD7891 ADC has eight single ended channels out of which only five channels are used
as analog inputs.
2.2 Analog Input Connector:
•CH1 to CH4: Four PUTs are provided to connect single ended ANALOG INPUTS
Table 1: Analog Inputs
Ch1 Ch2 Ch3 Ch4
Ch1 In GND Ch2 In GND Ch3 In GND Ch4 In GND
Figure 4 : Anti- Aliasing Filter

7
1 2 1 2 1 2 1 2

8
Table 2: ADC Interface to SPARTAN 3 FPGA
Data Bits FPGA pin
"AD0_F" 45
"AD1_F"" 46
"AD2_F"" 57
"AD3_F"" 58
"AD4_F"" 61
"AD5_F"" 62
"AD6_F"" 63
"AD7_F"" 64
"AD8_F"" 65
"AD9_F"" 67
"AD10_F"" 68
"AD11_F"" 71
Table 3: Control Inputs to ADC
Control Inputs FPGA PIN
"MODE" 72
"EOC_F" 44
"\CONVST\" 48
"\CS\" 50
"\RD\" 51
"\WR\" 52
2.3 ANALOG OUTPUT
Four analog output channels are provided on-board DAC – AD7541
•Output Range +10 V to -10 Volts, single ended
•Analog output on Out-Channel 1 and Out-Channel 2 can be routed either to Stereo Jacks or
PUT terminals.
•Out-Channel 3 is directly connected to PUT terminals.
•Out-Channel 4, user has the option of either connecting its output directly to PUT terminal or
through a “Reconstruction filter” (Low pass analog filter), as shown in Figure 5.

9
Figure 5: Reconstruction Filter
2.4 Analog Output Connector:
•Vout1 to Vout4: Four PUTs are provided to provide ANALOG OUTPUTS
Table 4: Analog Outputs
Vout1 Vout2 Vout3 Vout4
Vout1 GND Vout2 GND Vout3 GND Vout4 GND
1 2 1 2 1 2 1 2
Table 5: DAC Interface to FPGA
Data Bits FPGA PIN
"DAC0_F" 81
"DAC1_F" 79
"DAC2_F" 100
"DAC3_F" 97
"DAC4_F" 93
"DAC5_F" 90
"DAC6_F" 94
"DAC7_F" 95
"DAC8_F" 96
"DAC9_F" 102
"DAC10_F" 101
"DAC11_F" 80
"EN1_F" 87
"EN2_F" 85
"EN3_F" 86
"EN4_F" 74
2.6 Stereo Jack Connector:
Stereo jack connectors are provided taking in / giving out signals to/from for audio systems.

10
Figure 6: Stereo Jack
2.7 Function Generator
Function Generator - IC8038 is used on board to generate sine, square, triangular waves in the
frequency range of 60 Hz to 200 KHz.
Output of function generator can be used as analog input to ADC for performing different DSP
applications
yFunction Generator outputs are available as Sine, Square and Triangular wave at three test
points – SINE, SQUARE and TRIANGULAR respectively.
yFrequency Setting – function generator frequency can be varied in 2-steps
ÐCoarse Frequency – using switch SW8.
ÐFine Frequency – using potentiometer PR1 for frequency range selection
SW8 is 4-way DIP Switch and is used to select the frequency range of the Function generator.
Figure 7: Frequency Range Set
Only one switch must be ON at a time for correct operation of the function generator.
•Amplitude Setting – Amplitude of the generated waveform(s) can be adjusted using
potentiometers as follows
ÐPR2 for Square wave,
ÐPR3 for Triangular Wave
ÐPR4 for Sine wave
2.8 Potentiometer Adjustments
Details of the potentiometers used in ADC DAC Interface are given in table 4
Table 6: Potentiometer adjustments
Adjustments Potentiometer

11
Frequency Adjustment PR1
Square Wave Amplitude Adjustment PR2
Triangular Wave Amplitude Adjustment PR3
Sine Wave Amplitude Adjustment PR4
Offset adjustment of Sine wave PR5
Offset adjustment of Triangular wave PR6
Time constant(R) adjustment of anti-Aliasing Filter PR7
Time constant(R) adjustment of Reconstruction Filter PR8
DAC-1 range adjustment PR9
DAC-2 range adjustment PR10
DAC-3 range adjustment PR11
DAC-4 range adjustment PR12
DAC Reference Voltage Adjustment PR13
2.9 Jumper Settings of ADC- DAC Interface
•Analog Input to ADC
Jumper JP3 is for In-Channel 1 and JP2 for In-Channel 2
Table 7: Jumper Setting for ADC Input
JUMPER SETTING JP3 / JP2
1-2 Audio I/P from Stereo Jack
2-3 Analog I/P from PUT
•Anti aliasing filter selection JP4
Anti-aliasing filter provided with channel 4 is selected using JP4
Table 8: Jumper setting for Anti Aliasing Filter
JUMPER SETTING JP4
1-2 ADC IN with Anti-Aliasing Filter
2-3 ADC IN without Anti-Aliasing Filter
•Analog Output
Jumper JP9 is for Out-Channel 1 and JP8 for Out-Channel 2
Table 9: Jumper Setting for Analog Output
JUMPER SETTING JP9/JP8
1-2 Audio O/P to Stereo Jack
2-3 Analog O/P to PUT
•Reconstruction Filter selection JP7
Reconstruction Filter provided with channel4 is selected using JP7.
Table 10: Jumper Setting for Reconstruction Filter
JUMPER SETTING JP7

12
1-2 DAC OUT with Reconstruction Filter
2-3 DAC OUT without Reconstruction Filter

13
CHAPTER 3
USB Interface
SPARTAN-3 Protoboard has a USB interface using device FT245BM from FTDI. It offers data
transfer rates up to 8 Million bits (1 Megabyte) per second.
To send data from the FPGA to the host computer, write the byte-wide data into the module
when TXE# is low. If the (384-byte) transmit buffer fills up or is busy storing the previously
written byte, the device keeps TXE# high in order to stop further data from being written until
some of the FIFO data has been transferred over USB to the host. TXE# goes high after every
byte written.
When the host sends data to the FPGA over USB, the device will make RXF# low to let the
FPGA know that at least one byte of data is available. The FPGA can read a data byte every
time RXF# goes low. RXF# goes high after every byte read.
FTDI chip supports two drivers:
•VCP Drivers
•D2xx Drivers
SPARTAN -3 Protoboard uses D2xx Drivers that allow application software to access the device
“directly” through a published DLL based API.
For more details on Drivers visit http://www.ftdichip.com

14
Figure 8: USB Interface
3.1 Data Bus Connection
8 bit bidirectional data bus for data transfer from / to FPGA and USB interface.
Table 11: Data Bus Interface to SPATAN -3 FPGA
Data Bit FPGA Pin
"USB_D0_F" 106
"USB_D1_F" 107
"USB_D2_F" 108
"USB_D3_F" 109
"USB_D4_F" 111
"USB_D5_F" 113
"USB_D6_F" 114
"USB_D7_F" 115
3.2 Control Lines:
Control group interface consist of following signals:

15
•RD #: Enables reading of data byte from USB controller on data line interface when low.
•WR : Writes data byte from D0-D7 into the transmit FIFO of USB.
•TXE #: Data write enable.
•RXF #: Data read enable.
Table 12: Control Lines Interface to SPARTAN-3 FPGA
Control Bit FPGA Pin
"RD#_F" 116
"WR#_F" 117
"TXE#_F" 119
"RXF#_F" 120
3.3. FTDI Driver Installation
•To install the FTDI drivers on your PC, run the FTDI_Setup.exe file provided in the CD
accompanied with your Protoboard.
•After successful installation following message will be displayed on screen
•After installation when USB device plugged in Device Manager will add USB Serial
Converter controller into its USB Serial Bus Controller list as shown below: