Mesa 7I43 User manual

7I43/7I43H MANUAL
V3.0

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iii
Table of Contents
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
HARDWARE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GENERAL .................................................... 2
FPGA CONFIGURATION SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
USBPOWER.................................................. 2
POWER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
CONNECTOR POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
BUS SWITCH MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PRE-CONFIGURATION PULL-UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS . . . . . . . . 4
I/O CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
JTAG CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
POWER CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EPP INTERFACE CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FPGA ....................................................... 10
EPP CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
USB CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EEPROM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EXTRA EEPROM SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RECONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CONFIGURATION FILE STARTUP OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 13
SC7I43P and SC7I43W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
EPP-FPGA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
USB-FPGA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ADDITIONAL 7I43H INTERFACE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LEDS ....................................................... 16
BUS SWITCH MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I/O LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STARTUP I/O STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DRIVING 5V REFERRED LOADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

iv
Table of Contents
SUPPLIED CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EPPIOPR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USBIOPR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LBP ................................................... 21
EXAMPLE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LOCAL LBP COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LOCAL LBP READ COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LOCAL LBP WRITE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RPC COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EXAMPLE RPC COMMAND LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AVAILABLE DAUGHTER CARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REFERENCE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7I43 1
GENERAL
DESCRIPTION
The 7I43 is a USB/EPP version of the FPGA based Anything I/O card series. It
provides 48 programmable I/O bits The 7I43H variant is a high speed USB version.
Initial FPGA configurations can be downloaded to the 7I43 via the USB (7I43 and
7I43H) or EPP (7I43 only) port. The 7I43/7I43H also has a serial EEPROM for FPGA
configuration storage when the 7I43/7I43H is used in stand-alone applications.
The 48 I/O bits are available on two 50 pin connectors, 24 bits per connector. The
50 pin connectors have I/O module rack compatible pin-outs. The connector pin-out uses
interleaved grounds for lower crosstalk and controlled impedance.
/Done, /Init and power status LEDs are provided for debugging puposes as are 8
FPGA driven LEDs. Several I/O interface daughter cards are available for the 7I43/7I43H.
These cards include a 4 axis 3A Hbridge, a 2 Axis 3A stepper motor driver, an analog
servo amp. interface, anRS-422/485interface, and a debug LED card. One daughter card
can plug directly onto the 7I43/7I43H.
Many IO configuration files are provided with the 7I43/7I43H including simple
remote I/O, 4 and 8 axis servo motion control, 4 and 8 axis microstepping stepper motor
control, multiple channel PWM generator, quadrature counters and more. VHDL source
is provided for all configurations.
FPGA system clock is 50MHZ Oscillator. The Spartan3 used can multiply or divide
this frequency to suitable values for application use.
The 7I43 uses a 200K or 400K gate Xilinx SpartanIII FPGA, and the 7I43H uses
a 400K SpartanIII FPGA. Free development tools for the SpartanIII are available (Xilinx
WebPack) from Xilinx’s web site.

7I43 2
HARDWARE CONFIGURATION
GENERAL
Hardware setup jumper positions assume that the 7I43 or 7I43H card is oriented in
an upright position, that is, with the USB connector towards the person doing the
configuration, and the power connector on top right. In the following, "7I43" refers to both
the 7I43 and the 7I43H.
FPGA CONFIGURATION SOURCE
The 7I43's FPGA can be configured via the USB port, The EPP port, or the on card
serial EEPROM. Jumpers W4 and W5 select the configuration source. The 7I43H does
not have the EPP configuration option.
W4 W5 MODE
DOWN DOWN EPP (PARALLEL PORT) CONFIG
DOWN UP USB CONFIG
UP DOWN EEPROM CONFIG
USB POWER
The 7I43 can be powered by the USB host. The maximum power that can be
supplied by a USB host is 450 mA. This will be sufficient for most but not all 7I43
applications. For applications that require more than the 450 mA supplied by the host, the
7I43 has provisions for external power. W6 connects host USB power to the 7I43's power
supplies. To use host power, W6 must be set to the "UP" position. If external 5Vpower is
used, W6 must be set to the "DOWN" position.
WARNING: Connecting an external 5V supply to the 7I43 while W6 is in the "UP"
position and a USB cable connects the 7I43 to a host computer is likely to damage
the computer by feeding external power ‘backwards’ into the USB port!
POWER ENABLE
The 7I43 can be set to power-up only after the USB interface is activated. This is
the suggested operational mode when the 7I43 is interfaced via USB. For applications
where the 7I43 must operate without the USB interface, This function must be disabled.
W7 controls the power upenable mode. When W7 is in the "UP" position, the 7I43 power
supplies are always enabled. When W7 is in the "DOWN" position, the 7I43 power
supplies will only be enabled when the USB interface is active.

7I43 3
HARDWARE CONFIGURATION
CONNECTOR POWER
The power connection on both I/O connectors (Pin 49) can supply either 3.3V or
5V power. Supplied power should be limited to 400 mA total. W1 selects the power
supplied to both P3 and P4 . When W1 is in the "UP" position, 5V power is supplied to the
connector. When W1 is in the "DOWN" position, 3.3V power is supplied to P3 and P4.
Note that most Mesa I/O adapter cards that connect to Anything I/O cards require 5V.
BUS SWITCH MODE
Jumper W2 determines bus switch mode for all user I/O pins. When jumper W2 is
in the "UP" position, 5V tolerant mode is selected, when ‘down’, 3.3V mode is selected.
Note that 3.3V mode is not 5V tolerant. The FPGA can be damaged byinput voltages
greater than 4V in 3.3V mode.
PRE-CONFIGURATION PULL-UPS
The 7I43 has no pull-up resistors on its user I/O pins. This means that before these
pins are configured, they will not have adefinedstate. If this is not desired, internal pull-up
resistors on all FPGA pins can be enabled via Jumper W3. When W3 is in the "DOWN"
position, user I/O will float until the FPGA is configured. When W3 is in the "UP" position,
all FPGA pins including user I/O pins will have a pull-up resistor to 3.3V so the pins will be
in a "HIGH" state. It is suggested that the internal pull-ups be enabled unless this causes
aproblemwithconnectedI/Odevices.NotethatoncetheFPGAisconfigured,eachFPGA
input pin can have programmable pull-up or pull-down resistors.

7I43 4
CONNECTORS
CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS
7I43-U shown -P version has different defaults

7I43 5
CONNECTORS
7I43H CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS

7I43 6
CONNECTORS
I/O CONNECTORS
P3 and P4 are the 7I43s I/O connectors. These are 50 pin box headers that mate
with standard 50 conductor female IDC connectors. For information on which I/O pin
connects to which FPGA pin, please see the 7I43IO.PIN file on the 7I43 distribution disk.
7I43 IO connector pinouts are as follows:
P4 CONNECTOR PINOUT
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
1 IO0 2 GND 3 IO1 4 GND
5 IO2 6 GND 7 IO3 8 GND
9 IO4 10 GND 11 IO5 12 GND
13 IO6 14 GND 15 IO7 16 GND
17 IO8 18 GND 19 IO9 20 GND
21 IO10 22 GND 23 IO11 24 GND
25 IO12 26 GND 27 IO13 28 GND
29 IO14 30 GND 31 IO15 32 GND
33 IO16 34 GND 35 IO17 36 GND
37 IO18 38 GND 39 IO19 40 GND
41 IO20 42 GND 43 IO21 44 GND
45 IO22 46 GND 47 IO23 48 GND
49 POWER 50 GND

7I43 7
CONNECTORS
7I43 I/O CONNECTORS
P3 CONNECTOR PINOUT
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
1 IO24 2 GND 3 IO25 4 GND
5 IO26 6 GND 7 IO27 8 GND
9 IO28 10 GND 11 IO29 12 GND
13 IO30 14 GND 15 IO31 16 GND
17 IO32 18 GND 19 IO33 20 GND
21 IO34 22 GND 23 IO35 24 GND
25 IO36 26 GND 27 IO37 28 GND
29 IO38 30 GND 31 IO39 32 GND
33 IO40 34 GND 35 IO41 36 GND
37 IO42 38 GND 39 IO43 40 GND
41 IO44 42 GND 43 IO45 44 GND
45 IO46 46 GND 47 IO47 48 GND
49 POWER 50 GND

7I43 8
CONNECTORS
7I43 JTAG CONNECTOR
P5 is a JTAG programming connector. It is not normally used since the 7I43 can be
programmed via the USB or EPP interface, but can be useful when debugging or
reprogramming the CPLD. 3.3V levels are used for JTAG signals. A single JTAG
connector is used for both the CPLD and the FPGA, with the CPLD being first in the JTAG
chain.
P6 CONNECTOR PINOUT
PIN FUNCTION DIRECTION
1 TMS IN
2 TDI IN
3 TDO OUT
4 TCK IN
5 GND
6 +3.3V
POWER CONNECTOR
The 7I43 has an external 5V power connector, P1. This connector supplies power
to the 7I43 in EPP, standalone, and USB applications where USB host power is not
sufficient to power the 7I43. On 7I43 card with revisions B or less, P1 is a four pin .1"
male header. On 7I43s with revision C or greater or 7I43Hs’, P1 is a 2 pin 3.5MM
pluggable screw terminal block. P1 pin-out is as follows:
P1 PINOUT(REV B and<) P1PINOUT(7I43 Rev C and >, all 7I43H)
PIN FUNCTION PIN FUNCTION
1 +5V 1 +5V
2 GND 2 GND
3 GND
4 +5V

7I43 9
CONNECTORS
EPP INTERFACE CONNECTOR
On the 7I43 (but not the 7I43H), P2 is the EPP printer port interface connector. P2
is a 26 pin header. P2 pin-out matches stands DB25 printer port pin-out, allowing asimple
flat cable with a DB25M IDC connector on one end and a 26 pin female header on the
other end to interface the hosts printer port to the 7I43.
P2 PIN DB25 PIN SIGNAL P2 PIN DB25 PIN SIGNAL
1 1 /STROBE 2 14 /AUTOFD
3 2 PD0 4 15 /FAULT
5 3 PD1 6 16 /INIT
7 4 PD2 8 17 /SELECTIN
9 5 PD3 10 18 GND
11 6 PD4 12 19 GND
13 7 PD5 14 20 GND
15 8 PD6 16 21 GND
17 9 PD7 18 22 GND
19 10 /ACK 20 23 GND
21 11 BUSY 22 24 GND
23 12 PERROR 24 25 GND
25 13 SELECT 26 VCC
Note: All handshake signals are available at the CPLD but only /STROBE,
/AUTOFD,/SELECTIN and BUSY are forwarded to the FPGA with the standard CPLD
configuration.

7I43 10
OPERATION
FPGA
The 7I43/7I43H uses a Xilinx Spartan-III FPGA in a 144 pin QFP package, Either
PN XC3S200-5PQ144C or XC3S400-5PQ144C depending on 7I43 model.
HOST INTERFACE
The 7I43 uses either a USB or EPP printer port interface to the host. The 7I43H is
USB only. These interfaces can be used for programming the FPGA and accessing the
FPGA once programmed.
EPP CONFIGURATION
When the7I43 is jumperedso the configuration source is EPP, andthe FPGA is not
configured (DONE is low), the on card CPLD implements two EPP registers to allow
configuring the FPGA via the EPP port.
The two EPP registers are the control register and the data register. The control
register is at EPP address 1 and has a single output bit (at D0) that controls FPGA
/PROGRAM, and a single input bit (at D0) that reads the FPGA’s done status. The data
register at EPP address 0, is used for the byte wide configuration data. Reads from the
data register will return the FPGA size in D0, 1 = 400K and 0 = 200K.
EPP CONFIGURATION PROCEDURE
EPPWriteAddress(1) ; Select EPP address 0x01 = control register
EPPWriteData(0) ; Set /PROGRAM low
EPPWriteData(1) ; Set /PROGRAM High
(Wait 100 Usec) ; Wait 100 Usec for FPGA to initialize
EPPWriteAddress(0) ; Select EPP address 0x00 = data register
EPPReadData ; Verify FPGA size
EPPWriteData(FPGAByte0) ; Write first byte of FPGA config data
EPPWriteData(FPGAByte1) ; Write second byte of FPGA config data
(write remaining FPGA config bytes)

7I43 11
OPERATION
EPP CONFIGURATION
Once the FPGA is configured, the CPLD EPP registers and EPP handshake logic
are disabled and it is the FPGA’s responsibility to handle the EPP host interface. The
CPLD is still used at this point to forward some of the EPP port handshaking lines through
to the FPGA for 5V tolerance.
USB CONFIGURATION
When the7I43 isjumpered so the configuration sourceis USB, and the FPGA is not
configured (DONE is low), the on card CPLD implements a simple data handshake so all
data sent to the USB port is written to the FPGAs configuration port.
The CPLD also will echo characters to indicate the FPGA size and DONE status.
If a character is sent to the 7I43 and the characters LSb is ‘1' the DONE status will be
returned inthe echoed characters LSb. If a character with a ‘0' LSb is sent, a character will
be echoed indicating the FPGA size. This echoed character will have a ‘0' LSb for 200K
7I43s and a ‘1' LSb for 400K 7I43s. Since it in not desirable to deal with echoed
characters for every configuration byte sent to the 7I43, status character echoing is
disabled after receiving 4 consecutive characters with a ‘0' LSB..
Once the FPGA is configured the CPLD data handshake is disabled and it is the
FPGA’s responsibility to handle the interface to the USB chip.
USB CONFIGURATION PROCEDURE
Flush receive buffer ; Optional
Send "1" character ; Optional
Check echoed character for LSb = 0 (done should be low ; Optional
Send "0" character ; Optional
Check echoed character LSb to determine FPGA size ; Optional
Send 4 more "0" characters ; Disable echo
Send configuration byte 0
Send configuration byte 1
(Send remaining configuration bytes)

7I43 12
OPERATION
EEPROM CONFIGURATION
For stand-alone applications and when it is not desired to have to preconfigure the
FPGA via the host interface at power up, the 7I43 can be configured via its serial
EEPROM. Of course the Serial EEPROM must first be programmed with the desired
configuration file. The serial EEPROM used is a ST M25P20 SPI flash serial EEPROM.
All access the serial EEPROM is via the FPGA, so programming the serial
EEPROM is a "bootstrap" process, where the first step is programming the FPGA with a
configuration giving host (EPP or USB) access to the serial EEPROM through the FPGA.
Both the EPP and USB GPIO demo configurations allow this EEPROM access via a
simple SPI interface built into the configuration.
The SCM7I43P program is an example program for writing the serial EEPROM via
the EPP port (DOS only), SCM7I43W is a similar example program for writing the serial
EEPROM via the USB port (windows only) The SCM programs rely on EPPIOPR8 (for
EPP programming or USBIOPR8 (for USB) configuration file being preloaded into the
FPGA before writing the serial EEPROM, as the serial EEPROM can only be accessed
through the FPGA. EPPIOPR8 and USBIOPR8 have a simple SPI interface to allow
EEPROM access.
EXTRA EEPROM SPACE
The serial configurationEEPROM onthe 7I43 has acapacity of 256K bytes, but the
configuration bit file for the 400K Spartan 3 chip is only ~208K bytes, leaving 48 K bytes
free for FPGA accessible non volatile storage. The 200K gate Spartan 3 chip uses only
~128Kbytes of the serial EEPROM leaving 128K bytes free. This storage can be usedfor
non-volatile settings or program storage in stand-alone 7I43 applications.

7I43 13
OPERATION
RECONFIGURATION
Once the 7I43 is configured, the CPLD loader is disabled. In order to reconfigure
the FPGA, the FPGA must be reset via /PROGRAM. This can be done by having the
FPGA assert its /RECONFIG pin (drive it low).Ifyou wish to have the ability to reconfigure
the FPGA without cycling the power, the FPGA configuration must include some way of
asserting /RECONFIG. /RECONFIG is FPGA pin 52 on the 7I43 and pin 44 on the 7I43H.
Note that pin 52 is also USB2CLK input on the 7I43H. This means that you should
not load a standard 7I43/7I43H to a configuration file to a 7I43H and configure the USB
chip for synchronous operation, not only will it not work, it will cause a bus conflict.
CONFIGURATION FILE STARTUP OPTIONS
Important: Because the 7I43s CPLDstops configuration when DONE is asserted,
the configuration file startup options must be set so that asserting DONE is the last
configuration step. Suggested startup options are as follows:
FPGA STARTUP CLOCK: CCLK
DONE: 6
ENABLE OUTPUTS: 5
RELEASE WRITE ENABLE: 4
RELEASE DLL: NO WAIT
SC7I43P and SC7I43W
Two utility programs, SC7I43P.EXE and SC7I43W are provided to send
configurationfilestothe7I43.SC7I43Pis aDOSonlyprogram andSC7I43W isawindows
only program.
SC7I43P is invoked with the FPGA configuration file and the Hexadecimal EPPport base
address on the command line:
SC7I43P FPGAFILE.BIT 378
SC7I43W is invoked with the FPGA configuration file and the COM port on the command
line:
SC7I43W FPGAFILE.BIT COM6
SC7I43P and SC7I43W use binary FPGA configuration files. These files can
standard Xilinx BIT files or Xilinx PROM format files.

7I43 14
OPERATION
CLOCK SIGNALS
The 7I43 has a 50 MHz crystal controlled clock signal routed to pin 53 (GCLK3) on
the FPGA. Four user I/O pins are also GCLK pins:
IO BIT GCLK FPGA PIN IO BIT GCLK FPGA PIN
IOBIT0 GCLK6 127 IOBIT24 GCLK7 128
IOBIT17 GCLK4 124 IOBIT40 GCLK5 125
EPP-FPGA INTERFACE
The interface from host EPP printer port to the FPGA uses 12 FPGA pins. These
consist of an eight bit bidirectional data bus (D0..D7), and four handshake lines. Note that
the handshake lines are fed through the CPLD so depend on the standard CPLD
configuration. The D bus connects to the FPGA through 100 Ohm resistors. These
resistors provide 5V tolerance and series line termination for driving the cable.
P2 PIN EPPNAME SPPNAME FPGA PIN DIRECTION
1 /WRITE /STROBE 84 TO FPGA
2 /DSTROBE /AUTOFD 79 TO FPGA
8 /ASTROBE /SELECTIN 80 TO FPGA
21 WAIT BUSY 82 FROM FPGA
3 D0 D0 68 BIDIR
5 D1 D1 63 BIDIR
7 D2 D2 60 BIDIR
9 D3 D3 59 BIDIR
11 D4 D4 51 BIDIR
13 D5 D5 50 BIDIR
15 D6 D6 47 BIDIR
17 D7 D7 46 BIDIR

7I43 15
OPERATION
EPP-FPGA INTERFACE
The EPP interface implements a simple multiplexed 8 bit data/address bus. The
EPPIOPR8 configuration can be used as an example of an EPP interface in the FPGA.
This is a simple GPIO interface organized as six eight bit ports.
USB-FPGA INTERFACE
The USB interface differs between the 7I43 and 7I43H. The 7I43 uses a FTDI USB
interface chip, the FT245R. This is a Full speed interface chip (12 Mbps max). The
FT245R appears as a single endpoint communication device, basically a simple
bidirectional byte-stream with receive and transmit FIFOs. In order to use the USB
configurationandinterfaceyoumustloadtheappropriatedriversforyouoperatingsystem.
These drivers are available at FTDICHIP.COM. The utilities supplied with the 7I43 utilize
the VCP (Virtual COM Port) series drivers.
The 7I43H uses a FT2232H high speed USB interface chip (480 Mbps). Unlike the
FT245R used in the 7I43, the FT2232H appears as two serial ports. Only the first port is
used by the 7I43H. The supplied configurations support the same FIFOinterface mode as
the 7I43 and the same pinout, but the 7I43H also has the FPGA connections to support
the high speed synchronous mode that allows host transfer rates up to 25M bytes per
second. The default mode is limited to 10 M bytes per second.
The FPGA interface uses a bidirectional 8 bit data bus that is shared with the EPP
interface on the 7I43). Because of this sharing you cannot operate the USB and EPP
interfaces simultaneously.
SIGNAL NAME FPGA PIN DIRECTION FUNCTION
USBWRITE 56 FROM FPGA XMIT DATA STROBE
/USBRD 55 FROM FPGA RECV DATA STROBE
/USBTXE 83 TO FPGA XMIT FIFO NOT FULL
/USBRXF 69 TO FPGA RECV FIFO HAS DATA
D0 68 BIDIR DATA BUS
D1 63 BIDIR DATA BUS
D2 60 BIDIR DATA BUS
D3 59 BIDIR DATA BUS

7I43 16
OPERATION
SIGNAL NAME FPGA PIN DIRECTION FUNCTION
D4 51 BIDIR DATA BUS
D5 50 BIDIR DATA BUS
D6 47 BIDIR DATA BUS
D7 46 BIDIR DATA BUS
ADDITIONAL 7I43H USB INTERFACE PINS
The 7I43H can use the FT2232H’s high speed synchronous FIFO interface mode
and the SPI mode on channel B. These additional pins are connected as follows:
SIGNAL NAME FPGA PIN DIRECTION FUNCTION
USB2CLK 52 TO FPGA SYNC FIFO CLOCK
/USB2OE 82 FROM FPGA SYNC FIFO OUTPUT
ENABLE
UDI 57 FROM FPGA SPI DATA IN
UDO 84 TO FPGA SPI DATA OUT
USK 85 TO FPGA SPI CLOCK
/UCS 79 TO FPGA SPI CHIP SELECT
LEDS
The 7I43 has 8 FPGA driven user LEDS. These green LEDS are located in the top
center of the card. They can be used for any purpose, and can be helpful as a simple
debugging feature. A low output signal from the FPGA lights the LED. See the
7I43MISC.PIN file for FPGA pin locations of the LED signals.
In addition to the user LEDs there are three other LEDS that display board status
information. These status LEDS are on the lower right hand side of the cardjust above the
USB connector, The LEDS are a yellow PWR LED, a red /DONE LED and a red /INIT
LED.The/DONEand/INITLEDcanbeusedtodetermineFPGAconfigurationstatus.The
/INIT LED will be illuminated when /PROGRAM is asserted or when a CRC error has
occurred during the configuration process. The /DONE LED will be illuminated when the
FPGA is not configured.