Micrel MICRF506 User manual

MICRF506
410MHz and 450MHz ISM Band
Transceiver
General Description
The MICRF506 is a true single-chip, frequency shift keying
(FSK) transceiver intended for use in half-duplex,
bidirectional RF links. The multi-channeled FSK transceiver
is intended for UHF radio equipment in compliance with the
European Telecommunication Standard Institute (ETSI)
specification, EN300 220.
The transmitter consists of a PLL frequency synthesizer
and power amplifier. The frequency synthesizer consists of
a voltage-controlled oscillator (VCO), a crystal oscillator,
dual modulus prescaler, programmable frequency dividers,
and a phase-detector. The loop-filter is external for flexibility
and can be a simple passive circuit. The output power of
the power amplifier can be programmed to seven levels. A
lock-detect circuit detects when the PLL is in lock. In
receive mode, the PLL synthesizer generates the local
oscillator (LO) signal. The N, M, and A values that give the
LO frequency are stored in the N0, M0, and A0 registers.
The receiver is a zero intermediate frequency (IF) type
which makes channel filtering possible with low-power,
integrated low-pass filters. The receiver consists of a low
noise amplifier (LNA) that drives a quadrature mix pair. The
mixer outputs feed two identical signal channels in phase
quadrature. Each channel includes a pre-amplifier, a third
order Sallen-Key RC low-pass filter that protects the
following switched-capacitor filter from strong adjacent
channel signals, and a limiter. The main channel filter is a
switched-capacitor implementation of a six-pole elliptic low
pass filter. The cut-off frequency of the Sallen-Key RC filter
can be programmed to four different frequencies: 100kHz,
150kHz, 230kHz, and 340kHz. The I and Q channel
outputs are demodulated and produce a digital data output.
The demodulator detects the relative phase of the I and the
Q channel signal. If the I channel signal lags behind the Q
channel, the FSK tone frequency is above the LO
frequency (data '1'). If the I channel leads the Q channel,
the FSK tone is below the LO frequency (data '0'). The
output of the receiver is available on the DataIXO pin. A
receive signal strength indicator (RSSI) circuit indicates the
received signal level. All support documentation can be
found on Micrel’s web site at www.micrel.com.
RadioWire®
Features
•True single chip transceiver
•Digital bit synchronizer
•Received signal strength indicator (RSSI)
•RX and TX power management
•Power down function
•Reference crystal tuning capabilities
•Frequency error estimator
•Baseband shaping
•Three-wire programmable serial interface
•Register read back function
Applications
•Telemetry
•Remote metering
•Wireless controller
•Remote data repeater
•Remote control systems
•Wireless modem
•Wireless security system
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General Description....................................................................................................................................................1
Features......................................................................................................................................................................1
Applications ................................................................................................................................................................1
RadioWire® RF Selection Guide................................................................................................................................4
Ordering Information...................................................................................................................................................4
Block Diagram ............................................................................................................................................................4
Pin Configuration ........................................................................................................................................................5
Pin Description............................................................................................................................................................5
Absolute Maximum Ratings
(1)
.....................................................................................................................................6
Operating Ratings
(2)
....................................................................................................................................................6
Electrical Characteristics
(4)
.........................................................................................................................................6
Programming ..............................................................................................................................................................9
Writing to the control registers in MICRF506 ...........................................................................................................10
Writing to a Single Register ......................................................................................................................................10
Writing to All Registers .............................................................................................................................................11
Writing to n Registers having Incremental Addresses..............................................................................................11
Writing to n Registers having Non-Incremental Addresses......................................................................................12
Reading from the control registers in MICRF506 .....................................................................................................12
Programming interface timing...................................................................................................................................12
Power on Reset ........................................................................................................................................................13
Programming summary ............................................................................................................................................14
Frequency Synthesizer.............................................................................................................................................15
Crystal Oscillator (XCO)........................................................................................................................................16
VCO ......................................................................................................................................................................17
Charge Pump........................................................................................................................................................18
PLL Filter...............................................................................................................................................................18
Lock Detect ...........................................................................................................................................................18
Modes of Operation ..............................................................................................................................................18
Transceiver Sync/Non-Synchronous Mode..............................................................................................................19
Data Interface ...........................................................................................................................................................19
Receiver....................................................................................................................................................................20
Front End ..............................................................................................................................................................20
Sallen-Key Filters..................................................................................................................................................20
Switched Capacitor Filter ......................................................................................................................................21
RSSI......................................................................................................................................................................21
FEE .......................................................................................................................................................................22
Bit Synchronizer....................................................................................................................................................23
Transmitter................................................................................................................................................................24
Power Amplifier.....................................................................................................................................................24
Modulator ..............................................................................................................................................................26
Using the XCO-tune Bits ..........................................................................................................................................28
Typical Application....................................................................................................................................................30

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MICRF506BML/YML Land pattern ...........................................................................................................................31
Layout Considerations..............................................................................................................................................32
Package Information MICRF506BML.......................................................................................................................33
Package Information MICRF506YML.......................................................................................................................34
Overview of programming bit....................................................................................................................................35
Table 1: Detailed description of programming bit.....................................................................................................35
Table 2: Main Mode bit .............................................................................................................................................40
Table 3: Synchronizer mode bit................................................................................................................................40
Table 4: Modulation bit .............................................................................................................................................40
Table 5: Prefilter bit...................................................................................................................................................40
Table 6: Power amplifier bit ......................................................................................................................................41
Table 7:Generation of Bitrate_clk, BitSync_clk and Mod_clk...................................................................................41
Table 8: Test signals.................................................................................................................................................41
Table 10: Frequency Error Estimation control bit .....................................................................................................42
Table 11: Frequency Error Estimation control bit, cont. ...........................................................................................42

Micrel MICRF506BML/YML
RadioWire® RF Selection Guide
Device Frequency Range
Maximum
Data Rate Receive Supply
Voltage Transmit Modulation
Type Package
MICRF500 700MHz – 1.1GHz 128k Baud 12mA 2.5 to 3.4V 50mA FSK LQFP-44
MICRF501 300MHz – 440MHz 128k Baud 8mA 2.5 to 3.4V 45mA FSK LQFP-44
MICRF505 850MHz – 950MHz 200k Baud 13mA 2.0 to 2.5V 28mA FSK MLF™-32
MICRF506 410MHz – 450MHz 200k Baud 12mA 2.0 to 2.5V 21.5mA FSK MLF™-32
MICRF405 290-980MHz 200k Baud NA 2.0-3.6V 18mA FSK/ASK MLF™-24
Ordering Information
Part Number Junction Temp. Range
(1)
Package
MICRF506YML TR –40° to +85°C Lead free 32-Pin MLF
TM
MICRF506BML TR –40° to +85°C 32-Pin MLF
TM
____________________________________________________________________________________________________
Block Diagram
VCO
Bias
RSSI
DATAIXO
DATACLK
VARINXTALOUT
XTALIN CPOUT
LD
PTATBIAS
ANT
LNA
Sallen-key
Sallen-key
Main
filter
Main
filter
IFAMP
PA
DIV 4
IFAMP
LO-Buffer
PA-buffer
Frequency
Synthesiser
Demodulator
Clock recovery
Modulator
Deviation control
RSSI
XCO
Control logic
CS
IO
SCLK
CIBIAS
LC Filter
Loop
filter
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Pin Configuration
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10111213141516
32 3130 29 28 27 26 25
RFGND
P
TATBIAS
RFVDD
RFGND
ANT
RFGND
GND
NC
XTALOU
T
XTALIN
CS
SCLK
IO
DATAIXO
DATACL
K
NC
GND VARIN VCOGN
D
VCOVD
D
NC CPOUT DIGGND DIGVDD
Q
CHOUT
ICHOUT
IFGND
IFVDD
CIBIAS
RSSI
LD
NC
MICRF506BML
32-Pin MLF
TM
Pin Description
Pin
Number Pin Name Type Pin Function
1 RFGND LNA and PA ground.
2 PTATBIAS O Connection for bias
resistor.
3 RFVDD LNA and PA power
supply.
4 RFGND LNA and PA ground.
5 ANT I/O Antenna In/Output.
6 RFGND LNA and PA ground.
7 RFGND LNA and PA ground.
8 NC No connect.
9 CIBIAS O Connection for bias
resistor.
10 IFVDD IF/mixer power
supply.
11 IFGND IF/mixer ground.
12 ICHOUT O Test pin.
13 QCHOUT O Test pin.
14 RSSI O Received signal
strength indicator.
15 LD O PLL lock detect.
16 NC No connect.
17 NC No connect
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Pin
Number Pin Name Type Pin Function
18 DATACLK O RX/TX data clock
output.
19 DATAIXO I/O RX/TX data
input/output.
20 IO I/O 3-wire interface data
in/output.
21 SCLK I 3-wire interface serial
clock.
22 CS I 3-wire interface chip
select.
23 XTALIN I Crystal oscillator
input.
24 XTALOUT O Crystal oscillator
output.
25 DIGVDD Digital power supply.
26 DIGGND Digital ground.
27 CPOUT O PLL charge pump
output.
28 GND Substrate ground.
29 VARIN I VCO varactor.
30 VCOGND VCO ground.
31 VCOVDD VCO power supply.
32 NC No connect.

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Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
) ........................................ +2.7V
Voltage on any pin (GND = 0V). .....-0.3V to 2.7V
Storage Temperature (T
s
)................ -55°C to +150°C
ESD Rating
(3)
....................................................... 2kV
Operating Ratings
(2)
Supply voltage (V
IN
) ............................+2.0V to +2.5V
RF Frequencies ..........................410MHz to 450MHz
Data Rate ................................................ <200kBaud
Ambient Temperature (T
A
)................ –40°C to +85°C
Package Thermal Resistance
MLF
TM
(θ
JA
)........................................... 41.7°C/W
Electrical Characteristics
(4)
f
RF
= 433MHz. Data-rate = 125kbps, Modulation type = closed-loop VCO modulation, V
DD
= 2.5V; T
A
= 25°C, bold
values indicate –40°C<T
A
< +85°C, unless noted.
Symbol Parameter Condition Min Typ Max Units
RF Frequency Operating Range 410 450 MHz
Power Supply 2.0 2.5 V
Power Down Current 0.3 3 µA
Standby Current 280
µA
VCO and PLL Section
Reference Frequency 4 40 MHz
433.75MHz to 434.25MHz 0.7 1.3 msPLL Lock Time
(5)
3kHz bandwidth 430MHz to 440MHz 1.3 2 ms
PLL Lock Time
(5)
20kHz bandwidth
433.75MHz to 434.25MHz 0.3 ms
Rx – Tx 1.0 1.4 ms
Tx – Rx 1.0 2.5 ms
Standby Rx 1.0 3 ms
Switch Time
(5)
3kHz loop bandwidth
Standby Tx 1.0 ms
Crystal Oscillator Start-Up Time 16MHz, 9pF load, 5.6pF loading
capacitors
1.0 ms
VCP
OUT
= 1.1V, CP_HI = 0 100 125 170 µA Charge Pump Current VCP
OUT
= 1.1V, CP_HI = 1 420 500 680 µA
Transmit Section
R
LOAD
= 50Ω, Pa2-0-111 11 dBm
Output Power R
LOAD
= 50Ω, Pa2-0-001 -7 dBm
Over temperature range 1 dBOutput Power Tolerance Over power supply range 3 dB
R
LOAD
= 50Ω, Pa2-0-111 21.5 mA
R
LOAD
= 50Ω, Pa2-0-001 10.5 mA
Tx Current Consumption
R
LOAD
= 50Ω, Pa2-0-000 8.0 mA
Binary FSK Frequency
Separation
(5)
Birate = 200kbps 20 500 kHz
VCO modulation 20 200 kbpsData Rate
(5)
Divider modulation 20 kbps

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Symbol Parameter Condition Min Typ Max Units
38.4kbps, β= 2, 20dBc 140 kHz
125kbps, β= 2, 20dBc 550 kHz
Occupied bandwidth
(5)
200kbps, β= 2, 20dBc 800 kHz
Harmonics 434MHz
(5)
-36 dBm
Spurious Emission in Restricted
bands < 1GHz
(5)
-54 dBm
Spurious Emission < 1GHz
(5)
-36 dBm
Spurious Emission > 1GHz
(5)
ETSI EN300 220
(Using antenna matching network)
-30 dBm
Receive Section
All functions turned on 12 mA
LNA bypass 10.3 mA
Switch cap filter bypass with LNA 9.8 mA
Rx Current Consumption
Bypass of Switch cap and LNA 8.0 mA
Rx Current Consumption Variation Over temperature 3 mA
2.4kbps, β= 16, BER 10
-3
-113 dBm
4.8kbps, β= 16, BER 10
-3
-111 dBm
19.2kbps, β= 4, BER 10
-3
-106 dBm
38.4kbps, β= 4, BER 10
-3
-104 dBm
76.8kbps, β= 2, BER 10
-3
-101 dBm
125kbps, β= 2, BER 10
-3
-100 dBm
Receiver Sensitivity
200kbps, β= 2, BER 10
-3
-97 dBm
125kbps, 125kHz deviation +12 dBmReceiver Maximum Input Power 20kbps, 40kHz deviation +2 dBm
Over temperature 4 dBReceiver Sensitivity Tolerance Over power supply range 1 dB
Receiver Bandwidth 50 350 kHz
Co-Channel Rejection 19.2 kbps, β= 6, SC=133 kHz -8 dB
500kHz spacing, 19.2kbps, Main
filter cut off frequency 133kHz
48 dB
Adjacent Channel Rejection 1MHz ,19.2kbps, Main filter cut off
frequency 133kHz
56 dB
Offset ±1MHz 61 dB
Offset ±2MHz 58 dB
Offset ±5MHz 46 dB
Offset ±10MHz 62 dB
Blocking
Desired signal:
19.2 kbps, β=6,
3dB above sens,
SC=133 kHz
Offset ±30MHz 75 dB
1dB Compression -34 dBm
Input IP3 2 tones with 1MHz separation -25 dBm
LO Leakage -90 dBm
<1GHz, EN 300 220 -57 dBmSpurious Emission
(5)
>1GHz, EN 300 220 -47 dBm
Input Impedance
(5)
50
Ω

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Symbol Parameter Condition Min Typ Max Units
RSSI Dynamic Range 50 dB
Pin = -110dBm 0.9 VRSSI Output Range Pin = -60dBm 2 V
Digital Inputs/Outputs
V
IH
Logic Input High 0.7V
DD
V
DD
V
V
IL
Logic Input Low 0 0.3V
DD
V
Clock/Data Frequency
(5)
10 MHz
Clock/Data Duty Cycle
(5)
45 55 %
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. Specification for packaged product only.
5. Guaranteed by design.

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Programming
General
The MICRF506 functions are enabled through a
number of programming bits. The programming bits
are organized as a set of addressable control
registers, each register holding 8 bits.
There are 23 control registers in total in the
MICRF506, and they have addresses ranging from 0
to 22. The user can read all the control registers.
The user can write to the first 22 registers (0 to 21);
the register 22 is a read-only register.
All control registers hold 8 bits and all 8 bits must be
written to when accessing a control register, or they
will be read. Some of the registers do not utilize all 8
bits. The value of an unused bit is “don’t care.”
The control register with address 0 is referred to as
ControlRegister0, the control register with address 1
is ControlRegister1 and so on. A summary of the
control registers is given in the table below. In
addition to the unused bits (marked with”-“) there are
a number of mandatory bits (marked with “0” or “1”).
Always maintain these as shown in the table.
The control registers in MICRF506 are accessed
through a 3-wire interface; clock, data and chip
select. These lines are referred to as SCLK, IO, and
CS, respectively. This 3-wire interface is dedicated
to control register access and is referred to as the
control interface. Received data (via RF) and data to
transmit (via RF) are handled by the DataIXO and
DataClk (if enabled) lines; this is referred to as the
data interface.
The SCLK line is applied externally; access to the
control registers are carried out at a rate determined
by the user. The MICRF506 will ignore transitions on
the SCLK line if the CS line is inactive. The
MICRF506 can be put on a bus, sharing clock and
data lines with other devices.
All control registers should be written to after a
battery reset. During operation, it is sufficient to write
to one register only. The MICRF506 will
automatically enter power down mode after a battery
reset.
Adr Data
A6…A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0
0000010 CP_HI SC_by ‘0’ PA_By OUTS3 OUTS2 OUTS1 OUTS0
0000011 ‘1’ ‘1’ ‘0’ VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0
0000100 Mod_F2 Mod_F1 Mod_F0 Mod_I4 Mod_I3 Mod_I2 Mod_I1 Mod_I0
0000101 - - ‘0’ ‘1’ Mod_A3 Mod_A2 Mod_A1 Mod_A0
0000110 - Mod_clkS2 Mod_clkS1 Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0
0001000 ‘1’ ‘1’ ‘0’ ScClk4 ScClk3 ScClk2 ScClk1 ScClk0
0001001 ‘0’ ‘0’ ‘1’ XCOtune4 XCOtune3 XCOtune2 XCOtune1 XCOtune0
0001010 - - A0_5 A0_4 A0_3 A0_2 A0_1 A0_0
0001011 - - - - N0_11 N0_10 N0_9 N0_8
0001100 N0_7 N0_6 N0_5 N0_4 N0_3 N0_2 N0_1 N0_0
0001101 - - - - M0_11 M0_10 M0_9 M0_8
0001110 M0_7 M0_6 M0_5 M0_4 M0_3 M0_2 M0_1 M0_0
0001111 - - A1_5 A1_4 A1_3 A1_2 A1_1 A1_0
0010000 - - - - N1_11 N1_10 N1_9 N1_8
0010001 N1_7 N1_6 N1_5 N1_4 N1_3 N1_2 N1_1 N1_0
0010010 - - - - M1_11 M1_10 M1_9 M1_8
0010011 M1_7 M1_6 M1_5 M1_4 M1_3 M1_2 M1_1 M1_0
0010100 ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’
0010101 - - - - FEEC_3 FEEC_2 FEEC_1 FEEC_0
0010110 FEE_7 FEE_6 FEE_5 FEE_4 FEE_3 FEE_2 FEE_1 FEE_0
Names of programming bits, unused bits (“-“) and mandatory bits (“1” or “0”) are shown. Change of mandatory bits may cause malfunction.
Table 1. Control Registers in MICRF506

Micrel MICRF506BML/YML
Writing to the control registers in MICRF506
Writing: A number of octets are entered into
MICRF506 followed by a load-signal to activate the
new setting. Making these events is referred to as a
“write sequence.” It is possible to update all, 1, or n
control registers in a write sequence. The address to
write to (or the first address to write to) can be any
valid address (0-21). The IO line is always an input
to the MICRF506 (output from user) when writing.
What to write:
•The address of the control register to write
to (or if more than 1 control register should
be written to, the address of the 1
st
control
register to write to).
•A bit to enable reading or writing of the
control registers. This bit is called the R/W
bit.
•The values to write into the control
register(s).
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What to write:
Field Comments
Address: A 7-bit field, ranging from 0 to 21. MSB is
written first.
R/W bit: A 1-bit field, = “0” for writing
Values: A number of octets (1-22 octets). MSB in
every octet is written first. The first octet is
written to the control register with the
specified address (=”Address”). The next
octet (if there is one) is written to the control
register with address = “Address + 1” and so
on.
Table 2.
How to write:
Bring CS active to active to start a write sequence.
The active state of the CS line is “high.” Use the
SCLK/IO serial interface to clock “Address” and
“R/W” bit and “Values” into the MICRF506.
MICRF506 will sample the IO line at negative edges
of SCLK. Make sure to change the state of the IO
line before the negative edge. Refer to figures
below.
Bring CS inactive to make an internal load-signal
and complete the write-sequence. Note: there is an
exception to this point. If the programming bit called
“load_en” (bit0 in ControlRegister0) is “0”, then no
load pulse is generated.
The two different ways to “program the chip” are:
•Write to a number of control registers (0-22)
when the registers have incremental
addresses (write to 1, all or n registers)
•Write to a number of control registers when
the registers have non-incremental
addresses.
Writing to a Single Register
Writing to a control register with address “A6. A5,
…A0” is described here. During operation, writing to
1 register is sufficient to change the way the
transceiver works. Typical example: Change from
receive mode to power-down.
What to write:
Field Comments
Address: 7 bit = A6, A5, …A0 (A6 = msb. A0 = lsb)
R/W bit: “0” for writing
Values: 8 bits = D7, D6, …D0 (D7 = msb, D0 = lsb)
Table 3.
“Address” and “R/W bit” together make 1 octet.
In addition, 1 octet with programming bits is entered. In
total, 2 octets are clocked into the MICRF506.
How to write:
•Bring CS high
•Use SCLK and IO to clock in the 2 octets
•Bring CS low
C
S
SCLK
IO A6 A5 A0 RW D7 D6 D2 D1 D0
Address of register i RW Data to write into register i
Internal load pulse made here
Figure 1.
In Figure 1, IO is changed at positive edges of SCLK. The
MICRF506 samples the IO line at negative edges. The
value of the R/W bits is always “0” for writing.

Micrel MICRF506BML/YML
Writing to All Registers
After a power-on, all writable registers should be
written. This is described here.
Writing to all register can be done at any time. To
get the simplest firmware, always write to all
registers. The price to pay for the simplicity is
increased write-time, which leads to increased time
to change the way the MICRF506 works.
What to write
Field Comments
Address: ‘000000’ (address of the first register to write
to, which is 0)
R/W bit: “0” for writing
Values: 1
st
Octet: wanted values for
ControlRegister0. 2
nd
Octet: wanted values
for ControlRegister1 and so on for all of the
octets. So the 22
nd
octet wants values for
ControlRegister21. Refer to the specific
sections of this document for actual values.
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Table 4.
“Address” and “R/W bit” together make 1 octet.
In addition, 22 octets with programming bits are entered.
In total, 23 octets are clocked into the MICRF506.
How to write:
•Bring CS high
•Use SCLK and IO to clock in the 23 octets
•Bring CS low
Refer to the figure in the next section, “Writing to n
registers having incremental addresses”.
Writing to n Registers having Incremental
Addresses
In addition to entering all bytes, it is also possible to
enter a set of n bytes, starting from address i = “A6,
A5, … A0”. Typical example: Clock in a new set of
frequency dividers (i.e. change the RF frequency).
“Incremental addresses”. Registers to be written are
located in i, i+1, i+2.
What to write
Field Comments
Address: 7 bit = A6, A5, …A0 (A6 = msb. A0 = lsb)
(address of first byte to write to)
R/W bit: “0” for writing
Values: n* 8 bits =
D7, D6, …D0 (D7 = msb, D0 = lsb) (written
to control reg. with address ”i”)
D7, D6, …D0 (D7 = msb, D0 = lsb) (written
to control reg. with address ”i+1”)
D7, D6, …D0 (D7 = msb, D0 = lsb) (written
to control reg. with address ”i+n-1”)
Table 5.
“Address” and “R/W bit” together make 1 octet.
In addition, n octets with programming bits are entered.
Totally, 1 +n octets are clocked into the MICRF506.
How to write:
•Bring CS high
•Use SCLK and IO to clock in the 1 + n
octets
•Bring CS low
In Figure 1, IO is changed at positive edges of SCLK. The
MICRF506 samples the IO line at negative edges. The
value of the R/W bits is always “0” for writing.
C
S
SCLK
IO A6 A5 A0 RW D7 D6 D2 D1 D0
Address of first RW
register to write to,
register i
Data to write
into register i
Internal load pulse made here
Data to write
into register i+1
Figure 2.

Micrel MICRF506BML/YML
Writing to n Registers having Non-Incremental
Addresses
Registers with non-incremental addresses can be
written to in one write-sequence as well. Example of
non-incremental addresses: “0,1,3”. However, this
requires more overhead, and the user should
consider the possibility to make a “continuous”
update, for example, by writing to “0,1,2,3” (writing
the present value of “2” into “2”). The simplest
firmware is achieved by always writing to all
registers. Refer to previous sections.
This write-sequence is divided into several sub-
parts:
•Disable the generation of load-signals by
clearing bit “load_en” (bit0 in
ControlRegister0)
•Repeat for each group of register having
incremental addresses:
oBring CS active
oEnter first address for this group,
R/W bit and values
oBring CS inactive
oFinally, enable and make a load-
signal by setting “load_en”
Refer to the previous sections for how to write to 1 or
n (with incremental addresses) registers in the
MICRF506.
Reading from the control registers in MICRF506
The “read-sequence” is:
1. Enter address and R/W bit
2. Change direction of IO line
3. Read out a number of octets and change IO
direction back again.
It is possible to read all, 1 or n registers. The
address to read from (or the first address to read
from) can be any valid address (0-22). Reading is
not destructive, i.e. values are not changed. The IO
line is output from the MICRF506 (input to user) for a
part of the read-sequence. Refer to procedure
description below.
A read-sequence is described for reading n
registers, where n is number 1-23.
Reading n registers from MICRF506
CS
SCLK
IO A6 A5 A0 RW D7 D6 D0
Address of register i RWData read from reg. i
S
imple time
I
O Input
I
O Output
Figure 3.
In the figure, 1 register is read. The address is A6,
A5, … A0. A6 = msb. The data read out is D7, D6,
…D0. The value of the R/W bit is always “1” for
reading.
SCLK and IO together form a serial interface. SCLK
is applied externally for reading as well as for writing.
•Bring CS active
•Enter address to read from (or the first
address to read from) (7 bits) and
•The R/W bit = 1 to enable reading
•Make the IO line an input to the user (set pin
in tristate)
•Read n octets. The first rising edge of SCLK
will set the IO as an output from the
MICRF506. MICRF will change the IO line at
positive edges. The user should read the IO
line at the negative edges.
•Make the IO line an output from the user
again.
Programming interface timing
Figure 4 and Table 6 shows the timing specification for the
3-wire serial programming interface.
C
S
S
CLK
I
OA6 A5 A0 RW D7 D6 D2 D1 D0
Address Register Data Register
LOA
D
Tscl
Twrite
TreadThigh
Tlow
TperTcsr traise
tfall
Figure 4.
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Micrel MICRF506BML/YML
Values
Symbol Parameter Min. Typ. Max. Units
Tper Min. period of
SCLK
50 ns
Thigh Min. high time of
SCLK
20 ns
Tlow Min. low time of
SCLK
20 ns
tfall Max. time of
falling edge of
SCLK
1 µs
trise Max. time of rising
edge of SCLK
1 µs
Tcsr Max. time of rising
edge of CS to
falling edge of
SCLK
0 ns
Tcsf Min. delay from
rising edge of CS
to rising edge of
SCLK
5 ns
Twrite Min. delay from
valid IO to falling
edge of SCLK
during a write
operation
0 ns
Tread Min. delay from
rising edge of
SCLK to valid IO
during a read
operation
(assuming load
capacitance of IO
is 25pF)
75 ns
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Table 6. Timing Specification for the 3-wire
Programming Interface
Power on Reset
When applying voltage to the MICRF506 a power
on reset state is entered. During the time period of
power on reset, the MICRF506 should be
considered to be in an unknown state and the user
should wait until completed (See Table 6). The
power on reset timing given in table 6 is covering all
conditions and should be treated as a maximum
delay time. In some application it might be beneficial
to minimize the power on reset time. In these cases
we recommend to follow below procedure:

Micrel MICRF506BML/YML
July 2006 14
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Programming summary
•Use CS, SCLK, and IO to get access to the
control registers in MICRF506.
•SCLK is user-controlled.
•Write to the MICRF506 at positive edges
(MICRF506 reads at negative edges).
•Read from the MICRF506 at negative edges
(MICRF506 writes at positive edges)
•After power-on: Write to the complete set of
control registers.
•Address field is 7 bits long. Enter msb first.
•R/W bit is 1 bit long (“1” for read, “0” for
write)
•Address and R/W bit together make 1 octet
•All control registers are 8 bits long.
Enter/read msb in every octet first.
•Always write 8 bits to/read 8 bits from a
control register. This is the case for registers
with less than 8 used programming bits as
well.
•Writing: Bring CS high, write address and
R/W bit followed by the new values to fill into
the addressed control register(s) and bring
CS low for loading, i.e. activation of the new
control register values (“load_en” = 1).
•Reading: Bring CS high, write address and
R/W bit, set IO as an input, read present
contents of the addressed control
register(s), bring CS low and set IO an
output.

Micrel MICRF506BML/YML
Frequency Synthesizer
The MICRF506 frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, dual
modulus prescaler, programmable frequency dividers and a phase-detector. The loop-filter is external for flexibility
and can be a simple passive circuit. The phase detector compares frequencies of two signals and produces an
error signal which is proportional to the difference between the input frequencies. The error signal is used to
control a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed
through a frequency divider back to the input of the phase detector, producing a feedback loop. If the output
frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the
error. Thus the output is locked to the frequency at the other input. This input is called the reference and is
derived from a crystal oscillator, which is very stable in frequency. The block diagram below shows the basic
elements and arrangement of a PLL based frequency synthesizer. The MICRF506 has a dual modulus prescaler
for increased frequency resolution. In a dual modulus prescaler the main divider is split into two parts, the main
part N and an additional divider A, where A < N. Both dividers are clocked from the output of the dual-modulus
prescaler, but only the output of the N divider is fed into the phase detector. The prescaler will first divide by 16.
Both N and A count down until A reaches zero, at which point the prescaler is switched to a division ratio 16+1. At
this point, the divider N has completed A counts. Counting continues until N reaches zero, which is an additional
N-A counts. At this point the cycle repeats.
Phase
detector
Prescaler N-Divider
M-Divider
Div/4
1800MHz
Loop filter
XCO
VCO
Charge pump
A-Divider
PA
A6…A0 D7 D6 D5 D4 D3 D2 D1 D0
0001010 - - A0_5 A0_4 A0_3 A0_2 A0_1 A0_0
0001011 - - - - N0_11 N0_10 N0_9 N0_8
0001100 N0_7 N0_6 N0_5 N0_4 N0_3 N0_2 N0_1 N0_0
0001101 - - - - M0_11 M0_10 M0_9 M0_8
0001110 M0_7 M0_6 M0_5 M0_4 M0_3 M0_2 M0_1 M0_0
0001111 - - A1_5 A1_4 A1_3 A1_2 A1_1 A1_0
0010000 - - - - N1_11 N1_10 N1_9 N1_8
0010001 N1_7 N1_6 N1_5 N1_4 N1_3 N1_2 N1_1 N1_0
0010010 - - - - M1_11 M1_10 M1_9 M1_8
0010011 M1_7 M1_6 M1_5 M1_4 M1_3 M1_2 M1_1 M1_0
July 2006 15
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Micrel MICRF506BML/YML
The lengths of the N, M, and A registers are 12, 12
and 6 respectively The values can be calculated
from the following formula:
()()
AN16
2f
2AN16
f
M
f
fRF
VCOXCO
PhD +×
×
=
×+×
==
M≠0
1 ≤A < N
where
f
PhD
: Phase detector comparison frequency
f
XCO
: Crystal oscillator frequency
f
VCO
: Voltage controlled oscillator frequency
f
RF
: RF carrier frequency
There are two sets of each of the divide factors (i.e.
A0 and A1). If modulation by using the dividers is
selected (that is Modulation1=1, Modulation0=0), the
two sets should be programmed to give two RF
frequencies, separated by two times the specified
frequency deviation. For all other modulation
methods, and also in receive mode, the 0-set will be
used.
Crystal Oscillator (XCO)
Adr D7 D6 D5 D4 D3 D2 D1 D0
0001001 ‘0’ ‘0’ ‘1’ XCOtune4 XCOtune3 XCOtune2 XCOtune1 XCOtune0
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The crystal oscillator is a very critical block. As the
crystal oscillator is a reference for the RF output
frequency and also for the LO frequency in the
receiver, very good phase and frequency stability is
required. The schematic of the crystal oscillator’s
external components for 16MHz are shown in Figure
5.
C11
5.6pF
C10
5.6pF
Y1
TSX-10A
Pin 24
X
TALOUT Pin 2
3
XTALI
N
Figure 5. Crystal Oscillator Circuit
The crystal should be connected between pins
XTALIN and XTALOUT (pin 23 and 24). In addition,
loading capacitors for the crystal are required. The
loading capacitor values depend on the total load
capacitance, C
L
, specified for the crystal. The load
capacitance seen between the crystal terminals
should be equal to C
L
for the crystal to oscillate at
the specified frequency.
C
L
=1
1
C
10
+1
C
11
+C
parasitic
The parasitic capacitance is the pin input
capacitance and PCB stray capacitance. Typically,
the total parasitic capacitance is around 6pF. For
instance, for a 9pF load crystal the recommended
values of the external load capacitors are 5.6pF.
It is also possible to tune the crystal oscillator
internally by switching in internal capacitance using
5 tune bits XCOtune4 – XCOtun0. When XCOtune4
– XCOtune0 = 0 no internal capacitors are
connected to the crystal pins. When XCOtune4 –
XCOtune0 = 1 all of the internal capacitors are
connected to the crystal pins. Figure 6 shows the
tuning range for two different capacitor values, 1.5pF
and no capacitors.
The crystal used is a TN4-26011 from Toyocom.
Specification: Package TSX-10A, Nominal frequency
16.000000 MHz, frequency tolerance ±10ppm,
frequency stability ±9ppm, load capacitance 9pF,
pulling sensitivity 15ppm/pF. When the external
capacitors are set to 1.5pF and the XCOtune=16,
the total capacitance will normally be ~9pF.
-60,0
-40,0
-20,0
0,0
20,0
40,0
60,0
80,0
100,0
0 8 16 24 32
XCO bitvalue
[ppm]
2x1.5pF
2x0pF
Figure 6. XCO Tuning
The start up time is given in Table 7. As can be
seen, more capacitance will slow down the start up
time.
The start-up time of a crystal oscillator is typically
around a millisecond. Therefore, to save current
consumption, the XCO is turned on before any other
circuit block. During start-up the XCO amplitude will
eventually reach a sufficient level to trigger the M-
counter. After counting 2 M-counter output pulses
the rest of the circuit will be turned on. The current
consumption during the prestart period is
approximately 280µA.

Micrel MICRF506BML/YML
XCOtune Start-up Time (µs)
0 590
1 590
2 700
4 700
8 810
16 1140
31 2050
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Table 7. Typical values with C
EXT
= 1.5pF
If an external reference is used instead of a crystal,
the signal shall be applied to pin 24, XTALOUT. Due
to internal DC setting in the XCO, an AC coupling is
recommended to be used between the external
reference and the XTALOUT-pin.
VCO
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000011 ‘1’ ‘1’ ‘0’ VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0
The VCO has no external components. If has three
bit to set the bias current and two bit to set the VCO
frequency. These five bit are set by the RF
frequency, as follows:
RF freq. VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0
410MHz 1 0 1 0 1
410-423MHz 1 0 1 0 1
423-436MHz 1 0 0 1 0
436-450MHz 0 1 1 1 1
Table 8. VCO Bit Setting
The bias bit will optimize the phase noise, and the
frequency bit will control a capacitor bank in the
VCO. The tuning range, the RF frequency versus
varactor voltage, is dependent on the VCO
frequency setting, and can be shown in Figure 7.
When the tuning voltage is in the range from 0.9V to
1.4V, the VCO gain is at its maximum, approximately
32 to 35MHz/V. It is recommended that the varactor
voltage stays in this range.
The input capacitance at the varactor pin must be
taken into consideration when designing the PLL
loop filter. This is most critical when designing a loop
filter with high bandwidth, which gives relatively
small component values. The input capacitance is
approximately 6pF.
VCO frequency gain, Vdd=2.5V
380
390
400
410
420
430
440
450
460
470
480
0 0.4 0.8 1.2 1.6 2 2.4
V_varactor [V]
Freq [MHz]
11
10
01
00
Figure 7. RF Frequency vs. Varactor Voltage
and VCO Frequency bit (V
DD
= 2.25V)

Micrel MICRF506BML/YML
Charge Pump
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000010 CP_HI SC_by ‘0’ PA_by OUTS3 OUTS2 OUTS1 OUTS1
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The charge pump current can be set to either 125µA
or 500µA by CP_HI (‘1’ →500µA). This will affect
the loop filter component values, see “PLL Filter”
section. In most cases, the low current is best suited.
For applications using phase detector frequency and
high PLL bandwidth, the 500µA can be a better
choice.
PLL Filter
The design of the PLL filter will strongly affect the
performance of the frequency synthesizer. The PLL
filter is kept externally for flexibility. Input parameters
when designing the loop filter for the MICRF506 are
mainly the modulation method and the bit rate.
These choices will also affect the switching time and
phase noise.
The frequency modulation can be done in two
different ways with the MICRF506, either by VCO
modulation or by modulation with the internal
dividers (see chapter Frequency modulation for
further details). In the first case, the PLL needs to
lock on a new carrier frequency for every new data
bit. Now the PLL bandwidth needs to be adequately
high. It is recommended to use a third order filter to
suppress the phase detector frequency, as this is
not suppressed as much as when doing modulation
on the VCO with a lower bandwidth filter.
A schematic for a second (R2=0 and C3=NC) and
third order loop filter is shown in Figure 8.
C3C1
Pin 27
C
P_OUT
Pin 29
VARI
N
C2
R2
R1
Figure 8. Second and Third Order Loop Filter
Table 9 shows three different loop filters, the two first
for VCO modulation and the last one for modulation
using the internal dividers. The component values
are calculated with RF frequency = 434MHz, VCO
gain = 32MHz/V and charge pump current = 125µA.
Other settings are shown in the table. The varactor
pin capacitance (pin 29) of 5pF does not influence
on the component values for the two filters with
lowest bandwidth.
Baud Rate
(kbaud/sec)
PLL
BW
(kHz)
Phase
Margin(˚)
Phase
Detector
Freq.
(kHz)
C1 C2 R1 R2 C3
VCO >38.4 0.8 56 100 10nF 100nF 6.2kΩ0 NC
VCO >125 3,2 56 100 680pF 6.8nF 22kΩ0 NC
Divider <20 13 86 500 150pF 10nF 18kΩ82kΩ4.7pF
Table 9. Loop Filter Components Values
Lock Detect
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0
A lock detector can be enabled by setting LD_en
= 1. When pin LD is high, it indicates that the
PLL is in lock.
Modes of Operation
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
Mode1 Mode0 State Comments
0 0 Power down Keeps register configuration
0 1 Standby Only crystal oscillator running
1 0 Receive Full receive
1 1 Transmit Full transmit ex PA state

Micrel MICRF506BML/YML
Transceiver Sync/Non-Synchronous Mode
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
0000110 - Mod_clkS2 Mod_clkS1 Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0
Sync_en State Comments
0 Rx: Bit
synchronization off
Transparent reception of
data
0 Tx: DataClk pin off Transparent transmission
of data
1 Rx: Bit
synchronization on
Bit-clock is generated by
transceiver
1 Tx: DATACLK pin on Bit-clock is generated by
transceiver
When Sync_en = 1, it will enable the bit
synchronizer in receive mode. The bit synchronizer
clock needs to be programmed, see chapter Bit
synchronizer. The synchronized clock will be set out
on pit DATACLK.
In transmit mode, when Sync_en = 1, the clock
signal on pin DATACLK is a programmed bit rate
clock. Now the transceiver controls the actual data
rate. The data to be transmitted will be sampled on
rising edge of DATACLK. The micro controller can
therefore use the negative edge to change the data
to be transmitted. The clock used for this purpose,
BITRATE_CLK, is programmed in the same way as
the modulator clock and the bit synchronizer clock:
)-(7
XCO
KBITRATE_CL
2Refclk_K
f
f
kSBitRate_cl
×
=
where:
f
BITRATE_CLK
: The clock frequency used to
control the bit rate, should be equal to the bit
rate (bit rate of 20 kbit/sec requires a clock
requency of 20kHz)
f
XCO
: Crystal oscillator frequency
Refclk_K: 6 bit divider, values between 1
and 63
BitRate_clkS: Bit rate setting, values
between 0 and 6
Data Interface
The MICRF506 interface can be divided in to two
separate interfaces, a “programming interface” and a
“Data interface”. The “programming interface” has a
three wire serial programmable interface and is
described in chapter Programming.
The “data interface” can be programmed to sync-
/non-synchronous mode. In synchronous mode the
MICRF506 is defined as “Master” and provides a
data clock that allows users to utilize low cost micro
controller reference frequency.
The data interface is defined in such a way that all
user actions should take place on falling edge and is
illustrated Figure 9 and 10. The two figures illustrate
the relationship between DATACLK and DATAIXO
in receive mode and transmit mode.
MICRF506 will present data on rising edge and the
“USER” sample data on falling edge in receive
mode.
DATAIXO
DATACLK
Figure 10. Data interface in Receive Mode
The User presents data on falling edge and
MICRF506 samples on rising edge in transmit mode.
DATAIXO
DATACLK
Figure 11. Data interface in Transmit Mode
When entering transmit mode it is important to keep
DATAIXO in tri-state from the time Tx-mode is
entered until user starts sending data. The data is
provided directly to the modulation circuit and
violation of this may/will cause abnormal behavior.
Depending upon the chosen FSK modulation, some
sort of encoding might be needed. The different
modulation types and encoding is described in
chapter Frequency modulation.
July 2006 19
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Micrel MICRF506BML/YML
Receiver
The receiver is a zero intermediate frequency (IF)
type in order to make channel filtering possible with
low-power integrated low-pass filters. The receiver
consists of a low noise amplifier (LNA) that drives a
quadrature mixer pair. The mixer outputs feed two
identical signal channels in phase quadrature. Each
channel include a pre-amplifier, a third order Sallen-
Key RC lowpass filter from strong adjacent channel
signals and finally a limiter. The main channel filter is
a switched-capacitor implementation of a six-pole
elliptic lowpass filte. The elliptic filter minimizes the
total capacitance required for a given selectivity and
dynamic range. The cut-off frequency of the Sallen-
Key RC filter can be programmed to four different
frequencies: 100kHz, 150kHz, 230kHz and 340kHz.
The demodulator demodulates the I and Q channel
outputs and produces a digital data output. If detects
the relative phase of the I and Q channel signal. If
the I channel signal lags the Q channel, the FSK
tone frequency lies above the LO frequency (data
‘1’). If the I channel leads the Q channel, the FSK
tone lies below the LO frequency (data ‘0’). The
output of the receiver is available on the DataIXO
pin. A RSSI circuit (receive signal strength indicator)
indicates the received signal level.
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Front End
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
A low noise amplifier in RF receivers is used to
boost the incoming signal prior to the frequency
conversion process. This is important in order to
prevent mixer noise from dominating the overall
front-end noise performance. The LNA is a two-
stage amplifier and has a nominal gain of
approximately 23dB at 434MHz. The front end has a
gain of about 35dB to 38dB. The gain varies by 1-
1.5dB over a 2.0V to 2.5V variation in power supply.
The LNA can be bypassed by setting bit LNA_by to
‘1’. This can be useful for very strong input signal
levels. The front-end gain with the LNA bypassed is
about 12dB. The mixers have a going of about 10dB
at 434MHz. The differential outputs of the mixers
can be made available at pins IchOut and QchOut.
The output impedance of each mixer is about 8kΩ.
The input impedance is close to 50Ωas shown in
Figure 12, giving an input reflection of about -20dB.
The receiver does not require any matching network
to optimize the gain. However, a matching network is
recommended for harmonic suppression in Tx and
for improved selectivity in Rx.
Figure 12. LNA Input Impedance
Sallen-Key Filters
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0
Each channel includes a pre-amplifier and a prefilter,
which is a three-pole Sallen-Key lowpass filter. It
protects the following switched-capacitor filter from
strong adjacent channel signals, and it also works as
an anti-aliasing filter. The preamplifier has a gain of
22dB. The maximum output voltage swing is about
1.4Vpp for a 2.25V power supply. In addition, the IF
amplifier also performs offset cancellation. Gain
varies by less than 0.5dB over a 2.0 – 2.5V variation
in power supply. The third order Sallen-Key lowpass
filter is programmable to four different cut-off
frequencies according to the table below:
PF_FC1 PF_FC0 Cut-off Freq. (kHz)
0 0 100
0 1 150
1 0 230
1 1 340