Microtips Technology DEPG0750RWU790F30 User manual

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This module uses ROHS material
EPD Module User Manual
MODEL: DEPG0750RWU790F30
CUSTOMER
APPROVED BY
'DWH
Specification for 7.5 inch EPD

EPD Module User Manual
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Revision History
Version
Content
Date
Producer
2.0
New release
2020/11/13
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EPD Module User Manual
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CONTENTS
1. Over View..................................................................................................................... 5
2. Features.........................................................................................................................5
3. Mechanical Specification............................................................................................. 6
4.Mechanical Drawing of EPD Module...........................................................................7
5. Input/output Pin Assignment........................................................................................8
6. Electrical Characteristics.............................................................................................. 9
6.1 Absolute Maximum Rating.................................................................................. 9
6.2 Panel DC Characteristics....................................................................................10
6.3 Panel AC Characteristics....................................................................................11
6.3.1 MCU Interface Selection...........................................................................11
6.3.2 MCU Serial Interface (4-wire SPI)...........................................................11
6.3.3 MCU Serial Interface (3-wire SPI)...........................................................12
7.Command Table.......................................................................................................... 14
8. Block Diagram............................................................................................................31
9.Typical Application Circuit with SPI Interface...........................................................32
10. Typical Operating Sequence.....................................................................................33
10.1 LUT from OTP Operation Flow.......................................................................33
10.2 OTP Operation Reference Program Code........................................................34
11. Reliability Test..........................................................................................................35
12. Inspection condition................................................................................................. 36
12.1 Environment..................................................................................................... 36
12.2 Illuminance....................................................................................................... 36
12.3 Inspect method..................................................................................................36
12.4 Display area...................................................................................................... 36
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EPD Module User Manual
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12.5 Ghosting test method........................................................................................36
12.6 Inspection standard...........................................................................................37
12.6.1 Electric inspection standard.................................................................... 37
12.6.2 Appearance inspection standard..............................................................38
13.Packaging...................................................................................................................40
14. Handling, Safety, and Environment Requirements..................................................41
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1. Over View
MT-DEPG0750RWU790F30 is an Active Matrix Electrophoretic Display (AM EPD), with
interface and a reference system design. The display is capable to display images at 1-bit white,
black and red full display capabilities. The 7.5 inch active area contains 480×800 pixels. The module
is a TFT-array driving electrophoresis display, with integrated circuits including gate driver, source
driver, MCU interface, timing controller, oscillator, DC-DC, SRAM, LUT, VCOM. Module can be
used in portable electronic devices, such as Electronic Shelf Label (ESL) System.
2. Features
◆480×800 pixels display
◆High contrast High reflectance
◆Ultra wide viewing angle Ultra low power consumption
◆Pure reflective mode
◆Bi-stable display
◆Commercial temperature range
◆Landscape portrait modes
◆Hard-coat antiglare display surface
◆Ultra Low current deep sleep mode
◆On chip display RAM
◆Waveform can stored in On-chip OTP or written by MCU
◆Serial peripheral interface available
◆On-chip oscillator
◆On-chip booster and regulator control for generating VCOM, Gate and Source driving
voltage
◆I2C signal master interface to read external temperature sensor
◆Built-in temperature sensor
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3. Mechanical Specification
Symbol
Parameter
Conditions
Min
Typ.
Max
Units
Notes
KS
Black State L* value
-
13
15
3-1
Black State A* value
-
4
6
3-1
Black Ghosting ΔE
-
2
-
3-1
After 24hour colour changed
-
2
-
3-4
WS
White State L* value
62
65
-
3-1
White State A* value
-
0
1
3-1
White Ghosting ΔE
-
2
-
3-1
After 24hour colour changed
-
2
-
3-4
RS
Red State L* value
27
28
32
3-1
Red State A* value
36
40
45
3-1
Red Ghosting ΔE
-
3
-
3-1
After 24hour colour changed
-
2
-
3-4
T update
Image update time
at 23 °C
-
17
-
sec
R
White Reflectivity
White
30
34
-
%
3-1
CR
Contrast Ratio
Indoor
15:1
20:1
-
3-1
3-2
GN
2Grey Level
-
-
-
-
Life
Temp:23±3°C
Humidity:55±
10%RH
5years
3-3
Notes: 3-1. Luminance meter: Eye-One Pro Spectrophotometer.
3-2. CR=Surface Reflectance with all white pixel/Surface Reflectance with all black pixels.
3-3. When the product is stored. The display screen should be kept white and face up.
3-4. After 24hour Colour Changed：
W: MaxΔE(W-W)<2, K: MaxΔE(B-B)<2, R: MaxΔEab(R-R)<2.
Parameter
Specifications
Unit
Remark
Screen Size
7.5
Inch
Display Resolution
800(H)×480(V)
Pixel
DPI:124
Active Area
163.2×97.92
mm
Pixel Pitch
0.204×0.204
mm
Pixel Configuration
Rectangle
Outline Dimension
170.2(H)×111.2 (V) ×1.20(D)
mm
Weight
43.9±0.5
g
24hours
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4.Mechanical Drawing of EPD Module
1/1mmSY ZHAOCC ZHENGDY FU
.XXX=± 0.20mm
.XX=± 0.20mm
.X=± 0.4mm
ANGLES± 5°
RoHS
DEPG0750_ _U790F30EPD A 20.07.10
MODIFICATIONREV.DATE
Confirmation:
1 DISPLAY MODULE 7.5" ARRAY FOR EPD
2 DRIVER IC:UC8179C
NOTE
3 RESOLUTION:480gateX800source
4 PIXEL SIZE:0.204mmX0.204mm
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5. Input/output Pin Assignment
No.
Name
I/O
Description
Remark
1
NC
Do not connect with other NC pins
Keep Open
2
GDR
O
N-Channel MOSFET Gate Drive Control
3
RESE
I
Current Sense Input for the Control Loop
4
NC
NC
Do not connect with other NC pins
Keep Open
5
VSH2
C
Positive Source driving voltage(Red)
6
TSCL
O
I2C Interface to digital temperature sensor Clock pin
7
TSDA
I/O
I2C Interface to digital temperature sensor Data pin
8
BS1
I
Bus Interface selection pin
Note 5-5
9
BUSY
O
Busy state output pin
Note 5-4
10
RES#
I
Reset signal input. Active Low.
Note 5-3
11
D/C#
I
Data /Command control pin
Note 5-2
12
CS#
I
Chip select input pin
Note 5-1
13
SCL
I
Serial Clock pin (SPI)
14
SDA
I/O
Serial Data pin (SPI)
15
VDDIO
P
Power Supply for interface logic pins It should be
connected with VCI
16
VCI
P
Power Supply for the chip
17
VSS
P
Ground
18
VDD
C
Core logic power pin VDD can be regulated internally
from VCI. A capacitor should be connected between
VDD and VSS
19
VPP
P
FOR TEST
Keep Open
20
VSH1
C
Positive Source driving voltage
21
VGH
C
Power Supply pin for Positive Gate driving voltage and
VSH1
22
VSL
C
Negative Source driving voltage
23
VGL
C
Power Supply pin for Negative Gate driving voltage
VCOM and VSL
24
VCOM
C
VCOM driving voltage
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I = Input Pin, O =Output Pin, I/O = Bi-directional Pin (Input/Output), P = Power Pin, C = Capacitor Pin
Note 5-1: This pin (CS#) is the chip select input connecting to the MCU. The chip is enabled for MCU
communication only when CS# is pulled LOW.
Note 5-2: This pin is (D/C#) Data/Command control pin connecting to the MCU in 4-wire SPI mode. When
the pin is pulled HIGH, the data at SDA will be interpreted as data. When the pin is pulled LOW,
the data at SDA will be interpreted as command.
Note 5-3: This pin (RES#) is reset signal input. The Reset is active low.
Note 5-4: This pin is Busy state output pin. When Busy is Low, the operation of chip should not be
interrupted, command should not be sent. The chip would put Busy pin Low when -Outputting
display waveform -Communicating with digital temperature sensor
Note 5-5: Bus interface selection pin
BS1 State
MCU Interface
L
4-lines serial peripheral interface(SPI) - 8 bits SPI
H
3- lines serial peripheral interface(SPI) - 9 bits SPI
6. Electrical Characteristics
6.1 Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Logic supply voltage
VCI
-0.3 to +6.0
V
Logic Input voltage
VIN
-0.3 to VCI +0.5
V
Logic Output voltage
VOUT
-0.3 to VCI +0.5
V
Operating Temp range
TOPR
0 to +40
ºC.
Storage Temp range
TSTG
-25 to+40
ºC.
Optimal Storage Temp
TSTGo
23±3
ºC.
Optimal Storage Humidity
HSTGo
55±10
%RH
Note:
1．Maximum ratings are those values beyond which damages to the device may occur. Functional
operation should be restricted to the limits in the Panel DC Characteristics tables.
2．We guarantee the single pixel display quality for 0-35℃, but we only guarantee the barcode readable
for 35-40℃.
3．The storage time is within 10 days for -25℃~ 0℃or 40℃~ 60℃.
The display screen should be kept white and face up.
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6.2 Panel DC Characteristics
The following specifications apply for: VSS=0V, VCI=3.3V, TOPR =23ºC.
Parameter
Symbol
Condition
Applicab
le pin
Min.
Typ.
Max.
Unit
Single ground
VSS
-
-
0
-
V
Logic supply voltage
VCI
-
VCI
2.3
3.3
3.6
V
Core logic voltage
VDD
VDD
2.3
3.3
3.6
V
High level input voltage
VIH
-
-
0.7 VCI
-
VCI
V
Low level input voltage
VIL
-
-
0
-
0.3 VCI
V
High level output voltage
VOH
IOH = -100uA
-
VCI -0.4
-
-
V
Low level output voltage
VOL
IOL = 100uA
-
0
-
0.4
Typical power
PTYP
VCI =3.3V
-
-
30
-
mW
Deep sleep mode
PSTPY
VCI =3.3V
-
-
0.003
-
mW
Typical operating current
Iopr_VCI
VCI =3.3V
-
-
10
-
-
mA
Image update time
-
23 ºC
-
-
17
-
sec
Typical peak current
Iopr_VCI
2.3~3.6v
100
200
mA
Sleep mode current
Islp_VCI
DC/DC off
No clock
No input load
Ram data retain
-
-
20
uA
Deep sleep mode current
Idslp_VCI
DC/DC off
No clock
No input load
Ram data not retain
-
-
1
5
uA
Notes: 1. The typical power is measured with following transition from horizontal 2 scale pattern to vertical
3 scale pattern.
2. The deep sleep power is the consumed power when the panel controller is in deep sleep mode.
3. The listed electrical/optical characteristics are only guaranteed under the controller & waveform
provided by MT.
4. Electrical measurement：Tektronix oscilloscope - MDO3024，
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Tektronix current probe–TCP0030A.
6.3 Panel AC Characteristics
6.3.1 MCU Interface Selection
Provides 3-wire/4-wire serial interface for command and display data transferred from the MCU. The
serial interface supports 8-bit mode. Data can be input/output by clocks while the chip is active (CSB
=LOW). While input, data are written in order from MSB at the clock rising edge. When too many
parameters are input, the chip accepts only defined parameters, and ignores undefined ones.
6.3.2 MCU Serial Interface (4-wire SPI)
Data / Command is recognized with DC pin. Data are transferred in the unit of 8 bits. To prevent
malfunction due to noise, it is recommended to set the CSB signal to HIGH every 8 bits. (The serial
counter is reset at the rising edge of the CSB signal.)
The MSB bit of data will be output at SDA pin after the CSB falling edge, if DC pin is High.
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6.3.3 MCU Serial Interface (3-wire SPI)
Data / Command is recognized with the first bit transferred. Data are transferred in the unit of 9 bits.
To prevent malfunction due to noise, it is recommended to set the CSB signal to HIGH every 9 bits.
(The serial counter is reset at the rising edge of the CSB signal.)
The MSB bit of data will be output at SDA pin after the 1 st SCL falling edge, if the 1 st input data at
SDA is high.
6.3.4 Interface Timing
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Serial Interface Timing Characteristics
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7.Command Table
W/R: 0: Write Cycle / 1: Read Cycle C/D: 0: Command / 1: Data D7-D0: –: Don’t Care
1) PANEL SETTING (PSR) (REGISTER: R00H)
REG: LUT selection
0: LUT from OTP. (Default)
1: LUT from register.
KW/R: Black / White / Red
0: Pixel with Black/White/Red, KWR mode. (Default)
1: Pixel with Black/White, KW mode.
UD: Gate Scan Direction
0: Scan down. First line to Last line: Gn-1 Gn-2 Gn-3 … G0
1: Scan up. (Default) First line to Last line: G0 G1 G2 … … . Gn-1
SHL: Source Shift Direction
0: Shift left. First data to Last data: Sn-1 Sn-2 Sn-3 … S0
1: Shift right. (Default) First data to Last data: S0 S1 S2 … … . Sn-1
SHD_N: Booster Switch
0: Booster OFF
1: Booster ON (Default)
When SHD_N becomes LOW, charge pump will be turned OFF, register and SRAM
data will keep until VDD OFF.And Source/Gate/Border/VCOM will be released to
floating.
RST_N: Soft Reset
0: Reset. Booster OFF, Register data are set to their default values, all drivers will be
reset, and all functions will be disabled. Source/Gate/Border/VCOM will be released to
floating.
1: No effect (Default).
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2) POWER SETTING (PWR) (R01H)
BD_EN: Border LDO enable
0 : Border LDO disable (Default)
Border level selection: 00b: VCOM 01b: VDH 10b: VDL 11b: VDHR
1 : Border LDO enable
Border level selection: 00b: VCOM 01b: VBH(VCOM-VDL) 10b:VBL(VCOM-VDH)
11b: VDHR
VSR_EN: Source LV power selection
0 : External source power from VDHR pins
1 : Internal DC/DC function for generating VDHR. (Default)
VS_EN: Source power selection
0 : External source power from VDH/VDL pins
1 : Internal DC/DC function for generating VDH/VDL. (Default)
VG_EN: Gate power selection
0 : External gate power from VGH/VGL pins
1 : Internal DC/DC function for generating VGH/VGL. (Default)
VCOM_SLEW: VCOM slew rate selection for voltage transition. The value is fixed at “1”.
VG_LVL[2:0]: VGH / VGL Voltage Level selection.
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3) POWER OFF (POF) (R02H)
After the Power OFF command, the driver will be powered OFF. Refer to the POWER
MANAGEMENT section for the sequence.
This command will turn off booster, controller, source driver, gate driver, VCOM, and temperature
sensor, but register data will be kept until VDD turned OFF or Deep Sleep Mode.
Source/Gate/Border/VCOM will be released to floating.
4) POWER OFF SEQUENCE SETTING (PFS) (R03 H)
T_VDS_OFF[1:0]: Source to gate power off interval time.
00b: 1 frame (Default) 01b: 2 frames 10b: 3 frames 11b: 4 frame
5) POWER ON (PON) (REGISTER: R04H)
After the Power ON command, the driver will be powered ON. Refer to the POWER
MANAGEMENT section for the sequence.
This command will turn on booster, controller, regulators, and temperature sensor will be activated
for one-time sensing before enabling booster. When all voltages are ready, the BUSY_N signal will
return to high.
6) BOOSTER SOFT START (BTST) (R06H)
BT_PHA[7:6]: Soft start period of phase A.
00b: 10mS 01b: 20mS 10b: 30mS 11b: 40mS
BT_PHA[5:3]: Driving strength of phase A
000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4
100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest)
BT_PHA[2:0]: Minimum OFF time setting of GDR in phase A
000b: 0.27uS 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS
100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b: 6.58uS
BT_PHB[7:6]: Soft start period of phase B.
00b: 10mS 01b: 20mS 10b: 30mS 11b: 40mS
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BT_PHB[5:3]: Driving strength of phase B
000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4
100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest)
BT_PHB[2:0]: Minimum OFF time setting of GDR in phase B
000b: 0.27uS 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS
100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b: 6.58uS
BT_PHC1[5:3]: Driving strength of phase C1
000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4
100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest)
BT_PHC1[2:0]: Minimum OFF time setting of GDR in phase C1
000b: 0.27uS 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS
100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b: 6.58uS
PHC2EN: Booster phase-C2 enable
0: Booster phase-C2 disable
Phase-C1 setting always is applied for booster phase-C.
1: Booster phase-C2 enable
If temperature > temperature boundary phase-C2(RE7h[7:0]), phase-C1 setting is
applied for booster phase-C.
If temperature <= temperature boundary phase-C2(RE7h[7:0]), phase-C2 setting is
applied for booster phase-C.
BT_PHC2[5:3]: Driving strength of phase C2
000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4
100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest)
BT_PHC2[2:0]: Minimum OFF time setting of GDR in phase C2
000b: 0.27uS 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS
100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b:6.58uS
7) DEEP SLEEP (DSLP) (R07H)
After this command is transmitted, the chip will enter Deep Sleep Mode to save power. Deep Sleep
Mode will return to Standby Mode by hardware reset. The only one parameter is a check code, the
command will be executed if check code = 0xA5.
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8) DATA START TRANSMISSION 1 (DTM1) (R10H)
This command starts transmitting data and write them into SRAM.
In KW mode, this command writes “OLD”data to SRAM.
In KWR mode, this command writes “K/W”data to SRAM.
In Program mode, this command writes “OTP”data to SRAM for programming.
9) DISPLAY REFRESH (DRF) (R12H)
While user sent this command, driver will refresh display (data/VCOM) according to SRAM data
and LUT.
After Display Refresh command, BUSY_N signal will become “0”and the refreshing of panel
starts.
10) DATA START TRANSMISSION 2 (DTM2) (R13 H)
This command starts transmitting data and write them into SRAM.
In KW mode, this command writes “NEW”data to SRAM.
In KWR mode, this command writes “RED”data to SRAM.
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11) VCOM LUT (LUTC) (R20H)
This command stores VCOM Look-Up Table with 10 groups of data. Each group contains
information for one state and is stored with 6 bytes (byte 2~7, 8~13, 14~19, 20~25, …), while the
sixth byte indicates how many times that phase will repeat.
Bytes 2, 8, 14, 20, 26, 32, 38, 44, 50, 56:
D[7:6], D[5:4], D[3:2], D[1:0]: Level Selection
00b: VCOM_DC
01b: VDH+VCOM_DC (VCOMH)
10b: VDL+VCOM_DC (VCOML)
11b: Floating
Bytes 3~6, 9~12, 15~18, 21~24, 27~30, 33~36, 39~42, 45~48, 51~54, 57~60:
Number of Frames
0000 0000b: 0 frame
: :
: :
1111 1111b: 255 frames
Bytes 7, 13, 19, 25, 31, 37, 43, 49, 55, 61:
Times to Repeat
0000 0000b: 0 time
: :
: :
1111 1111b: 255 times
If KW/R=0 (KWR mode), all 10 groups are used.
If KW/R=1 (KW mode), only 7 groups are used.
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