Motor Generator Division MC68EZ328 User manual



Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin TX 78735-8598
MC68EZ328
Integrated Processor
UserÕs Manual
Order this document by
MC68EZ328UM/D
(Motorola Order Number)
Rev. 1, 11/98

©MOTOROLA INC., 1998. All rights reserved.
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, function, or design. Motorola does not assume any liability arising out of the application or use
of any product or circuit described herein; neither does it convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer
OnCE and Mfax are trademarks of Motorola, Inc.

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TABLE OF CONTENTS
Paragraph Page
Number Title Number
PREFACE
Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Organization of This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
SECTION 1
BASIC ARCHITECTURE
1.1 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.2 Data and Address Mode Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.3 EC000 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2 Chip-Select Logic and Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3 Phase-Locked Loop and Power Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.5 Parallel General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6 Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.7 General-Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.8 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.9 UART and Infra-Red Communication Support . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.10 LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.11 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.12 DRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.13 In-Circuit Emulation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.14 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.15 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
SECTION 2
SIGNAL DESCRIPTIONS
2.1 Signals GROUped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 POWER and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 CLOCK and System Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 ADDRESS BUS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 DATA BUS Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.6 BUS CONTROL Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.7 INTERRUPT CONTROLler Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.8 LCD CONTROLLER Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

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2.9 UART Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.10 TIMER Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.11 Pulse-Width Modulator Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.12 Serial Peripheral Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.13 CHIP-SELECT Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.14 In-Circuit EMULATion Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
SECTION 3
SYSTEM CONTROL
3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
SECTION 4
CHIP-SELECT LOGIC
4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.1 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.2 Programmable Data Bus Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.3 Overlapping Chip-Select Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.1 Chip-Select Group Base Address Registers. . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.2 Chip-Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.3 Emulation Chip-Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.3 Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
SECTION 5
PHASE-LOCKED LOOP AND POWER CONTROL
5.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Using the PLL To Reduce Power Consumption . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 PLL Operation at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.3 PLL Operation at Wake-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.4 Changing the VCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.5 PLL Operation at System Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.1 PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.2 PLL Frequency Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3 POWER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.1 Operating the Power Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.2 Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
SECTION 6
INTERRUPT CONTROLLER

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6.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Exception Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3.1 DATA BUS WIDTH FOR BOOT DEVICE OPERATION . . . . . . . . . . . . . 6-5
6.4 INTERRUPT CONTROLLER operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.5 Vector Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.6.1 Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.6.2 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.6.3 Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.6.4 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.5 Interrupt Pending Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.7 KEYBOARD INTERRUPTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.8 PEN Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
SECTION 7
PARALLEL PORTS
7.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.1 Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.2 Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2.3 Port C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.4 Port D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.5 Port E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.2.6 Port F Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.2.7 Port G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
SECTION 8
PULSE-WIDTH MODULATOR
8.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.3 D/A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.1 PWM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.2 PWM Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2.3 PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2.4 PWM Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.3 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
SECTION 9
GENERAL-PURPOSE TIMER
9.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

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9.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.1 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 Timer Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.2.3 Timer Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.2.4 Timer Capture Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.2.5 Timer Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.2.6 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
SECTION 10
SERIAL PERIPHERAL INTERFACE MASTER
10.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Phase/Polarity Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1 SPIM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.2 SPIM Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.3 Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
SECTION 11
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER
11.1 SERIAL OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.1 NRZ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.2 IrDA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.3 SERIAL INTERFACE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2 SUB-BLOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.2.3 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.1 UART Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.2 UART Baud Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.3.3 UART Receiver Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.3.4 UART Transmitter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.3.5 UART Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.3.6 UART Non-Integer Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.4 Non-Integer Prescaler Programming Example. . . . . . . . . . . . . . . . . . . . . 11-19
SECTION 12
LCD CONTROLLER
12.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.1.1 Connecting the LCD Controller to an LCD Panel . . . . . . . . . . . . . . . . . 12-3
12.1.2 Controlling the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.1.3 Using Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

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12.1.4 Using the DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.2.1 LCD Screen Starting Address Register. . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.2.2 LCD Virtual Page Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.2.3 LCD Screen Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.2.4 LCD Screen Height Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.2.5 LCD Cursor X Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.2.6 LCD Cursor Y Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.2.7 LCD Cursor Width and Height Register . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.2.8 LCD Blink Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.2.9 LCD Panel Interface Configuration Register . . . . . . . . . . . . . . . . . . . . 12-13
12.2.10 LCD Polarity Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.2.11 LACD Rate Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.2.12 LCD Pixel Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.2.13 LCD Clocking Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.2.14 LCD Refresh Rate Adjustment Register . . . . . . . . . . . . . . . . . . . . . . . 12-16
12.2.15 LCD Panning Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.2.16 LCD Frame Rate Control Modulation Register . . . . . . . . . . . . . . . . . . 12-17
12.2.17 LCD Gray Palette Mapping Register. . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.2.18 PWM Contrast Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.3 Programming EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
SECTION 13
REAL-TIME CLOCK
13.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.1 Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.2 Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.4 Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.5 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2.1 RTC Hours, Minutes, and Seconds Register . . . . . . . . . . . . . . . . . . . . 13-4
13.2.2 RTC Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.2.3 Watchdog Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.2.4 RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.2.5 RTC Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.2.6 RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.2.7 Stopwatch Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.2.8 RTC Day Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.2.9 RTC Day Alarm Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
SECTION 14
DRAM CONTROLLER
14.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

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14.1.1 Address Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.2 DTACK Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.1.3 Refresh Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.1.4 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.1.5 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.1.6 Low-Power Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.1.7 Data Retention During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.1 DRAM Memory Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.2 DRAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
SECTION 15
IN-CIRCUIT EMULATION
15.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.1 Entering Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.2 Detecting Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.3 Using the Signal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.4 Using the Interrupt Gate Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.5 Using the A-Line Insertion Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2.1 In-Circuit Emulation Module Address Compare/Mask Registers . . . . . 15-4
15.2.2 In-Circuit Emulation Module Control Compare/Mask Register . . . . . . . 15-5
15.2.3 In-Circuit Emulation Module Control Register. . . . . . . . . . . . . . . . . . . . 15-6
15.2.4 In-Circuit Emulation Module Status Register . . . . . . . . . . . . . . . . . . . . 15-8
15.3 Typical Design Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.3.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.3.2 Dedicated Debug Monitor Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.3.3 Emulation Memory Mapping FPGA and Emulation Memory . . . . . . . 15-10
15.3.4 Optional Extra Hardware Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.3.5 Optional Trace Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.4 Plug-In Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.5 Application Development Design Example . . . . . . . . . . . . . . . . . . . . . . . 15-12
SECTION 16
BOOTSTRAP MODE
16.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.1 Entering Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.2 Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.1.3 Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.1.4 Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.2 System Initialization Programming Example . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3 Application Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.4 Instruction Buffer Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.5 Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

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16.6 Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
SECTION 17
APPLICATION GUIDE
17.1 Design Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2 Using the MC68EZ328ADS Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
SECTION 18
ELECTRICAL CHARACTERISTICS
18.1 MAXIMUM RATINGs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2 DC ELECTRICAL CharacteristicS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.3 AC ELECTRICAL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.3.1 CLKO reference to Chip-Select Signals Timing . . . . . . . . . . . . . . . . . . 18-2
18.3.2 Chip-Select Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3.3 Chip-Select Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.4 Chip-Select Flash Write Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.5 DRAM Read Cycle 16-Bit Access (CPU Bus Master). . . . . . . . . . . . . . 18-6
18.3.6 DRAM Write Cycle 16-Bit Access (CPU Bus Master) . . . . . . . . . . . . . . 18-7
18.3.7 DRAM Hidden Refresh Cycle (Normal Mode). . . . . . . . . . . . . . . . . . . . 18-8
18.3.8 DRAM Hidden Refresh Cycle (Low Power Mode) . . . . . . . . . . . . . . . . 18-9
18.3.9 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access(1 ws) ( . . . . . . . . 18-10
18.3.10 LCD DRAM DMA Cycle 16-Bit EDO Mode Access (LCD Bus Master)18-11
18.3.11 LCD DRAM DMA Cycle 16-Bit Page Mode Access (LCD Bus Master)18-12
18.3.12 LCD Controller Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
18.3.13 Normal Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.3.14 Normal Mode and Emulation Mode Timing. . . . . . . . . . . . . . . . . . . . . 18-14
18.3.15 Emulation Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.3.16 Bootstrap Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
SECTION 19
MECHANICAL DATA AND ORDERING INFORMATION
19.1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 TQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3 TQFP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.4 PBGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.5 PBGA Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

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LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 MC68EZ328 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Supervisor Programming Model Supplement . . . . . . . . . . . . . . . . . . . . . 1-3
1-4 MC68EZ328 System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
2-1 Signals Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2-2 Typical Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
4-1 Chip-Selects and Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 Size Selection and Memory Protection for CSB0 and CSB1 . . . . . . . . . 4-3
5-1 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 Power Control Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5-3 Power Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
6-1 Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
7-1 Parallel Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7-2 Interrupt Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
8-1 Pulse-Width Modulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8-2 Audio Waveform Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
9-1 General-Purpose Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
10-1 Serial Peripheral Interface Master Block Diagram . . . . . . . . . . . . . . . . 10-1
10-2 Serial Peripheral Interface Master Operation . . . . . . . . . . . . . . . . . . . . 10-2
11-1 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11-2 NRZ ASCII ÒAÓ Character with Odd Parity . . . . . . . . . . . . . . . . . . . . . . 11-2
11-3 IrDA ASCII ÒAÓ Character with Odd Parity. . . . . . . . . . . . . . . . . . . . . . . 11-3
11-4 Baud Rate Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
12-1 LCD Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12-2 LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths. . . . . . . . . . . . . 12-4
12-3 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12-4 Mapping Memory Data on the Screen . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
13-1 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
14-1 DRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14-2 DRAM Address Multiplexer Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

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14-3 LCD Controller and DRAM Controller Interface . . . . . . . . . . . . . . . . . . 14-4
14-4 Data Retention for the Reset Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
15-1 In-Circuit Emulation Module Block Diagram . . . . . . . . . . . . . . . . . . . . . 15-1
15-2 Typical Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15-3 Plug-in Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15-4 Application Development System Design Example . . . . . . . . . . . . . . 15-12
16-1 Bootstrap Mode Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16-2 Bootloader Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
19-1 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

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LIST OF TABLES
Table Page
Number Title Number
1-1 Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1-2 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1-3 ProgrammerÕs Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
2-1 Signal Function Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
6-1 Exception Vector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6-2 Interrupt Vector Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
11-1 Non-Integer Prescaler Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11-2 Non-Integer Prescaler Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11-3 Selected Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
12-1 Gray-Scale Palette Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
13-1 Sampling Timer Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

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PREFACE
The MC68EZ328 (DragonBallEZ) microprocessor, which is the second generation of the
DragonBall
ª
, is designed to save you time, power, cost, board space, pin count, and
programming steps when designing your product. This functionality on a different
microprocessor could require 20 separate components, each with 16-64 separate pins.
These components take up valuable space on your board and they also consume more
power. In addition, the signals between the CPU and a peripheral could be incompatible and
may not run from the same clock, which could require time delays or other special design
constraints.
All this combined makes the MC68EZ328 the microprocessor of choice among many
system designers. Its functionality and glue logic are all optimally connected, timed with the
same clock, fully tested, and uniformly documented. Also, only the essential signals are
brought out to the pins. The MC68EZ328Õs primary package consists of a surface-mount
plastic TQFP designed to leave the smallest possible footprint on your board.
RELATED DOCUMENTATION
This manual will discuss the details of how to initialize, configure, and program the
MC68EZ328 microprocessor. However, it assumes you have a basic knowledge of 68K
architecture. If you are not familiar with 68K, you should get a copy of the following
documents to use in conjunction with this manual.
¥
M68000 UserÕs Manual
(part number M68000UM/AD).
¥
M68EZ328ADS UserÕs Manual
, which is only available from our website.
¥
M68000 ProgrammerÕs Reference Manual
(part number M68000PM/AD).
You can go to the Motorola website at www.mot.com/dragonball and download these
documents or you can contact your local sales office and request a printed version. The
website also has application notes that may be useful to you.
ORGANIZATION OF THIS MANUAL
This manual is organized according to the MC68EZ328 memory map, which is discussed in
Section 1.15 Memory Map.

Preface
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SECTION 1
BASIC ARCHITECTURE
To improve total system throughput and reduce component count, board size, and cost of
system implementation, the MC68EZ328 combines a powerful MC68EC000 processor with
intelligent peripheral modules and a typical system interface logic. The architecture of the
MC68EZ328 consists of the following blocks:
¥ EC000 core
¥ Chip-select logic and bus interface
¥ Phase-locked loop and power control
¥ Interrupt controller
¥ Parallel general-purpose I/O ports
¥ Pulse-width modulator
¥ General-purpose timer
¥ Serial peripheral interface
¥ UART and infra-red communication support
¥ LCD controller
¥ Real-time clock
¥ DRAM controller
¥ In-circuit emulation module
¥ Bootstrap mode
This manual assumes you are familiar with 68K architecture. If you are not, get a copy of the
M68000 UserÕs Manual
(part number M68000UM/AD) and
M68000 ProgrammerÕs
Reference Manual
(part number M68000PM/AD) from your local Motorola sales office.

Basic Architecture
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1.1 CORE
The MC68EC000 core in the MC68EZ328 is an updated implementation of the M68000
32-bit microprocessor architecture. The main features of the core are:
¥ Low power, static HCMOS implementation
¥ 32-bit address bus and 16-bit data bus
¥ Sixteen 32-bit data and address registers
¥ 56 powerful instruction types that support high-level development languages
¥ 14 addressing modes and five main data types
¥ Seven priority levels for interrupt control
The core is completely code-compatible with other members of the M68000 families, which
means it has access to a broad base of established real-time kernels, operating systems,
languages, applications, and development tools.
1.1.1 Core Programming Model
The core has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2.
The first eight registers (D7ÐD0) are data registers that are used for byte (8-bit), word
(16-bit), and long-word (32-bit) operations. When using the data registers to manipulate
data, they affect the status register (SR). The next seven registers (A6ÐA0) and the user
Figure 1-1. MC68EZ328 Block Diagram
16-BIT
TIMER
MODULE
68EC000 HCMOS
STATIC
CORE
UART
WITH
INFRA-RED
SUPPORT
SPI
LCD
CONTROLLER
SYSTEM INTEGRATION MODULE
INTERRUPT
CONTROLLER
EMULATION
PHASE-LOCKED
LOOP AND
68EC000 INTERNAL BUS
8-/16-BIT
68000 BUS
INTERFACE
ENHANCED
PWM
DRAM
CONTROLLER
REAL-TIME
PARALLEL I/O PORTS
PARALLEL I/O PORTS
BOOTSTRAP
MODE
CLOCK
IN-CIRCUIT
POWER CONTROL
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