Motorola MVME3100 Manual

MVME3100
Single-Board Computer
Programmer’s Guide
V3100A/PG1
March 2006 Edition

© Copyright 2006 Motorola Inc.
All rights reserved.
Printed in the United States of America.
Motorola and the stylized M logo are trademarks of Motorola, Inc., registered in the U.S.
Patent and Trademark Office.
All other product or service names mentioned in this document are the property of their
respective owners.

Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of
this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as
the user of the product, should follow these warnings and all other safety precautions necessary for the safe
operation of the equipment in your operating environment.
Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.
Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or
damage.
Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement
or any internal adjustment. Service personnel should not replace components with power cable connected. Under
certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such
personnel should always disconnect power and discharge circuits before touching components.
Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To
prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling
of a CRT should be done only by qualified service personnel using approved safety mask and gloves.
Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.
Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety precautions
which you deem necessary for the operation of the equipment in your operating environment.
Warning
Wa rn in g To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its
components.

Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.
EMI Caution
!
Caution
Caution This equipment generates, uses and can radiate electromagnetic energy. It
may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.
Lithium Battery Caution
This product contains a lithium battery to power the clock and calendar circuitry.
!
Caution
Caution Danger of explosion if battery is replaced incorrectly. Replace battery only
with the same or equivalent type recommended by the equipment
manufacturer. Dispose of used batteries according to the manufacturer’s
instructions.
Attention
!
Caution Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type
équivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabricant.
Vorsicht
!
Caution Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur
durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung
gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)
!
Warning
Wa rn in g This is a Class A product. In a domestic environment, this product may
cause radio interference, in which case the user may be required to take
adequate measures.
Motorola products with the CE marking comply with the EMC Directive (89/336/EEC).
Compliance with this directive implies conformity to the following European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics
of Information Technology Equipment”; this product tested to Equipment Class A
EN55024 “Information technology equipment—Immunity characteristics—Limits and
methods of measurement”
Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain the
required EMC performance.
In accordance with European Community directives, a “Declaration of Conformity” has
been made and is available on request. Please contact your sales representative.

Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or from
the use of the information obtained therein. Motorola reserves the right to revise this
document and to make changes from time to time in the content hereof without obligation
of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Web site. The text itself may not
be published commercially in print or electronic form, edited, translated, or otherwise
altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola
products (machines and programs), programming, or services that are not available in your
country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.
Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clause
at DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Embedded Communications Computing
2900 South Diablo Way
Tempe, Arizona 85282

MVME3100 Programmer’s Guide (V3100A/PG1) vii
About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Overview of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Comments and Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Conventions Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiv
1 Board Description and Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Default Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MOTLoad’s Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VME Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
System Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PCI Bus Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PLD Data Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
External Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Prescalar Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Geographical Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2 Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
MPC8540 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MPC8540 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Local Bus Controller Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
User Configuration EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
VPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
RTM VPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contents

MVME3100 Programmer’s Guide (V3100A/PG1)
Contents
viii
Ethernet PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PCI IDSEL Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MPC8540 Real-Time Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
MPC8540 LBC Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Motorola Computer Group Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

MVME3100 Programmer’s Guide (V3100A/PG1) ix
Figure 1-1. MVME3100 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Figures

MVME3100 Programmer’s Guide (V3100A/PG1) xi
Table 1-1. MVME3100 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1-2. MVME712-101 RTM Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1-3. Default Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1-4. MOTLoad’s Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1-5. System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1-6. System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 1-7. System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 1-8. System Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 1-9. Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 1-10. PCI Bus A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 1-11. PCI Bus B Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 1-12. PCI Bus C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 1-13. Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-14. Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 1-15. PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 1-16. PLD Data Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 1-17. Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-18. Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-19. Prescalar Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-20. Tick Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-21. Tick Timer Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-22. Tick Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2-1. MPC8540 Power-on Reset Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2-2. MPC8540 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 2-3. LBC Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2-4. I2C Bus Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2-5. PHY Types and MII Management Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 2-6. Flash Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 2-7. IDSEL and Interrupt Mapping for PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 2-8. Planar PCI Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2-9. PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 2-10. Clock Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table A-1. Motorola Computer Group Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table A-2. Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table A-3. Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
List of Tables

MVME3100 Programmer’s Guide (V3100A/PG1) xiii
About This Manual
The MVME3100 Single-Board Computer Programmer’s Reference Guide provides general
programming information, including memory maps, interrupts, and register data for the
MVME3100 family of boards. This document should be used by anyone who wants general, as
well as technical information about the MVME3100 products.
As of the printing date of this manual, the MVME3100 supports the models listed below.
Overview of Contents
This manual is divided into the following chapters and appendices:
Chapter 1, Board Description and Memory Maps, provides a brief product description and a
block diagram. The remainder of the chapter providesinformation onmemory maps and system
and configuration registers.
Chapter 2,ProgrammingDetails, provides additional programming information including IDSEL
mapping, interrupt assignments for the MPC8540 interrupt controller, Flash memory, two-wire
serial interface addressing, and other device and system considerations.
Appendix A, Related Documentation, provides a listing of related Motorola manuals, vendor
documentation, and industry specifications.
Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentation. We want to know
what you think about our manuals and how we can make them better. Mail comments to:
Motorola, Inc.
Embedded Communications Computing
Reader Comments DW278
2900 S. Diablo Way
Tempe, Arizona 85282
Model Number Description
MVME3100-1152 677 MHz MPC8540 PowerQUICC III™ integrated processor, 256MB DDR
SDRAM, 64MB flash, Gigabit Ethernet, SATA, IEEE handles
MVME3100-1263 833 MHz MPC8540 PowerQUICC III integrated processor, 512MB DDR
SDRAM, 128MB flash, Gigabit Ethernet, SATA, USB, PCI expansion
connector, IEEE handles
MVME721-101 Rear Transition Module, direct connect, 75mm, PIM socket for PMC-1 I/O,
four serial, 10/100/1000 Enet, 10/100 Enet

MVME3100 Programmer’s Guide (V3100A/PG1)
About This Manual
xiv
You can also submit comments to the following e-mail address:
[e-mail]
In all your correspondence, please list your name, position, and company. Be sure to include
the title and part number of the manual and tell how you used it. Then tell us your feelings about
its strengths and weaknesses and any recommendations for improvements.
Conventions Used in This Manual
The following typographical conventions are used in this document:
bold
is used for user input that you type just as it appears; it is also used for commands, options
and arguments to commands, and names of programs, directories and files.
italic
is used for names of variables to which you assign values, for function parameters, and for
structure names and fields. Italic is also used for comments in screen displays and
examples, and to introduce new terms.
courier
is used for system output (for example, screen displays, reports), examples, and system
prompts.
<Enter>, <Return> or <CR>
represents the carriage return or Enter key.
Ctrl
represents the Control key. Execute control characters by pressing the Ctrl key and the
letter simultaneously, for example, Ctrl-d.

1
MVME3100 Programmer’s Guide (V3100A/PG1) 1
1Board Description and Memory Maps
Introduction
This chapter briefly describes the board level hardware features of the MVME3100 single-board
computer, including a table of features and a block diagram. The remainder of the chapter provides
memory map information including a default memory map, MOTLoad’s processor memory map, a
default PCI memory map, MOTLoad’s PCI memory map, system I/O memory map, and other
configuration registers.
Overview
The MVME3100 is a single-slot, single-board computer based on the MPC8540 PowerQUICC III™
integrated processor. The MVME3100 provides serial ATA (sATA), USB 2.0, 2eSST VMEbus interfaces,
dual 64-bit/100 MHz PMC sites, up to 256MB of Flash, dual 10/100/1000 Ethernet, one 10/100
Ethernet, and five serial ports. This board supports front and rear I/O and a single SODIMM module for
DDR memory. Access to rear I/O is available with a rear transition module (RTM).
Figure 1-1 shows a block diagram of the MVME3100 and Table 1-1 lists the features of the MVME3100.

MVME3100 Programmer’s Guide (V3100A/PG1)
Chapter 1 Board Description and Memory Maps
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Figure 1-1. MVME3100 Block Diagram
4377 0106
PMC 1 Front IO
U
S
Bs ATA
P2 P0 P1
GigE
RJ45
PHY
5461
COM1
RJ45
XCVR
RS232
DUART DDR MC
TSEC1
TSEC2
FEC LBC
I2C
PCIX
MPC8540
Processor
833 MHz
Serial Port 0
GigE 1
GigE 2
10/100
PHY
5461
PHY
5221
SODIMM - Up to
1GB DDR Memory
User
128KB
RTC
DS1375
VPD
8KB
VME
TSI148
XCVR
22501
XCVR
RS232
CPLD
Decode
Timers/Regs
RTC
DS1621
Quart
16C554
s ATA
GD31244
USB
uPD720101
Flash
128MB
Clock
Distribution
Reset
Control
Power
Supplies
P2P
PCI6520
P2P
PCI6520
PMCSpan
Planar
Connector
Bus A
PCI-X 66MHz
PMC 1 PMC 2
s ATA 1
VME Bus
I2C Bus USB 2PMC 1 Jn4 IOCOM2 - COM510/100 s ATA 2
USB 2USB 1
GigE 2
Bus C
PCI 33 MHz
Bus B
PCI-X 66/100 MHz
PCI 33/66 MHz
Serial Ports 1-4
sATA 0
Device
Bus
166 MHz Memory Bus
RST/ABORT
PMC 2 Front IO
I2C Bus
Front Panel
Future Option
De-pop in -1152

Chapter 1 Board Description and Memory Maps
MVME3100 Programmer’s Guide (V3100A/PG1) 3
Table 1-1. MVME3100 Features Summary
Feature Description
Processor/Host
Controller/Memory
Controller
– Single 667/833 MHz MPC8540 PowerQUICC III™ integrated
processor (e500 core)
– Integrated 256KB L2 cache/SRAM
– Integrated four-channel DMA controller
– Integrated PCI/PCI-X controller
– Two integrated 10/100/1000 Ethernet controllers
– Integrated 10/100 Ethernet controller
– Integrated dual UART
– Integrated I2C controller
– Integrated programmable interrupt controller
– Integrated local bus controller
– Integrated DDR SDRAM controller
System Memory – One SODIMM socket
– Up to DDR333, ECC
– 256MB or 512MB SODIMM
I2C Interface – One 8KB VPD serial EEPROM
– Two 64KB user configuration serial EEPROMs
– One real-time clock (RTC) with removable battery
– One temperature sensor
– Interface to SPD(s) on SODIMM and P2 for RTM VPD
Flash – 32MB to 256MB soldered Flash with two alternate 1MB boot
sectors selectable via a hardware switch
– Hardware switch or software bit write protection for entire logical
bank
PCI Interface Bus A:
– 66 MHz PCI-X (PCI-X 1.0b compliant)
– One TSi148 VMEbus controller
– One serial ATA (sATA) controller
– Two PCI6520 PCI-X-to-PCI-X bridges (primary side)
Bus B:
– 33/66/100 MHz PCI/PCI-X (PCI 2.2 and PCI-X 1.0b compliant)
– Two +3.3V/5V selectable VIO, 64-bit, single-wide PMC sites or
one double-wide PMC site (PrPMC ANSI/VITA 32-2003 and PCI-X
Auxiliary ANSI/VITA 39-2003 compliant)
– One PCI6520 PCI-X-to-PCI-X bridge (secondary side)
Bus C (-1263 version):
– 33 MHz PCI (PCI 2.2 compliant)
– One USB 2.0 controller
– One PCI expansion connector for interface to PMCspan
– One PCI6520 PCI-X-to-PCI-X bridge (secondary side)
I/O – One front panel RJ45 connector with integrated LEDs for front I/O:
one serial channel
– One front panel RJ45 connector with integrated LEDs for front I/O:
one 10/100/1000 Ethernet channel
– One front panel external sATA data connector for front I/O: one
sATA channel
– One front panel USB Type A upright receptacle for front I/O: one
USB 2.0 channel (-1263 version)
– PMC site 1 front I/O and rear P2 I/O
– PMC site 2 front I/O

MVME3100 Programmer’s Guide (V3100A/PG1)
Chapter 1 Board Description and Memory Maps
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Serial ATA – Onefour-channel sATA controller: one channelfor front-panelI/O,
one channel for planar I/O, one channel for future rear P0 I/O, and
one channel is not used
– One planar data connector and one planar power connector for
an interface to the sATA hard disk drive
USB (-1263 version) – One four-channel USB 2.0 controller: one channel for front panel
I/O and one channel for future rear P0 I/O. The other two channels
are not used.
Ethernet – Two 10/100/1000 MPC8540 Ethernet channelsfor front-panel I/O
and rear P2 I/O
– One 10/100 MPC8540 Ethernet channel for rear P2 I/O
Serial Interface – One 16550-compatible, 9.6 to 115.2 KBAUD, MPC8540,
asynchronous serial channel for front-panel I/O
– One quad UART controller to provide four 16550-compatible, 9.6
to 115.2 KBAUD, asynchronous serial channels for rear P2 I/O
Timers – Four 32-bit MPC8540 timers
– Four 32-bit timers in a PLD
Watchdog Timer – One MPC8540 watchdog timer
VME Interface – VME64 (ANSI/VITA 1-1994) compliant
– VME64 Extensions (ANSI/VITA 1.1-1997) compliant
– 2eSST (ANSI/VITA 1.5-2003) compliant
– VITA 41.0, version 0.9 compliant
– Two five-row P1 and P2 backplane connectors
– One TSi148 VMEbus controller
Form Factor – Standard 6U VME
Miscellaneous – One front-panel reset/abort switch
– Four front-panel status indicators: 10/100/1000 Ethernet
link/speed and activity, board fail, and user software controlled LED
– Six planar status indicators: one power supply status LED, two
user software controlled LEDs, three sATA activity LEDs (one per
channel)
– One standard 16-pin JTAG/COP header
– Boundary scan support
– Switches for VME geographical addressing in a three-row
backplane
Software Support – VxWorks operating system
– Linux operating system
Table 1-1. MVME3100 Features Summary (continued)
Feature Description

Chapter 1 Board Description and Memory Maps
MVME3100 Programmer’s Guide (V3100A/PG1) 5
Memory Maps
Default Processor Memory Map
The MPC8540 presents a default processor memory map following RESET negation. The following
table shows the default memory map from the point of view of the processor. The e500 core only
provides one default TLB entry to access boot code and it allows for accesses within the highest 4KB
of memory. To access the full 8MB of default boot space (and the 1MB of CCSR space), additional TLB
entriesmust beset upwithin thee500coreformappingtheseregions. Referto theMPC8540Reference
Manual listed in Appendix A, Related Documentation, for details.
Notes
1. This is the default location for the CCSRs, but it is not mapped after reset.
2. Only FFFF F000 to FFFF FFFF is mapped after reset. The e500 core fetches the first instruction
from FFFF FFFC following a reset.
Table 1-2. MVME712-101 RTM Features Summary
Feature Description
I/O – One five-row P2 backplane connector for serial and Ethernet I/O
passed from the MVME3100
– Four RJ-45 connectors for rear-panel I/O: four asynchronous
serial channels
– Two RJ-45 connectors with integrated LEDs for rear panel I/O:
one 10/100/1000 Ethernet channel and one 10/100 Ethernet
channel
– One PIM site with rear-panel I/O
Miscellaneous – Four rear-panel status indicators: 10/100/1000 and 10/100
Ethernet link/speed and activity LEDs
Table 1-3. Default Processor Address Map
Processor Address
Size Definition NotesStart End
0000 0000 FF6F FFFF 4087M Not mapped
FF70 0000 FF7F FFFF 1M MPC8540 CCS Registers 1
FF80 0000 FFFF FFFF 8M Flash 2

MVME3100 Programmer’s Guide (V3100A/PG1)
Chapter 1 Board Description and Memory Maps
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MOTLoad’s Processor Memory Map
MOTLoad’s processor memory map is given in the following table.
Notes
1. Reserved for future larger FLASH devices.
2. The FLASH is logically one bank but may be physically implemented in two banks.
After RESET, the MPC8540 does not map any PCI memory space (inbound or outbound), and does not
respond to Config cycles.
VME Memory Map
The MVME3100 is fully capable of supporting both the PReP and the CHRP VME Memory Map
examples with RAM size limited to 2GB.
Table 1-4. MOTLoad’s Processor Address Map
Processor Address
Size Definition NotesStart End
0000 0000 top_dram-1 dram_size
(2GB max) System Memory (on-board DRAM)
8000 0000 DFFF FFFF 1.5GB PCI Memory Space/VME
E000 0000 E0FF FFFF 16MB PCI I/O Space
E100 0000 E10F FFFF 1MB MPC8540 CCSR
E1100 0000 E1FF FFFF 15MB Not Used
E200 0000 E2FF FFFF 16MB Status/Control Registers/UARTs,
External Timers
E300 0000 EFFF FFFF 208MB Not Used
F000 0000 F7FF FFFF 128MB Reserved 1, 2
bottom_flash FFFF FFFF flash_size
(128MB max) FLASH 2

Chapter 1 Board Description and Memory Maps
MVME3100 Programmer’s Guide (V3100A/PG1) 7
System I/O Memory Map
System resources including System Control and Status registers, external timers, and the QUART are
mapped into a 16MB address range from the MVME3100 via the MPC8540 local bus controller (LBC).
The memory map is defined in the following table, including the LBC bank chip select used to decode
the register:
Table 1-5. System I/O Memory Map
Address Definition LBC Bank /
Chip Select Notes
E200 0000 System Status Register 2 3
E200 0001 System Control Register 2 3
E200 0002 Status Indicator Register 2 3
E200 0003 Flash Control/Status Register 2 3
E200 0004 PCI Bus A Status Register 2 3
E200 0005 PCI Bus B Status Register 2 3
E200 0006 PCI Bus C Status Register 2 3
E200 0007 Interrupt Detect Register 2 3
E200 0008 Presence Detect Register 2 3
E200 0009 PLD Revision 2 3
E200 000C PLD Date Code (32 bits) 2 3
E200 0010 Test Register 1 (32 bits) 2 3
E200 0014 Test Register 2 (32 bits) 2 3
E200 0018 -
E200 0FFF Reserved 1
E201 1000 -
E201 1FFF COM 2 (QUART channel 1) 3
E201 2000 -
E201 2FFF COM 3 (QUART channel 2) 3
E201 3000 -
E201 3FFF COM 4 (QUART channel 3) 3
E201 4000 -
E201 4FFF COM 5 (QUART channel 4) 3
E201 5000 -
E201 FFFF Reserved 1
E202 0000 External PLD Tick Timer Prescaler Register 4 2
E202 0010 External PLD Tick Timer 1 Control Register 4 2
E202 0014 External PLD Tick Timer 1 Compare Register 4 2
E202 0018 External PLD Tick Timer 1 Counter Register 4 2
E202 001C Reserved 4 2
E202 0020 External PLD Tick Timer 2 Control Register 4 2
E202 0024 External PLD Tick Timer 2 Compare Register 4 2

MVME3100 Programmer’s Guide (V3100A/PG1)
Chapter 1 Board Description and Memory Maps
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Notes
1. Reserved for future implementation
2. 32-bit write only
3. Byte read/write capable
E202 0028 External PLD Tick Timer 2 Counter Register 4 2
E202 002C Reserved 4 2
E202 0030 External PLD Tick Timer 3 Control Register 4 2
E202 0034 External PLD Tick Timer 3 Compare Register 4 2
E202 0038 External PLD Tick Timer 3 Counter Register 4 2
E202 003C Reserved 4 2
E202 0040 External PLD Tick Timer 4 Control Register 4 2
E202 0044 External PLD Tick Timer 4 Compare Register 4 2
E202 0048 External PLD Tick Timer 4 Counter Register 4 2
E202 004C -
E2FF FFFF Reserved 1
Table 1-5. System I/O Memory Map (continued)
Address Definition LBC Bank /
Chip Select Notes