Motorola MC68340 User manual

MC68340UM/ AD
Rev. 1
INTEGRATED
PROCESSOR
WITHDMA
USER 'S MANUAL
® MOTOROLA

®MOTOROLA
MC68340
Integrated Processor with DMA
User's Manual
MolOroIa reserves the right to make changes without further nolk:e to any products herein to Imprcw reliability, function or deslgh. MolDrola does not assume any
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eMOTOROLA INC" 1992

PREFACE
The complete documentation package for the MC68340 consists of the MC68340UM/AD,
MC68340 Integrated Processor with DMA User's Manual, M68000PM/AD, MC68000
Family Programmer's Reference Manual, and the MC68340P/D, MC68340 Integrated
Processorwith DMA Product Brief.
The MC68340 Integrated with DMA Processor User's Manual describes the programming,
capabilities, registers, and operation of the MC68340; the MC68000 Family Programmer's
Reference Manual provides instruction details for the MC68340; and the
MC68340
Integrated Processor with DMA Product Briefprovides a brief description of the MC68340
capabilities.
This user's manual is organized as follows:
Section 1
Section 2
Section 3
Section 4
Section 5
Section 6
Section 7
Device Overview Section 8
Signal Descriptions Section 9
Bus Operation
System Integration Module Section 10
CPU32 Section
11
DMA Controller Module Section 12
Serial Module
6SK FAX-IT
FAX [phone]
Timer Modules
IEEE 1149.1 Test Access
Port
Applications
Electrical Characteristics
Ordering Information and
Mechanical Data
The Motorola High-End Technical Publication Department provides a FAX number for you
to submit any questions and comments about this document.
We welcome your
suggestions for improving ourdocumentation orany questions concerning our products.
Please provide the part number and revision number (located in upper right-hand corner
on the cover), and the title of the document when submitting. When referring to items in
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number~ figure number,
table number, and line number if needed. Reference the line number from the top of the
page.
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through Friday,
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TABLE OF CONTENTS
Paragraph
Number Title
Page
Number
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.1.7
1.3.2
1.3.3
1.3.4
1.4
1.5
1.6
1.7
Section 1
Device Overview
M68300 Family ..................................................................................................1-2
Organization ..................................................................................................1-3
Advantages....................................................................................................1-3
Central Processor Unit .....................................................................................1-3
CPU32 ............................................................................................................1-4
Background Debug Mode...........................................................................1-4
On-Chip Peripherals........................................................................................1-5
System Integration Module.........................................................................1-5
External Bus Interface..............................................................................1-5
System Configuration and Protection...................................................1-6
Clock Synthesizer.....................................................................................1-6
Chip Select and Wait State Generation...............................................1-6
Interrupt Handling.....................................................................................1-6
Discrete 1/0 Pins ........................................................................................1-6
IEEE 1149.1 Test Access Port................................................................1-7
Direct Memory Access Module ...................................................................1-7
Serial Module................................................................................................1-7
Timer Modules ...............................................................................................1-8
Power Consumption Management................................................................1-8
Physical ..............................................................................................................1-9
Compact Disc-Interactive ................................................................................1-9
More Information............................................................................................... 1-1 0
Section 2
Signal Descriptions
2.1 Signal Index.......................................................................................................2-2
2.2 Address Bus .......................................................................................................2-4
2.2.1 Address Bus (A23-AO)................................................................................2-4
2.2.2 Address Bus (A31-A24)..............................................................................2-4
2.3 Data Bus (015-00) ..........................................................................................2-4
2.4 Function Codes (FC3-FCO) ............................................................................2-5
2.5 Chip Selects (CS3-CSO).................................................................................2-5
2.6 Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3)......................................2-6
MOTOROLA MC68340 USER'S MANUAL
iii

Paragraph
Number
TABLE OF CONTENTS (Continued)
Title
Page
Number
2.7 Bus Control Signals ......................................................................................... 2-6
2.7.1 Data and Size Acknowledge (DSACK1, DSACKO) ................................. 2-6
2.7.2 Address Strobe
(AS) .................................................................................... 2-6
2.7.3
Data Strobe (OS) ...........................................................................................2-7
2.7.4 Transfer
Size (SIZ1, SIZO) .......................................................................... 2-7
2.7.5
ReadWrite (RIW) ...........................................................................................2-7
2.8
Bus Arbitration Signals .................................................................................... 2-7
2.8.1 Bus Request (BR) ..........................................................................................2-7
2.8.2
Bus Grant (BG) .............................................................................................. 2-7
2.8.3
Bus Grant Acknowledge (BGACK) .............................................................2-7
2.8.4 Read-Modify-Write
Cycle (RMC) ................................................................ 2-8
2.9 Exception Control Signals
.............................................................................. 2-8
2.9.1 Reset (RESET) ...............................................................................................2-8
2.9.2
Halt (HAL T) .....................................................................................................2-8
2.9.3
Bus Error (BERR) .......................................................................................... 2-8
2.10 Clock Signals .................................................................................................... 2-8
2.10.1 System Clock (CLKOUT) ............................................................................2-8
2.10.2 Crystal Oscillator (EXTAL, XTAL) ...............................................................2-9
2.10.3 External Filter Capacitor (XFC) .................................................................. 2-9
2.10.4 Clock Mode Select (MODCK) .....................................................................2-9
2.11 Instrumentation and Emulation Signals ................................ , ...................... 2-9
2.11.1 Instruction Fetch (IFETCH) ...........................................................................2-9
2.11.2 Instruction
Pipe (I PIPE) ................................................................................ 2-9
2.11.3 Breakpoint
(BKPT) ........................................................................................ 2-10
2.11.4 Freeze (FREEZE) .......................................................................................... 2-1 0
2.12 DMA Module Signals ....................................................................................... 2-10
2.12.1 DMA Request (DREQ2, DREQ1) ................................................................ 2-10
2.12.2 DMA Acknowledge (DACK2, DACK1) ....................................................... 2-1 0
2.12.3 DMA Done (DONE2, DONE1) ..................................................................... 2-10
2.13 Serial Module Signals ..................................................................................... 2-11
2.13.1 Serial Crystal Oscillator (X2, X1) ............................................................... 2-11
2.13.2 Serial External Clock Input (SCLK) ........................................................... 2-11
2.13.3 Receive Data (RxDA, RxDB) ....................................................................... 2-11
2.13.4 Transmit Data (TxDA, TxDB) ....................................................................... 2-11
2.13.5 Clearto Send (CTSA, CTSB) ...................................................................... 2-11
2.13.6 Request to Send (R'fSA, R'f'SB)................................................................. 2-11
2.13.7 Transmitter Ready (TxRDYA) ...................................................................... 2-11
2.13.8 Receiver Ready (RxRDYA) .......................................................................... 2-12
2.14 Timer Signals
.................................................................................................... 2-12
2.14.1 Timer Gate (TGATE2, TGATE1) ................................................................. 2-12
2.14.2 Timer Input
(TIN2, TIN 1) .............................................................................. 2-12
2.14.3
Timer Output (TOUT2, TOUT1 )...................................................................2-12
iv MC68340 USER'S MANUAL
MOTOROLA

Paragraph
Number
TABLE OF CONTENTS (Continued)
Title
Page
Number
2.15 Test Signals.......................................................................................................2-13
2.15.1 Test Clock (TCK)...........................................................................................2-13
2.15.2 Test Mode Select (TMS)..............................................................................2-13
2.15.3 Test Data
In (TO I) ..........................................................................................2-13
2.15.4 Test DataOut (TOO).....................................................................................2-13
2.16 SynthesizerPower
(VCCSYN) ..........................................................................2-13
2.17 System Powerand Ground (Vee and GNO)................................................2-13
2.18 Signal Summary...............................................................................................2-13
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.7.1
3.1.7.2
3.1.7.3
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.2.3.6
3.2.3.7
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
MOTOROLA
Section 3
Bus Operation
Bus TransferSignals........................................................................................ 3-1
Bus Control Signals.....................................................................................3-2
Function Code Signals................................................................................3-3
Address Bus (A31-AO) ................................................................................3-4
Address Strobe (AS) ....................................................................................3-4
Data Bus
(015-00) ......................................................................................3-4
Data Strobe (OS) ...........................................................................................3-4
Bus Cycle Termination Signals..................................................................3-4
Data Transfer and Size Acknowledge Signals
(OSACK1 and OSACKO) ......................................................................3-4
Bus Error (BERR) ......................................................................................3-5
Autovector (AVEC)....................................................................................3-5
Data Transfer Mechanism...............................................................................3-5
Dynamic Bus Sizing.....................................................................................3-5
Misaligned Operands...................................................................................3-7
Operand Transfer Cases.............................................................................3-7
Byte Operand to 8-Bit Port, Odd
or Even (AO =X) ..............................3-7
Byte Operand to 16-Bit Port, Even
(AO = 0)..........................................3-8
Byte Operand to 16-Bit Port, Odd (AO = 1)...........................................3-9
Word Operand to 8-Bit Port, Aligned.....................................................3-9
Word Operand to 16-Bit Port, Aligned...................................................3-10
Long-word Operand to 8-Bit Port, Aligned...........................................3-10
Long-Word Operand to 16-Bit Port, Aligned........................................3-12
Bus Operation................................................................................................3-14
Synchronous Operation with
OSACKx ......................................................3-14
Fast Termination Cycles...............................................................................3-15
Data Transfer Cycles........................................................................................3-16
Read Cycle.....................................................................................................3-16
Write Cycle.....................................................................................................
3-18
Read-Modify-Write Cycle.............................................................................3-19
MC68340 USER'S MANUAL v

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3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.4.3
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
4.1
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.2.6.1
4.2.2.6.2
4.2.2.7
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.4
4.2.4.1
vi
TABLE OF CONTENTS (Continued)
Title
Page
Number
CPU Space Cycles...........................................................................................3-21
Breakpoint Acknowledge Cycle.................................................................3-22
LPSTOP Broadcast Cycle...........................................................................3-23
Module Base Address Register Access....................................................3-27
Interrupt Acknowledge Bus Cycles............................................................3-27
Interrupt Acknowledge Cycle-Terminated Normally........................3-27
Autovector Interrupt Acknowledge Cycle.............................................3-29
Spurious Interrupt Cycle..........................................................................3-30
Bus Exception Control Cycles........................................................................3-32
Bus Errors.......................................................................................................3-34
Retry Operation .............................................................................................3-36
Halt Operation ...............................................................................................3-38
Double Bus Fault ..........................................................................................3-39
Bus Arbitration...................................................................................................
3-40
Bus Request...................................................................................................3-43
Bus Grant........................................................................................................3-43
Bus Grant Acknowledge..............................................................................3-43
Bus Arbitration Control.................................................................................3-44
Show Cycles..................................................................................................3-44
Reset Operation ................................................................................................3-46
Section 4
System Integration Module
Module Overview.............................................................................................. 4-1
Module Operation.............................................................................................4-2
Module Base Address Register Operation...............................................4-2
System Configuration and Protection Operation....................................4-3
System Configuration ..............................................................................4-5
Internal Bus Monitor.................................................................................4-6
Double Bus Fault Monitor........................................................................4-6
Spurious Interrupt Monitor......................................................................4-6
Software Watchdog..................................................................................4-6
Periodic Interrupt Timer...........................................................................4-7
Periodic Timer Period Calculation.....................................................4-8
Using the Periodic Timer as a Real-Time Clock.............................4-9
Simultaneous Interrupts by Sources in the SIM40.............................4-9
Clock Synthesizer Operation......................................................................4-9
Phase Comparator and Filter.................................................................4-11
Frequency Divider....................................................................................4-12
Clock Control.............................................................................................4-13
Chip Select Operation .................................................................................4-13
Programmable Features..........................................................................4-14
MC68340 USER'S MANUAL MOTOROLA

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Number
4.2.4.2
4.2.5
4.2.5.1
4.2.5.2
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.3.3
4.3.4
4.3.4.1
4.3.4.2
4.3
.. 4.3
4.3.5
4.3.5.1
4.3.5.2
4.3.5.3
4.3.5.4
4.3.5.5
4.3.5.6
4.3.5.7
4.4
4.4.1
4.4.2
4.4.3
TABLE OF CONTENTS (Continued)
Title
Page
Number
Global Chip Select Operation ................................................................4-14
External Bus Interface Operation...............................................................4-15
PortA...........................................................................................................4-15
Port B...........................................................................................................4-16
Low-Power Stop...........................................................................................4-17
Freeze.............................................................................................................4-17
Programming ModeL.......................................................................................4-18
Module Base Address Register (MBAR)...................................................4-20
System Configuration and Protection Registers.....................................4-21
Module Configuration Register (MCR)..................................................4-21
Autovector Register (AVR).......................................................................4-23
Reset Status Register (RSR)...................................................................4-23
Software Interrupt Vector Register (SWIV)...........................................4-24
System Protection Control Register (SYPCR).....................................4-24
Periodic Interrupt Control Register (PICR) ...........................................4-26
Periodic Interrupt Timer Register (PITR)...............................................4-27
Software Service Register (SWSR) ......................................................4-28
Clock Synthesizer Control Register (SYNCR) ........................................4-28
Chip Select Registers...................................................................•..............4-29
Base Address Registers ..........................................................................4-30
Address Mask Registers..........................................................................4-31
Chip Select Registers Programming Example....................................4-33
External Bus Interface ControL...................................................................4-33
Port A Pin Assignment Register 1 (PPARA1).......................................4-33
Port A Pin Assignment Register 2 (PPARA2).......................................4-34
Port A Data Direction Register (DORA).................................................4-34
Port A Data Register (PORTA)................................................................4-34
Port B Pin Assignment Register (PPARB) ............................................4-35
Port B Data Direction Register (DDRB).................................................4-35
Port B Data Register (pORTB, PORTB1) ..............................................4-35
MC68340 Initialization Sequence.................................................................4-36
Startup............................................................................................................4-36
SIM40 Module Configuration .....................................................................4-36
SIM40 Example Configuration Code........................................................4-38
Section 5
CPU32
5.1 Overview............................................................................................................. 5-1
5.1.1 Features.......................................................................................................;;.5-2
5.1.2 Virtual Memory..............................................................................................5-2
5.1.3 Loop Mode Instruction Execution .....................................:........................5-3
MOTOROLA
MC68340 USER'S MANUAL
vii

Paragraph
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5.1.4
5.1.5
5.1.6
5.1.7
5.1.7.1
5.1.7.2
5.1.8
5.1.9
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.1.1
5.3.1.1.1
5.3.1.1.2
5.3.1.2
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.3.3.5
5.3.3.6
5.3.3.7
5.3.3.8
5.3.3.9
5.3.3.10
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.4.5
5.3.5
5.3.6
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
viii
TABLE OF CONTENTS (Continued)
Title
Page
Number
Vector Base Register.................................................................................... 5-4
Exception Handling...................................................................................... 5-4
Addressing Modes........................................................................................ 5-5
Instruction Set. ............................................................................................... 5-5
Table lookup and Interpolate Instructions........................................... 5-7
low-Power STOP Instruction................................................................. 5-7
Processing States......................................................................................... 5-7
Privilege States............................................................................................. 5-7
Architecture Summary..................................................................................... 5-8
Programming Model..................................................................................... 5-8
Registers......................................................................................................... 5-1 0
Instruction Set....................................................................................................5-11
M68000 Family Compatibility.....................................................................5-11
New Instructions........................................................................................5-11
Low-Power Stop (lPSTOP)................................................................5-11
Table lookup and Interpolation (TBl) ..............................................5-12
Unimplemented Instructions...................................................................5-12
Instruction Format and Notation.................................................................5-12
Instruction Summary....................................................................................5-15
Condition Code Register.........................................................................5-20
Data Movement Instructions...................................................................5-21
Integer Arithmetic Operations.................................................................5-22
logic Instructions......................................................................................5-24
Shift and Rotate Instructions...................................................................5-24
Bit Manipulation Instructions...................................................................5-25
Binary-Coded Decimal (BCD) Instructions..........................................5-26
Program Control Instructions..................................................................5-26
System Controllnstructions....................................................................5-27
Condition Tests.........................................................................................5-29
Using the TBl Instructions..........................................................................5-29
Table Example 1: Standard Usage.......................................................5-30
Table Example 2: Compressed Table ..................................................5-31
Table Example 3: 8-Bit Independent Variable....................................5-32
Table Example 4: Maintaining Precision..............................................5-34
Table Example 5: Surface Interpolations.............................................5-36
Nested Subroutine Calls.............................................................................5-36
Pipeline Synchronization with the NOP Instruction................................5-36
Processing States.............................................................................................5-36
State Transitions...........................................................................................5-37
Privilege levels .............................................................................................5-37
Supervisor Privilege leveL.....................................................................5-37
User Privilege level .................................................................................5-39
MC68340 USER'S MANUAL MOTOROLA

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5.4.2.3
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.2.4
5.5.2.5
5.5.2.6
5.5.2.7
5.5.2.8
5.5.2.9
5.5.2.10
5.5.2.11
5.5.2.12
5.5.3
5.5.3.1
5.5.3.1.1
5.5.3.1.2
5.5.3.1.3
5.5.3.1.4
5.5.3.2
5.5.3.2.1
5.5.3.2.2
5.5.3.2.3
5.5.3.2.4
5.5.3.2.5
5.5.3.2.6
5.5.3.2.7
5.5.4
5.5.4.1
5.5.4.2
5.5.4.3
5.6
5.6.1
5.6.1.1
5.6.1.2
MOTOROLA
TABLE OF CONTENTS (Continued)
Title Page
Number
Changing Privilege Level ........................................................................5-39
Exception
Processing ...................................................................................... 5-39
Exception Vectors ......................................................................................... 5-40
Types of Exceptions ................................................................................. 5-41
Exception Processing Sequence .......................................................... 5-41
Exception Stack Frame ............................................................................ 5-42
Multiple Exceptions .................................................................................. 5-42
Processing of Specific Exceptions ............................................................ 5-44
Reset ........................................................................................................... 5-44
Bus Error ..................................................................................................... 5-46
Address Error ............................................................................................. 5-46
Instruction Traps ........................................ ~ ............................................... 5-47
Software BreakpOints ............................................................................... 5-47
Hardware Breakpoints ............................................................................. 5-48
Format Error ............................................................................................... 5-48
Illegal or Unimplemented Instructions .................................................. 5-48
Privilege Violations ................................................................................... 5-49
Tracing
........................................................................................................ 5-50
Interrupts ..................................................................................................... 5-51
Retum from Exception .............................................................................. 5-52
Fault Recovery ............................................................................................... 5-53
Types of Faults .......................................................................................... 5-55
Type I-Released Write Faults ........................................................... 5-55
Type II-Prefetch, Operand, RMW, and MOVEP Faults .................5-56
Type III-Faults During MOVEM Operand Transfer ....................... 5-57
Type IV-Faults During Exception Processing ............................... 5-57
Correcting a Fault .................................................. , .................................. 5-57
Type !-Completing Released Writes via Software ....................... 5-57
Type I-Completing Released Writes via RTE ................................ 5-57
Type II-Correcting Faults via RTE ....................................................5-58
Type III-Correcting Faults via Software .......................................... 5-58
Type III-Correcting Faults by Conversion and Restart .................5-58
Type III-Correcting Faults via RTE ...................................................5-59
Type IV-Correcting Faults via Software ......................................... 5-59
CPU32 Stack Frames .................................................................................. 5-60
Four-Word Stack Frame .......................................................................... 5-60
Six-Word Stack Frame ............................................................................. 5-60·
Bus Error Stack Frame ............................................................................. 5-60
Development Support ...................................................................................... 5-63
CPU32 Integrated Development Support ................................................ 5-63
Background Debug Mode (BDM) Overview ........................................ 5-64
Deterministic
Opcode Tracking Overview ............................................ 5-64
MC68340 USER'S MANUAL Ix

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5.6.3.1
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5.7
5.7.1
5.7.1.1
5.7.1.2
x
TABLE OF CONTENTS (Continued)
Title Page
Number
On-Chip Hardware Breakpoint Overview.............................................5-64
Background Debug Mode...........................................................................5-65
Enabling BDM...........................................................................................5-65
BDM Sources............................................................................................5-66
External BKPT Signal..........................................................................5-66
BGND Instruction ..................................................................................5-66
Double Bus Fault. .................................................................................5-66
Entering BDM............................................................................................5-66
Command Execution................................................................................5-67
BDM Registers...........................................................................................5-67
Fault Address Register (FAR) .............................................................5-67
Return Program Counter (RPC) .........................................................5-67
Current Instruction Program Counter (PCC)....................................5-67
Returning from BDM.................................................................................5-68
Serial Interlace..........................................................................................5-68
CPU Serial Logic..................................................................................5-69
Development System Serial Logic....................................................5-71
Command Set...........................................................................................5-73
Command Format.................................................................................5-73
Command Sequence Diagram..........................................................5-74
Command Set Summary.....................................................................5-75
Read AID Register (RAREG/RDREG)................................................5-76
Write AID Register (WAREGIWDREG) ..............................................5-77
Read System Register (RSREG)........................................................5-77
Write System Register (WSREG).......................................................5-78
Read Memory Location (READ).........................................................5-79
Write Memory Location (WRITE)........................................................5-79
Dump Memory Block (DUMP)............................................................5-80
Fill Memory Block (FILL)......................................................................5-82
Resume Execution (GO)......................................................................5-83
Call UserCode (CALL)........................................................................5-83
Reset Peripherals (RST)......................................................................5-85
No Operation (NOP).............................................................................5-85
Future Commands................................................................................5-86
Deterministic Opcode Tracking..................................................................5-86
Instruction Fetch (IFETCH) ..................................,....................................5-86
Instruction Pipe (IPIPE)............................................................................5-87
Opcode Tracking during Loop Mode....................................................5-88
Instruction Execution Timing...........................................................................5-88
Resource Scheduling .............................................................................., ... 5-88
Microsequencer........................................................................................5-89
Instruction Pipeline...................................................................................5-89
MC68340 USER'S MANUAL MOTOROLA

Paragraph
Number
5.7.1.3
5.7.1.3.1
5.7.1.3.2
5.7.1.3.3
5.7.1.4
5.7.1.5
5.7.1.6
5.7.1.7
5.7.2
5.7.2.1
5.7.2.2
5.7.2.3
5.7.3
5.7.3.1
5.7.3.2
5.7.3.3
5.7.3.4
5.7.3.5
5.7.3.6
5.7.3.7
5.7.3.8
5.7.3.9
5.7.3.10
5.7.3.11
5.7.3.12
5.7.3.13
5.7.3.14
6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.2
6.3.2.1
MOTOROLA
TABLE OF CONTENTS (Continued)
Title
Page
Number
Bus Controller Resources .......................................................................5-89
Prefetch Controller................................................................................5-90
Write Pending Buffer............................................................................5-90
Microbus Controller..............................................................................5-91
Instruction Execution Overlap.................................................................5-91
Effects ofWait States................................................................................5-92
Instruction Execution Time Calculation ................................................5-92
Effects of Negative Tails ..........................................................................5-93
Instruction Stream Timing Examples ........................................................5-94
Timing Example i-Execution Overlap................................................5-94
Timing Example 2-Branch Instructions..............................................5-95
Timing Example 3-Negative Tails.......................................................5-96
Instruction Timing Tables............................................................................5-97
Fetch Effective Address...........................................................................5-99
Calculate Effective Address.................................................................... 5-1 00
MOVE Instruction ...................................................................................... 5-1 01
Special-Purpose MOVE Instruction....................................................... 5-1 01
Arithmetic/Logic Instructions...................................................................5-102
Immediate Arithmetic/Logic Instructions............................................... 5-1 05
Binary-Coded Decimal and Extended Instructions............................ 5-1 06
Single Operand Instructions...................................................................5-107
Shift/Rotate Instructions...........................................................................5-108
Bit Manipulation Instructions................................................................... 5-1 09
Conditional Branch Instructions.............................................................5-11 0
Control Instructions...................................................................................5-111
Exception-Related Instructions and Operations..................................5-111
Save and Restore Operations................................................................5-111
Section 6
DMA
Controller Module
DMA Module Overview....................................................................................6-2
DMA Module Signal Definitions.....................................................................6-4
DMA Request (DREQx)................................................................................6-4
DMA Acknowledge (DACKx) .......................................................................6-4
DMA Done (DONEx).....................................................................................6-4
Transfer Request Generation .........................................................................6-4
Internal Request Generation.......................................................................6-4
Internal Request. Maximum Rate...........................................................6-5
Internal Request, Limited Rate ...............................................................6-5
External Request Generation .....................................................................6-5
External Burst Mode.................................................................................6-5
MC68340 USER'S MANUAL
xi

Paragraph
Number
6.3.2.2
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.2
6.4.2.1
6.4.2.2
6.5
6.6
6.6.1
6.6.2
6.6.2.1
6.6.2.2
6.6.3
6.6.3.1
6.6.3.2
6.6.3.3
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.8
6.9
6.9.1
6.9.1.1
6.9.1.2
6.9.2
TABLE OF CONTENTS (Continued)
Title
Page
Number
External Cycle Steal Mode .....................................................................6-5
Data Transfer Modes........................................................................................6-6
Single-Address Mode..................................................................................
6-6
Single-Address Read...............................................................................6-7
Single-Address Write...............................................................................6-9
Dual-Address Mode.....................................................................................6-12
Dual-Address Read..................................................................................6-12
Dual-Address Write ..................................................................................6-14
Bus Arbitration...................................................................................................6-18
DMA Channel Operation.................................................................................6-18
Channel Initialization and Startup.............................................................6-18
Data Transfers...............................................................................................6-19
Internal Request Transfers......................................................................6-19
External Request Transfers.....................................................................6-19
Channel Termination ...................................................................................6-20
Channel Termination ...............................................................................6-20
Interrupt Operation....................................................................................6-20
Fast Termination Option ..........................................................................6-20
Register Description.........................................................................................6-22
Module Configuration Register (MCR)......................................................6-23
Interrupt Register (INTR)..............................................................................6-26
Channel Control Register (CCR) ...............................................................6-26
Channel Status Register (CSR).................................................................6-30
Function Code Register (FCR) ...................................................................6-32
Source Address Register (SAR) ................................................................6-33
Destination Address Register (DAR).........................................................6-33
Byte Transfer Counter Register (BTC) ......................................................6-34
Data Packing .....................................................................................................6-35
DMA Channel Initialization Sequence .........................................................6-36
DMA Channel Configuration......................................................................6-36
DMA Channel Operation in Single-Address Mode............................6-37
DMA Channel Operation in Dual-Address Mode...............................6-37
DMA Channel Example Configuration Code..........................................6-38
Section 7
Serial Module
7.1 Module Overview..............................................................................................7-2
7.1.1 Serial Communication Channels A and B...............................................7-3
7.1.2 Baud Rate Generator Logic........................................................................7-3
7.1.3 Internal Channel Control Logic..................................................................7-3
7.1.4 Interrupt Control Logic.................................................................................7-3
xii
MC68340 USER'S MANUAL
MOTOROLA

Paragraph
Number
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.8.1
7.2.8.2
7.2.9
7.2.9.1
7.2.9.2
7.2.10
7.2.11
7.2.12
7.2.12.1
7.2.12.2
7.2.13
7.2.13.1
7.2.13.2
7.2.13.3
7.3
7.3.1
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.3.4
7.3.5
7.3.5.1
7.3.5.2
7.3.5.3
7.4
7.4.1
7.4.1.1
MOTOROLA
TABLE OF CONTENTS (Continued)
Title
"' _____ : ____ ,c ~ __ :_I "._-.1 ..'_ .1._ •• ""'~n,..n~
Page
Number
""'V. I ItJQ, 1..,;;)"'1. "I ....,lII0I1111;&1 IVIUUU'Q LV IVIVUVVU 1 ••••••••••••••••••••••••••••••••••••••••••••• ,-.,..
Serial Module Signal Definitions...................................................................7-4
Crystal Input or External Clock (X1) ..........................................................7-5
Crystal Output (X2) ....................................................................................... 7-5
External Input (SCLK)..................................................................................7-6
Channel A Transmitter Serial Data Output (TxDA).................................7-6
Channel A Receiver Serial Data Input (RxDA)........................................7-6
Channel B Transmitter Serial Data Output (TxDB).................................7-6
Channel B Receiver Serial Data Input (RxDB)........................................7-6
Channel A Request-To-Send (RTSA).......................................................7-6
RTSA ...........................................................................................................7-6
OPO ..............................................................................................................7-6
Channel B Request-To-Send (RTSB).......................................................7-6
RTSB ...........................................................................................................7-7
OP1 ..............................................................................................................7-7
Channel A Clear-To-Send (CTSA).............................;..............................7-7
Channel B Clear-To-Send (CTSB)............................................................7-7
Channel A Transmitter Ready (TxRDYA)..................................................7-7
TxRDYA......................................................................................................
7-7
OP6..............................................................................................................7-7
Channel A Receiver Ready (RxRDYA)......................................................7-7
RxRDYA......................................................................................................7-7
FFULLA.......................................................................................................
7-7
OP4..............................................................................................................7-7
Operation............................................................................................................7-8
Baud Rate Generator...................................................................................7-8
Transmitter and Receiver Operating Modes............................................7-8
Transmitter.................................................................................................
7-1 0
Receiver......................................................................................................7-11
FIFO Stack..................................................................................................7-12
Looping Modes.............................................................................................7-14
Automatic Echo Mode..............................................................................7-14
Local Loopback Mode.............................................................................
7-14
Remote Loopback Mode.........................................................................7-14
Multidrop Mode.............................................................................................7-15
Bus Operation................................................................................................7-17
Read Cycles...............................................................................................7-17
Write Cycles...............................................................................................7-17
Interrupt Acknowledge Cycles................................................................7-17
Register Description and Programming .......................................................7-17
Register Description.....................................................................................7-17
Module Configuration Register (MCR)..................................................7-19
MC68340 USER'S MANUAL xiii

Paragraph
Number
7.4.1.2
7.4.1.3
7.4.1.4
7.4.1.5
7.4.1.6
7.4.1.7
7.4.1.8
7.4.1.9
7.4.1.10
7.4.1.11
7.4.1.12
7.4.1.13
7.4.1.14
7.4.1.15
7.4.1.16
7.4.1.17
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.5
7.5.1
7.5.2
8.1
8.1.1
8.1.1.1
8.1.1.2
8.1.1.3
8.1.1.4
8.1.2
8.1.3
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
xiv
TABLE OF CONTENTS (Continued)
Title
Page
Number
Interrupt Level Register (ILR)..................................................................7-21
Interrupt Vector Register (IVR)................................................................7-21
Mode Register 1 (MR1)............................................................................7-22
Status Register (SR).................................................................................7-24
Clock-Select Register (CSR)..................................................................7-26
Command Register (CR) .........................................................................7-27
Receiver Buffer (RB).................................................................................7-30
Transmitter Buffer (TB).............................................................................7-30
Input Port Change Register (IPCR)........................................................7-31
Auxiliary Control Register (ACR)............................................................7-32
Interrupt Status Register (ISR)................................................................7-32
Interrupt Enable Register (IER)...............................................................7-34
Input Port (IP).............................................................................................7-35
Output Port Control Register (OPCR)....................................................7-35
Output Port Data Register (OP) ..............................................................7-37
Mode Register 2 (MR2)............................................................................7-37
Programming.................................................................................................
7-40
Serial Module Initialization .....................................................................7-40
VO Driver Example....................................................................................7-40
Interrupt Handling.....................................................................................7-40
Serial Module Initialization Sequence.........................................................7-46
Serial Module Configuration......................................................................7-46
Serial Module Example Configuration Code..........................................7-47
Section 8
Timer Modules
Module Overview.............................................................................................. 8-1
Timer and Counter Functions.....................................................................8-2
Prescaler and Counter.............................................................................8-2
limeout Detection.....................................................................................8-2
Comparator................................................................................................8-2
Clock Selection Logic..............................................................................8-3
Internal Control Logic...................................................................................8-3
Interrupt Control Logic.................................................................................8-4
Timer Modules Signal Definitions.................................................................8-4
limer Input (TIN1, TIN2) ...........................................;..................................8-5
Timer Gate (TGATE1, TGATE2) .................................................................8-6
limer Output (TOUT1, TOUT2)...................................................................8-6
Operating Modes..............................................................................................8-6
Input Capture/Output Compare..................................................................8-6
Square-Wave Generator.............................................................................8-8
MC68340 USER'S MANUAL MOTOROLA

Paragraph
Number
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.9.1
8.3.9.2
8.3.9.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.5
8.5.1
8.5.2
TABLE OF CONTENTS (Continued)
Title
Page
Number
\I<)ri<) .... lo n"h,_r."I'lo ~n"<)ro_W<)"o ~onorl:ltnr R-Q
- ------"- - --, -" --- - -.-----
Variable-Width Single-Shot Pulse Generator......................................... 8-1 0
Pulse-Width Measurement..........................................................................8-12
Period Measurement....................................................................................8-13
Event Count ...................................................................................................8-14
Timer Bypass.................................................................................................8-16
Bus Operation................................................................................................8-17
Read Cycles...............................................................................................8-17
Write Cycles...............................................................................................8-17
Interrupt Acknowledge Cycles................................................................8-17
Register Description.........................................................................................8-17
Module Configuration Register
(MCR) ......................................................8-18
Interrupt Register (IR) ...................................................................................8-20
Control Register (CR) ...................................................................................8-20
Status Register (SR) .....................................................................................8-23
Counter Register (CNTR) ............................................................................8-25
Preload 1 Register (PREL1)........................................................................8-25
Preload 2 Register
(PREL2) ........................................................................8-26
Compare Register
(COM) ............................................................................8-26
Timer Module Initialization Sequence..........................................................8-27
Timer Module Configuration.......................................................................8-27
Timer Module Example Configuration Code...........................................8-28
Section 9
IEEE 1149.1 Test Access Port
9.1 Overview............................................................................................................. 9-1
9.2 TAP Controller...................................................................................................9-2
9.3 Boundary Scan Register.................................................................................9-3
9.4 Instruction Register...........................................................................................9-9
9.4.1 EXTEST (000) ...............................................................................................9-10
9.4.2 SAMPLE/PRELOAD (001) .......................................................................... 9-1 0
9.4.3 BYPASS (X1X, 101)..................................................................................... 9-11
9.4.4 HI-Z (1 00) ....................................................................................................... 9-11
9.5 MC68340 Restrictions...................................................................................... 9-11
9.6 Non-IEEE 1149.1 Operation...........................................................................9-12
Section 10
Applications
10.1 Minimum System Configuration...................................................................1 0-1
10.1.1 Processor Clock Circuitry..........................................................................10-1
MOTOROLA MC68340 USER'S MANUAL xv

Paragraph
Number
10.1.2
10.1.3
10.1.4
10.1.5
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3
10.3.1
10.3.2
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
12.1
12.2
12.2.1
12.2.2
12.3
12.3.1
12.3.2
xvi
TABLE OF CONTENTS (Concluded)
Title
Page
Number
Reset Circuitry.............................................................................................10-3
SRAM Interface ...........................................................................................10-3
ROM Interface..............................................................................................10-4
Serial Interface............................................................................................10-4
Memory Interface Information.......................................................................10-5
Using an 8-Bit Boot ROM...........................................................................10-5
Access Time Calculations.........................................................................10-6
Calculating Frequency-Adjusted Output ................................................10-7
Interfacing an 8-Bit Device to 16-Bit Memory Using
Single-Address DMA Mode..................................................................10-10
Power Consumption Considerations..........................................................10-10
MC68340 Power Reduction at 5V ..........................................................10-11
MC68340V (3.3
V) .....................................................................................10-13
Section 11
Electrical Characteristics
Maximum Rating .............................................................................................11-1
Thermal Characteristics.................................................................................11-1
Power Considerations...................................................................................11-2
AC Electrical Specification Definitions.......................................................11-2
DC Electrical Specifications.........................................................................11-5
AC Electrical Specifications Control Timing..............................................11-6
AC Timing Specifications..............................................................................11-8
DMA Module AC Electrical Specifications.................................................11-19
Timer Module Electrical Specifications......................................................11-20
Serial Module Electrical Specifications......................................................11-22
IEEE 1149.1 Electrical Specifications.........................................................11-25
Section 12
Ordering Information and Mechanical Data
Standard MC68340 Ordering Information .................................................12-1
Pin Assignment...............................................................................................12-2
144-Lead Ceramic Quad Flat Pack (FE Suffix).....................................12-2
145-Lead Plastic Pin Grid Array (RP Suffix) ..........................................12-4
Package Dimensions.....................................................................................12-6
FE Suffix.......................................................................................................12-6
RP Suffix.......................................................................................................12-7
Index
MC68340 USER'S MANUAL MOTOROLA

- - - -. - ~ ~-- - -- ----
LIST OF ILLU:S I HA IIUN::S
Figure
Number
Title
Page
Number
1-1 Block Diagram ......................................................................................................... 1-1
2-1 Functional Signal Groups ..................................................................................... 2-1
3-1 Inpu1 Sample Window ............................................................................................3-2
3-2
MC68340 Interface to Various Port Sizes .......................................................... 3-7
3-3
Long-Word Operand Read Timing from 8-Bit Port ............................................ 3-11
3-4 Long-Word Operand Write Timing to 8-Bit Port .................................................3-12
3-5 Long-Word
and Word Read and Write Timing-16-Bit Port ........................... 3-13
3-6
Fast Termination Timing ........................................................................................ 3-15
3-7
Word Read Cycle Flowchart ................................................................................. 3-16
3-8
Word Write Cycle Flowchart ..................................................................................3-18
3-9 Read-Modify-Write Cycle Timing
......................................................................... 3-19
3-10 CPU Space Address Encoding ............................................................................ 3-21
3-11 Breakpoint Operation Flowchart .......................................................................... 3-24
3-12 Breakpoint Acknowledge
Cycle Timing (Opcode Returned) .......................... 3-25
3-13 Breakpoint Acknowledge Cycle Timing (Exception Signaled)
...................... 3-26
3-14 Interrupt Acknowledge Cycle Flowchart
............................................................. 3-28
3-15 Interrupt Acknowledge
Cycle Timing .................................................................. 3-29
3-16 Autovector Operation Timing
................................................................................ 3-31
3-17 Bus Error without DSACKx .................................................................................... 3-35
3-18
Late Bus Error with DSACKx ................................................................................. 3-36
3-19 Retry Sequence
...................................................................................................... 3-37
3-20 Late Retry Sequence ............................................................................................. 3-38
3-21 HALT Timing ............................................................................................................ 3-39
3-22
Bus Arbitration Flowchart for Single Request .................................................... 3-41
3-23 Bus Arbitration Timing Diagram-Idle Bus Case ..............................................3-42
3-24
Bus Arbitration Timing Diagram-Active Bus Ca.se ......................................... 3-42
3-25
Bus Arbitration State Diagram ..............................................................................3-45
3-26
Show Cycle Timing Diagram ................................................................................3-46
3-27 Timing for External Devices Driving
RESET ...................................................... 3-47
3-28 Power-Up Reset Timing
Diagram ........................................................................ 3-48
4-1 SIM40 Module Register Block .............................................................................. 4-3
4-2
System Configuration and Protection Function ............................................... .4-5
4-3 Software Watchdog Block Diagram .................................................................... 4-7
4-4 Clock Block
Diagram for Crystal Operation ...................................................... .4-10
MOTOROLA
MC68340 USER'S MANUAL xvii

Figure
Number
LIST OF ILLUSTRATIONS (Continued)
Title
Page
Number
4-5 MC68340 Crystal Oscillator ....................... , .......................................................... 4-10
4-6 Clock Block Diagram for External Oscillator Operation .................................. .4-11
4-7 Full Interrupt Request Multiplexer ........................................................................ 4-16
4-8
SIM40 Programming Model. .................................................................................4-19
5-1 CPU32 Block Diagram ...........................................................................................5-3
5-2
Loop Mode Instruction Sequence ....................................................................... 5-3
5-3 User Programming Model
..................................................................................... 5-9
5-4 Supervisor Programming
Model Supplement .................................................. 5-9
5-5 Status Register
........................................................................................................ 5-10
5-6 Instruction Word General Format ......................................................................... 5-12
5-7 Table Example 1
..................................................................................................... 5-30
5-8 Table Example 2 ..................................................................................................... 5-31
5-9 Table Example 3 ..................................................................................................... 5-33
5-1 0 Exception Stack Frame ..........................................................................................5-42
5-11 Reset Operation Flowchart ..... ,..............................................................................5-45
5-12 Format $O-Four-Word Stack
Frame .................................................................. 5-60
5-13 Format $2-Six-Word Stack Frame .................................................................... 5-60
5-14 Internal Transfer Count Register .......................................................................... 5-61
5-15 Format $C-BERR Stack for Prefetches and Operands ..................................5-62
5-16 Format
$C-BERR Stack on MOVEM Operand ................................................ 5-62
5-17 Format
$C-Four- and Six-Word BERRStack .................................................. 5-63
5-18 In-Circuit Emulator Configuration
........................................................................ 5-64
5-19
Bus State Analyzer Configuration ....................................................................... 5-64
5-20 BDM Block Diagram ............................................................................................... 5-65
5-21 BDM Command Execution Flowchart ................................................................. 5-68
5-22
Debug Serial 1/0 Block Diagram ................................... ~ ......................................5-70
5-23 Serial Interface Timing Diagram .......................................................................... 5-71
5-24 BKPT.Timing for Single Bus Cycle ...................................................................... 5-72
5-25
BKPT Timing for Forcing BDM ..............................................................................5-72
5-26
BKPT/DSCLK Logic Diagram ...............................................................................5-72
5-27
Command-Sequence Diagram ...............:............................................................5-75
5-28 Functional
Model of Instruction Pipeline ............................................................ 5-87
5-29 Instruction Pipeline Timing Diagram
................................................................... 5-88
5-30 Block Diagram of Independent Resources ........................................................ 5-90
5-31 Simultaneous Instruction Execution .................................................................... 5-91
5-32 Attributed Instruction Times ...................................................................................5-92
5-33 Example 1-lnstruction Stream
........................................................................... 5-95
5-34 Example
2-Branch Taken ................................................................................... 5-95
5-35
Example 2-Branch Not Taken ............................................................................5-96
5-36 Example
3-Branch Negative Tail ...................................................................... 5-96
xviii
MC68340 USER'S MANUAL
MOTOROLA

LIST OF ILLUSTRATIONS (Continued)
Figure
Number Title
Page
Number
". .. ..... .... "' __ I~ n= __ ... __ e:: ..
U- I ...,.v.,", ...,.""""" ..,'Ql:I'Q ••••••••••••••••••••••••.••••••••••••••••••••••••••••••••••••••••••••••••••••••..•••.•.•••••••••.• _~.
6-2 Single-Address Transfers ..................................................................................... 6-3
6-3
Dual-Address Transfer ...........................................................................................6-3
6-4
DMA External Connections to Serial Module ....................................................6-6
6-5 Single-Address
Read Timing (External Burst) .................................................. 6-8
6-6
Single-Address Read Timing (Cycle Steal) .......................................................6-9
6-7
Single-Address Write Timing (External Burst) ................................................... 6-1 0
6-8 Single-Address Write Timing (Cycle Steal) ....................................................... 6-11
6-9 Dual-Address Read Timing (External Burst-Source Requesting) ...............6-13
6-10 Dual-Address Read Timing (Cycle Steal-Source Requesting) ................... 6-14
6-11 Dual-Address Write Timing (External Burst-Destination Requesting)........6-16
6-12 Dual-Address Write Timing
(Cycle Steal-Destination Requesting) ............ 6-17
6-13
Fast Termination Option (Cycle Steal) ................................................................ 6-21
6-14 Fast Termination Option (External Burst-Source Requesting) .................... 6-22
6-15
DMA Module Programming Model ...................................................................... 6-23
6-16
Packing and Unpacking of Operands ................................................................. 6-35
7-1 Simplified Block Diagram ...................................................................................... 7-1
7-2 External and Internal Interface Signals .............................................................. 7-5
7-3
Baud Rate Generator Block Diagram ..................................................................7-8
7-4 Transmitter
and Receiver Functional Diagram ..................................................7-9
7-5 Transmitter Timing
Diagram ................................................................................. 7-10
7-6 Receiver Timing Diagram ......................................................................................7-12
7
-7 Looping Modes Functional Diagram ...................................................................7-15
7-8 Multidrop
Mode Timing Diagram ......................................................................... 7-16
7-9 Serial Module Programming Model .................................................................... 7-19
7-10 Serial Module Programming Flowchart .............................................................. 7-41
8-1 Simplified Block Diagram ...................................................................................... 8-1
8-2 Timer Functional Diagram .....................................................................................8-3
8-3 External and Internal Interface Signals
.............................................................. 8-5
8-4
Input Capture/Output Compare Mode .................................................................8-7
8-5
Square-Wave Generator Mode ............................................................................8-8
8-6 Variable Duty-Cycle Square-Wave Generator Mode ...................................... 8-1 0
8-7 Variable-Width Single-Shot Pulse Generator Mode ........................................ 8-11
8-8 Pulse-Width Measurement Mode ........................................................................ 8-12
8-9 Period Measurement
Mode .................................................................................. 8-14
8-10 Event Count Mode .................................................................................................. 8-15
8-11 Timer Module Programming ModeL ...................................................................8-18
9-1 Test Access Port Block Diagram .......................................................................... 9-2
9-2
TAP Controller State Machine ..............................................................................9-3
MOTOROLA
MC68340 USER'S MANUAL
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