Motorola MC68340 User manual

MC68340UM/ AD
Rev. 1
INTEGRATED
PROCESSOR
WITHDMA
USER 'S MANUAL
® MOTOROLA

®MOTOROLA
MC68340
Integrated Processor with DMA
User's Manual
MolOroIa reserves the right to make changes without further nolk:e to any products herein to Imprcw reliability, function or deslgh. MolDrola does not assume any
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eMOTOROLA INC" 1992

PREFACE
The complete documentation package for the MC68340 consists of the MC68340UM/AD,
MC68340 Integrated Processor with DMA User's Manual, M68000PM/AD, MC68000
Family Programmer's Reference Manual, and the MC68340P/D, MC68340 Integrated
Processorwith DMA Product Brief.
The MC68340 Integrated with DMA Processor User's Manual describes the programming,
capabilities, registers, and operation of the MC68340; the MC68000 Family Programmer's
Reference Manual provides instruction details for the MC68340; and the
MC68340
Integrated Processor with DMA Product Briefprovides a brief description of the MC68340
capabilities.
This user's manual is organized as follows:
Section 1
Section 2
Section 3
Section 4
Section 5
Section 6
Section 7
Device Overview Section 8
Signal Descriptions Section 9
Bus Operation
System Integration Module Section 10
CPU32 Section
11
DMA Controller Module Section 12
Serial Module
6SK FAX-IT
FAX [phone]
Timer Modules
IEEE 1149.1 Test Access
Port
Applications
Electrical Characteristics
Ordering Information and
Mechanical Data
The Motorola High-End Technical Publication Department provides a FAX number for you
to submit any questions and comments about this document.
We welcome your
suggestions for improving ourdocumentation orany questions concerning our products.
Please provide the part number and revision number (located in upper right-hand corner
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TABLE OF CONTENTS
Paragraph
Number Title
Page
Number
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.1.7
1.3.2
1.3.3
1.3.4
1.4
1.5
1.6
1.7
Section 1
Device Overview
M68300 Family ..................................................................................................1-2
Organization ..................................................................................................1-3
Advantages....................................................................................................1-3
Central Processor Unit .....................................................................................1-3
CPU32 ............................................................................................................1-4
Background Debug Mode...........................................................................1-4
On-Chip Peripherals........................................................................................1-5
System Integration Module.........................................................................1-5
External Bus Interface..............................................................................1-5
System Configuration and Protection...................................................1-6
Clock Synthesizer.....................................................................................1-6
Chip Select and Wait State Generation...............................................1-6
Interrupt Handling.....................................................................................1-6
Discrete 1/0 Pins ........................................................................................1-6
IEEE 1149.1 Test Access Port................................................................1-7
Direct Memory Access Module ...................................................................1-7
Serial Module................................................................................................1-7
Timer Modules ...............................................................................................1-8
Power Consumption Management................................................................1-8
Physical ..............................................................................................................1-9
Compact Disc-Interactive ................................................................................1-9
More Information............................................................................................... 1-1 0
Section 2
Signal Descriptions
2.1 Signal Index.......................................................................................................2-2
2.2 Address Bus .......................................................................................................2-4
2.2.1 Address Bus (A23-AO)................................................................................2-4
2.2.2 Address Bus (A31-A24)..............................................................................2-4
2.3 Data Bus (015-00) ..........................................................................................2-4
2.4 Function Codes (FC3-FCO) ............................................................................2-5
2.5 Chip Selects (CS3-CSO).................................................................................2-5
2.6 Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3)......................................2-6
MOTOROLA MC68340 USER'S MANUAL
iii

Paragraph
Number
TABLE OF CONTENTS (Continued)
Title
Page
Number
2.7 Bus Control Signals ......................................................................................... 2-6
2.7.1 Data and Size Acknowledge (DSACK1, DSACKO) ................................. 2-6
2.7.2 Address Strobe
(AS) .................................................................................... 2-6
2.7.3
Data Strobe (OS) ...........................................................................................2-7
2.7.4 Transfer
Size (SIZ1, SIZO) .......................................................................... 2-7
2.7.5
ReadWrite (RIW) ...........................................................................................2-7
2.8
Bus Arbitration Signals .................................................................................... 2-7
2.8.1 Bus Request (BR) ..........................................................................................2-7
2.8.2
Bus Grant (BG) .............................................................................................. 2-7
2.8.3
Bus Grant Acknowledge (BGACK) .............................................................2-7
2.8.4 Read-Modify-Write
Cycle (RMC) ................................................................ 2-8
2.9 Exception Control Signals
.............................................................................. 2-8
2.9.1 Reset (RESET) ...............................................................................................2-8
2.9.2
Halt (HAL T) .....................................................................................................2-8
2.9.3
Bus Error (BERR) .......................................................................................... 2-8
2.10 Clock Signals .................................................................................................... 2-8
2.10.1 System Clock (CLKOUT) ............................................................................2-8
2.10.2 Crystal Oscillator (EXTAL, XTAL) ...............................................................2-9
2.10.3 External Filter Capacitor (XFC) .................................................................. 2-9
2.10.4 Clock Mode Select (MODCK) .....................................................................2-9
2.11 Instrumentation and Emulation Signals ................................ , ...................... 2-9
2.11.1 Instruction Fetch (IFETCH) ...........................................................................2-9
2.11.2 Instruction
Pipe (I PIPE) ................................................................................ 2-9
2.11.3 Breakpoint
(BKPT) ........................................................................................ 2-10
2.11.4 Freeze (FREEZE) .......................................................................................... 2-1 0
2.12 DMA Module Signals ....................................................................................... 2-10
2.12.1 DMA Request (DREQ2, DREQ1) ................................................................ 2-10
2.12.2 DMA Acknowledge (DACK2, DACK1) ....................................................... 2-1 0
2.12.3 DMA Done (DONE2, DONE1) ..................................................................... 2-10
2.13 Serial Module Signals ..................................................................................... 2-11
2.13.1 Serial Crystal Oscillator (X2, X1) ............................................................... 2-11
2.13.2 Serial External Clock Input (SCLK) ........................................................... 2-11
2.13.3 Receive Data (RxDA, RxDB) ....................................................................... 2-11
2.13.4 Transmit Data (TxDA, TxDB) ....................................................................... 2-11
2.13.5 Clearto Send (CTSA, CTSB) ...................................................................... 2-11
2.13.6 Request to Send (R'fSA, R'f'SB)................................................................. 2-11
2.13.7 Transmitter Ready (TxRDYA) ...................................................................... 2-11
2.13.8 Receiver Ready (RxRDYA) .......................................................................... 2-12
2.14 Timer Signals
.................................................................................................... 2-12
2.14.1 Timer Gate (TGATE2, TGATE1) ................................................................. 2-12
2.14.2 Timer Input
(TIN2, TIN 1) .............................................................................. 2-12
2.14.3
Timer Output (TOUT2, TOUT1 )...................................................................2-12
iv MC68340 USER'S MANUAL
MOTOROLA

Paragraph
Number
TABLE OF CONTENTS (Continued)
Title
Page
Number
2.15 Test Signals.......................................................................................................2-13
2.15.1 Test Clock (TCK)...........................................................................................2-13
2.15.2 Test Mode Select (TMS)..............................................................................2-13
2.15.3 Test Data
In (TO I) ..........................................................................................2-13
2.15.4 Test DataOut (TOO).....................................................................................2-13
2.16 SynthesizerPower
(VCCSYN) ..........................................................................2-13
2.17 System Powerand Ground (Vee and GNO)................................................2-13
2.18 Signal Summary...............................................................................................2-13
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.7.1
3.1.7.2
3.1.7.3
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.2.3.6
3.2.3.7
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
MOTOROLA
Section 3
Bus Operation
Bus TransferSignals........................................................................................ 3-1
Bus Control Signals.....................................................................................3-2
Function Code Signals................................................................................3-3
Address Bus (A31-AO) ................................................................................3-4
Address Strobe (AS) ....................................................................................3-4
Data Bus
(015-00) ......................................................................................3-4
Data Strobe (OS) ...........................................................................................3-4
Bus Cycle Termination Signals..................................................................3-4
Data Transfer and Size Acknowledge Signals
(OSACK1 and OSACKO) ......................................................................3-4
Bus Error (BERR) ......................................................................................3-5
Autovector (AVEC)....................................................................................3-5
Data Transfer Mechanism...............................................................................3-5
Dynamic Bus Sizing.....................................................................................3-5
Misaligned Operands...................................................................................3-7
Operand Transfer Cases.............................................................................3-7
Byte Operand to 8-Bit Port, Odd
or Even (AO =X) ..............................3-7
Byte Operand to 16-Bit Port, Even
(AO = 0)..........................................3-8
Byte Operand to 16-Bit Port, Odd (AO = 1)...........................................3-9
Word Operand to 8-Bit Port, Aligned.....................................................3-9
Word Operand to 16-Bit Port, Aligned...................................................3-10
Long-word Operand to 8-Bit Port, Aligned...........................................3-10
Long-Word Operand to 16-Bit Port, Aligned........................................3-12
Bus Operation................................................................................................3-14
Synchronous Operation with
OSACKx ......................................................3-14
Fast Termination Cycles...............................................................................3-15
Data Transfer Cycles........................................................................................3-16
Read Cycle.....................................................................................................3-16
Write Cycle.....................................................................................................
3-18
Read-Modify-Write Cycle.............................................................................3-19
MC68340 USER'S MANUAL v

Paragraph
Number
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.4.3
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
4.1
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.2.6.1
4.2.2.6.2
4.2.2.7
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.4
4.2.4.1
vi
TABLE OF CONTENTS (Continued)
Title
Page
Number
CPU Space Cycles...........................................................................................3-21
Breakpoint Acknowledge Cycle.................................................................3-22
LPSTOP Broadcast Cycle...........................................................................3-23
Module Base Address Register Access....................................................3-27
Interrupt Acknowledge Bus Cycles............................................................3-27
Interrupt Acknowledge Cycle-Terminated Normally........................3-27
Autovector Interrupt Acknowledge Cycle.............................................3-29
Spurious Interrupt Cycle..........................................................................3-30
Bus Exception Control Cycles........................................................................3-32
Bus Errors.......................................................................................................3-34
Retry Operation .............................................................................................3-36
Halt Operation ...............................................................................................3-38
Double Bus Fault ..........................................................................................3-39
Bus Arbitration...................................................................................................
3-40
Bus Request...................................................................................................3-43
Bus Grant........................................................................................................3-43
Bus Grant Acknowledge..............................................................................3-43
Bus Arbitration Control.................................................................................3-44
Show Cycles..................................................................................................3-44
Reset Operation ................................................................................................3-46
Section 4
System Integration Module
Module Overview.............................................................................................. 4-1
Module Operation.............................................................................................4-2
Module Base Address Register Operation...............................................4-2
System Configuration and Protection Operation....................................4-3
System Configuration ..............................................................................4-5
Internal Bus Monitor.................................................................................4-6
Double Bus Fault Monitor........................................................................4-6
Spurious Interrupt Monitor......................................................................4-6
Software Watchdog..................................................................................4-6
Periodic Interrupt Timer...........................................................................4-7
Periodic Timer Period Calculation.....................................................4-8
Using the Periodic Timer as a Real-Time Clock.............................4-9
Simultaneous Interrupts by Sources in the SIM40.............................4-9
Clock Synthesizer Operation......................................................................4-9
Phase Comparator and Filter.................................................................4-11
Frequency Divider....................................................................................4-12
Clock Control.............................................................................................4-13
Chip Select Operation .................................................................................4-13
Programmable Features..........................................................................4-14
MC68340 USER'S MANUAL MOTOROLA

Paragraph
Number
4.2.4.2
4.2.5
4.2.5.1
4.2.5.2
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.3.3
4.3.4
4.3.4.1
4.3.4.2
4.3
.. 4.3
4.3.5
4.3.5.1
4.3.5.2
4.3.5.3
4.3.5.4
4.3.5.5
4.3.5.6
4.3.5.7
4.4
4.4.1
4.4.2
4.4.3
TABLE OF CONTENTS (Continued)
Title
Page
Number
Global Chip Select Operation ................................................................4-14
External Bus Interface Operation...............................................................4-15
PortA...........................................................................................................4-15
Port B...........................................................................................................4-16
Low-Power Stop...........................................................................................4-17
Freeze.............................................................................................................4-17
Programming ModeL.......................................................................................4-18
Module Base Address Register (MBAR)...................................................4-20
System Configuration and Protection Registers.....................................4-21
Module Configuration Register (MCR)..................................................4-21
Autovector Register (AVR).......................................................................4-23
Reset Status Register (RSR)...................................................................4-23
Software Interrupt Vector Register (SWIV)...........................................4-24
System Protection Control Register (SYPCR).....................................4-24
Periodic Interrupt Control Register (PICR) ...........................................4-26
Periodic Interrupt Timer Register (PITR)...............................................4-27
Software Service Register (SWSR) ......................................................4-28
Clock Synthesizer Control Register (SYNCR) ........................................4-28
Chip Select Registers...................................................................•..............4-29
Base Address Registers ..........................................................................4-30
Address Mask Registers..........................................................................4-31
Chip Select Registers Programming Example....................................4-33
External Bus Interface ControL...................................................................4-33
Port A Pin Assignment Register 1 (PPARA1).......................................4-33
Port A Pin Assignment Register 2 (PPARA2).......................................4-34
Port A Data Direction Register (DORA).................................................4-34
Port A Data Register (PORTA)................................................................4-34
Port B Pin Assignment Register (PPARB) ............................................4-35
Port B Data Direction Register (DDRB).................................................4-35
Port B Data Register (pORTB, PORTB1) ..............................................4-35
MC68340 Initialization Sequence.................................................................4-36
Startup............................................................................................................4-36
SIM40 Module Configuration .....................................................................4-36
SIM40 Example Configuration Code........................................................4-38
Section 5
CPU32
5.1 Overview............................................................................................................. 5-1
5.1.1 Features.......................................................................................................;;.5-2
5.1.2 Virtual Memory..............................................................................................5-2
5.1.3 Loop Mode Instruction Execution .....................................:........................5-3
MOTOROLA
MC68340 USER'S MANUAL
vii

Paragraph
Number
5.1.4
5.1.5
5.1.6
5.1.7
5.1.7.1
5.1.7.2
5.1.8
5.1.9
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.1.1
5.3.1.1.1
5.3.1.1.2
5.3.1.2
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.3.3.5
5.3.3.6
5.3.3.7
5.3.3.8
5.3.3.9
5.3.3.10
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.4.5
5.3.5
5.3.6
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
viii
TABLE OF CONTENTS (Continued)
Title
Page
Number
Vector Base Register.................................................................................... 5-4
Exception Handling...................................................................................... 5-4
Addressing Modes........................................................................................ 5-5
Instruction Set. ............................................................................................... 5-5
Table lookup and Interpolate Instructions........................................... 5-7
low-Power STOP Instruction................................................................. 5-7
Processing States......................................................................................... 5-7
Privilege States............................................................................................. 5-7
Architecture Summary..................................................................................... 5-8
Programming Model..................................................................................... 5-8
Registers......................................................................................................... 5-1 0
Instruction Set....................................................................................................5-11
M68000 Family Compatibility.....................................................................5-11
New Instructions........................................................................................5-11
Low-Power Stop (lPSTOP)................................................................5-11
Table lookup and Interpolation (TBl) ..............................................5-12
Unimplemented Instructions...................................................................5-12
Instruction Format and Notation.................................................................5-12
Instruction Summary....................................................................................5-15
Condition Code Register.........................................................................5-20
Data Movement Instructions...................................................................5-21
Integer Arithmetic Operations.................................................................5-22
logic Instructions......................................................................................5-24
Shift and Rotate Instructions...................................................................5-24
Bit Manipulation Instructions...................................................................5-25
Binary-Coded Decimal (BCD) Instructions..........................................5-26
Program Control Instructions..................................................................5-26
System Controllnstructions....................................................................5-27
Condition Tests.........................................................................................5-29
Using the TBl Instructions..........................................................................5-29
Table Example 1: Standard Usage.......................................................5-30
Table Example 2: Compressed Table ..................................................5-31
Table Example 3: 8-Bit Independent Variable....................................5-32
Table Example 4: Maintaining Precision..............................................5-34
Table Example 5: Surface Interpolations.............................................5-36
Nested Subroutine Calls.............................................................................5-36
Pipeline Synchronization with the NOP Instruction................................5-36
Processing States.............................................................................................5-36
State Transitions...........................................................................................5-37
Privilege levels .............................................................................................5-37
Supervisor Privilege leveL.....................................................................5-37
User Privilege level .................................................................................5-39
MC68340 USER'S MANUAL MOTOROLA

Paragraph
Number
5.4.2.3
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.2.4
5.5.2.5
5.5.2.6
5.5.2.7
5.5.2.8
5.5.2.9
5.5.2.10
5.5.2.11
5.5.2.12
5.5.3
5.5.3.1
5.5.3.1.1
5.5.3.1.2
5.5.3.1.3
5.5.3.1.4
5.5.3.2
5.5.3.2.1
5.5.3.2.2
5.5.3.2.3
5.5.3.2.4
5.5.3.2.5
5.5.3.2.6
5.5.3.2.7
5.5.4
5.5.4.1
5.5.4.2
5.5.4.3
5.6
5.6.1
5.6.1.1
5.6.1.2
MOTOROLA
TABLE OF CONTENTS (Continued)
Title Page
Number
Changing Privilege Level ........................................................................5-39
Exception
Processing ...................................................................................... 5-39
Exception Vectors ......................................................................................... 5-40
Types of Exceptions ................................................................................. 5-41
Exception Processing Sequence .......................................................... 5-41
Exception Stack Frame ............................................................................ 5-42
Multiple Exceptions .................................................................................. 5-42
Processing of Specific Exceptions ............................................................ 5-44
Reset ........................................................................................................... 5-44
Bus Error ..................................................................................................... 5-46
Address Error ............................................................................................. 5-46
Instruction Traps ........................................ ~ ............................................... 5-47
Software BreakpOints ............................................................................... 5-47
Hardware Breakpoints ............................................................................. 5-48
Format Error ............................................................................................... 5-48
Illegal or Unimplemented Instructions .................................................. 5-48
Privilege Violations ................................................................................... 5-49
Tracing
........................................................................................................ 5-50
Interrupts ..................................................................................................... 5-51
Retum from Exception .............................................................................. 5-52
Fault Recovery ............................................................................................... 5-53
Types of Faults .......................................................................................... 5-55
Type I-Released Write Faults ........................................................... 5-55
Type II-Prefetch, Operand, RMW, and MOVEP Faults .................5-56
Type III-Faults During MOVEM Operand Transfer ....................... 5-57
Type IV-Faults During Exception Processing ............................... 5-57
Correcting a Fault .................................................. , .................................. 5-57
Type !-Completing Released Writes via Software ....................... 5-57
Type I-Completing Released Writes via RTE ................................ 5-57
Type II-Correcting Faults via RTE ....................................................5-58
Type III-Correcting Faults via Software .......................................... 5-58
Type III-Correcting Faults by Conversion and Restart .................5-58
Type III-Correcting Faults via RTE ...................................................5-59
Type IV-Correcting Faults via Software ......................................... 5-59
CPU32 Stack Frames .................................................................................. 5-60
Four-Word Stack Frame .......................................................................... 5-60
Six-Word Stack Frame ............................................................................. 5-60·
Bus Error Stack Frame ............................................................................. 5-60
Development Support ...................................................................................... 5-63
CPU32 Integrated Development Support ................................................ 5-63
Background Debug Mode (BDM) Overview ........................................ 5-64
Deterministic
Opcode Tracking Overview ............................................ 5-64
MC68340 USER'S MANUAL Ix