N.A.T. MAMC-XLINK Product manual

Meikon
MAMC-XLINK – Technical Reference Manual
MAMC-XLINK
Technical Reference Manual V1.1
HW Revision 1. , 1.1

Meikon
MAMC-XLINK – Technical Reference Manual
The MAMC-XLINK has been designed by:
Meikon Ltd
1 Bringsty Common
Worcester
WR6 5UJ
Great Britain
Phone [phone]
Internet: http:// www.meikon.net
and
N.A.T. GmbH
Kamillenweg 22
53757 Sankt Augustin
Germany
Phone: [phone]-
Fax: [phone]
E-Mail: [email protected]
Internet: http://www.nateurope.com

Meikon
MAMC-XLINK – Technical Reference Manual
Disclaimer
The following documentation, compiled by Meikon Ltd. and N.A.T. GmbH (henceforth
called Meikon and N.A.T. , represents the current status of the product´s development. The
documentation is updated on a regular basis. Any changes which might ensue, including those
necessitated by updated specifications, are considered in the latest version of this
documentation. Meikon and N.A.T. are under no obligation to notify any person,
organization, or institution of such changes or to make these changes public in any other way.
Caution this publication may include technical inaccuracies or typographical errors.
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Note:
The release of the Hardware Manual is related
to a particular HW board revision given in the
document title. For earlier hardware revisions
please contact Meikon or N.A.T. for the relevant
Hardware Manual release.

Meikon
MAMC-XLINK – Technical Reference Manual
Table of Contents
LIST OF TABLES ................................................................................................................................................. 5
LIST OF FIGURES ............................................................................................................................................... 5
CONVENTIONS .................................................................................................................................................... 6
1 INTRODUCTION ............................................................................................................................................... 7
1.1 INSTALLATION .................................................................................................................................................... 8
1.2 BLOCK DIAGRAM ................................................................................................................................................ 9
1.3 BOARD FEATURES ............................................................................................................................................. 10
1.4 BOARD SPECIFICATION ....................................................................................................................................... 11
2 INSTALLATION ............................................................................................................................................... 12
2.1 SAFETY NOTE .................................................................................................................................................. 12
2.2 INSTALLATION PREREQUISITES AND REQUIREMENTS ................................................................................................ 13
2.3 STATEMENT ON ENVIRONMENTAL PROTECTION ...................................................................................................... 14
2.4 LOCATION OVERVIEW ........................................................................................................................................ 16
3 FUNCTIONAL BLOCKS ................................................................................................................................ 17
3.1 RE-DRIVER CIRCUITRY ...................................................................................................................................... 17
3.2 IPMI CONTROLLER .......................................................................................................................................... 17
3.3 IPMB INTERFACE ............................................................................................................................................ 17
3.4 AMC CLOCK INTERFACE .................................................................................................................................. 18
3.5 CABLE INTERFACE CONTROL SIGNALS ................................................................................................................. 18
4 HARDWARE DESCRIPTION ......................................................................................................................... 19
4.1 AMC PORT DEFINITION .................................................................................................................................... 19
4.2 DEFINITION OF ATMEGA645 PORT PINS .............................................................................................................. 20
4.3 FRONT PANEL LEDS ........................................................................................................................................ 22
5 CONNECTORS AND SWITCHES .................................................................................................................. 23
5.1 CONNECTOR OVERVIEW ..................................................................................................................................... 23
5.2 AMC CONNECTOR CON1 ............................................................................................................................... 24
5.3 FRONT PANEL CONNECTOR CON2 .................................................................................................................... 26
5.4 AVR PROGRAMMING PORT CONNECTOR JP1 ..................................................................................................... 26
5.5 HOT SWAP SWITCH SW1 .................................................................................................................................. 26
5.6 DIL SWITCH SW2 ........................................................................................................................................... 27
5.7 DIL SWITCH SW3 ........................................................................................................................................... 27
6 MAMC-XLINK PROGRAMMING NOTES .................................................................................................. 28
6.1 AMC CONTROL SIGNALS ................................................................................................................................. 28
6.2 SELECTING THE PCIE CLOCK SOURCE ................................................................................................................ 28
6.3 PCI EXPRESS EXTERNAL CABLE INTERFACE CONTROL SIGNALS ............................................................................ 28
6.4 PROGRAMMING THE RE-DRIVER DEVICE STRAPPING PINS ...................................................................................... 29
6.5 SETUP OF THE SERIAL INTERFACES ...................................................................................................................... 30
7 KNOWN BUGS / RESTRICTIONS ................................................................................................................. 31
APPENDIX A: REFERENCE DOCUMENTATION ...................................................................................... 32
APPENDIX B: DOCUMENT’S HISTORY ...................................................................................................... 33

Meikon
MAMC-XLINK – Technical Reference Manual
List of Tables
TABLE 1: LIST OF USED ABBREVIATIONS .................................................................................................. 6
TABLE 2: MAMC-XLINK FEATURES ............................................................................................................ 11
TABLE 3: AMC PORT DEFINITION ............................................................................................................... 19
TABLE 4: ATMEGA645 PORT PIN USAGE (PORT A) ................................................................................. 2
TABLE 5: ATMEGA645 PORT PIN USAGE (PORT B) ................................................................................. 2
TABLE 6: ATMEGA645 PORT PIN USAGE (PORT C) ................................................................................. 2
TABLE 7: ATMEGA645 PORT PIN USAGE (PORT D) ................................................................................. 21
TABLE 8: ATMEGA645 PORT PIN USAGE (PORT E) ................................................................................. 21
TABLE 9: ATMEGA645 PORT PIN USAGE (PORT F) ................................................................................. 21
TABLE 1 : ATMEGA645 PORT PIN USAGE (PORT G) .............................................................................. 22
TABLE 11: AMC CONNECTOR CON1 ............................................................................................................ 24
TABLE 12: PIN ASSIGNMENT OF THE FRONT PANEL CONNECTOR CON2 ..................................... 26
TABLE 13: ATMEGA645 PROGRAMMING PORT JP1 ............................................................................... 26
TABLE 14: SWITCH ASSIGNMENT OF DIL SWITCH SW2 ...................................................................... 27
TABLE 15: SWITCH ASSIGNMENT OF DIL SWITCH SW3 ...................................................................... 27
TABLE 16: RE-DRIVER STRAPPING PINS SEL – 2, EQUALIZER SELECTION ................................ 29
TABLE 17: RE-DRIVER STRAPPING PINS SEL3 – 4, OUTPUT SWING CONTROL ............................ 29
TABLE 18: RE-DRIVER STRAPPING PINS SEL5 – 6, OUTPUT DE-EMPHASIS ADJUSTMENT ....... 29
List of Figures
FIGURE 1:MAMC-XLINK ON A CARRIER BOARD (ATCA) ...................................................................... 8
FIGURE 2:MAMC-XLINK BLOCK DIAGRAM ............................................................................................... 9
FIGURE 3:LOCATION DIAGRAM OF THE MAMC-XLINK ..................................................................... 16
FIGURE 4:CONNECTORS OF THE MAMC-XLINK .................................................................................... 23

Meikon
MAMC-XLINK – Technical Reference Manual
Conventions
If not otherwise specified, addresses and memory maps are written in hexadecimal notation,
identified by 0x.
Table 1 gives a list of the abbreviations used in this document:
Table 1: List of used Abbreviations
Abbreviation Description
AMC Advanced Mezzanine Card
ATCA Advanced Telecommunications Computing Architecture
b Bit, binary
B byte
IPMI Intelligent Platform Management Interface Specification
MCH µTCA Carrier Hub
µTCA Micro Telecommunications Computing Architecture
nc not connected
PCI Peripheral Component Interconnect
PCIe PCI Express
PICMG PCI Industrial Computer Manufacturers Group

Meikon
MAMC-XLINK – Technical Reference Manual
1 Introduction
The MAMC-XLINK is a high performance standard Advanced Mezzanine Card, single
width, full height. It can be plugged onto any ATCA carrier board supporting AMC
standards. It is also designed to meet the requirements of µTCA systems.
The MAMC-XLINK connects one lane of a PCIe backplane through a programmable
Re-Driver circuitry to a PCI Express External Cable Interface Connector on the front
panel.
The MAMC-XLINK is member of a family of XLINK boards which enable the
connection of different system platforms via a PCI Express External Cable Interface.
Typically one system will be a master system containing a processor card and the second
system will be a slave system which does not contain a processor card and is controlled
by the master system. Examples of other XLINK products are the MPCI-XLINK and the
MPCIe-XLINK.

Meikon
MAMC-XLINK – Technical Reference Manual
1.1 Installation
The MAMC-XLINK can be installed either on a carrier board or plugged into a µTCA
system.
Figure 1: MAMC-XLINK on a Carrier Board (ATCA)
Backplane Connectors
MAMC-XLINK
(Back View
NAMC-8560-8E1/T1/J1
(Back View
The MAMC-XLINK provides master functionality for the cable interface, i.e. provides
clock and management signals. When connecting it to another XLINK board, please
make sure that the other board does not have master functionality for the cable interface.
The other board will be in a slave system. This slave system should be powerd up before
the system containing the MAMC-XLINK to ensure that the AMC system finds the
slave rack when it powers up.

Meikon
MAMC-XLINK – Technical Reference Manual
1.2 Block Diagram
The MAMC-XLINK has the following major features implemented on-board:
•1 Lane PCI Express Interface Rev. 1.1 to backplane
•1 Lane PCI Express External Cable Interface Rev. 1.0 to front panel
•Re-Driver circuitry for boost and reshaping of the PCIe signals
•IPMI Controller
Figure 2: MAMC-XLINK Block Diagram
PCIe ReDriver
PI2EQX4402D
PCIe x 1
uTCA Backplane
PCIe x 1
PCIe Cable
MAMC-X INK
IPMI Controller,
Temp. Sensor,
Control
Power Supplies,
Clock generation,
Hot Swap

Meikon
MAMC-XLINK – Technical Reference Manual
1.3 Board Features
•PCI Express Interface
The MAMC-XLINK includes a 1 – lane PCI Express interface. The PCI Express inter-
face connects to Port 4 of the Fat Pipe Region of the AMC backplane connector. The
implementation of PCIe conforms to the AMC.1 specification.
•PCI Express External Cable Interface
The MAMC-XLINK includes a 1 – lane PCI Express External Cable Interface. The
PCI Express External Cable Interface connects to a special PCI Express External Cable
connector. The implementation of PCI Express External Cable Interface conforms to the
PCI Express External Cabling Specification, Rev. 1.0.
•IPMI Controller
The MAMC-XLINK implements an IPMB interface which conforms to the AMC.0
specification. The IPMI firmware complies to the IPMI – Intelligent Platform
Management Interface Specification, v1.5., Revision 1.1.
•Re-Driver Circuitry
The MAMC-XLINK includes Re-Driver circuitry, in order to guarantee PCIe signal
quality at the receiver portion of the PCI Express External Cable Interface.
•Clock Selection
The MAMC-XLINK offers the choice to select between a local PCIe clock and the
backplane clock FCLKA, which is defined in the AMC.0 specification.