National Instruments 6583R User manual

NI 6583R User Guide and Specifications
The NI 6583R is a single-ended and differential signaling device designed to work in conjunction with
your NI FlexRIO™FPGA module. The NI 6583 is available in two versions: one with low-voltage
differential signals (LVDS) and another with multipoint low-voltage differential signals (MLVDS). The
term, differential, in this document refers to both LVDS and MLVDS signals unless otherwise specified.
This document contains signal information and specifications for the NI 6583R, which is composed of
an NI FlexRIO FPGA module and the NI 6583. This document also contains tutorial sections that
demonstrate how to acquire data using a LabVIEW FPGA example VI and how to create and run your
own LabVIEW project with the NI 6583R.
Contents
How to Use Your NI FlexRIO Documentation Set ............................................................................. 3
Front Panel and Connector Pinouts ..................................................................................................... 4
Pin and Signal Tables .......................................................................................................................... 5
Block Diagrams ................................................................................................................................... 7
Connecting Cables and Accessories .................................................................................................... 12
Using Accessories................................................................................................................................ 12
Using Your NI 6583R with a LabVIEW FPGA Example VI.............................................................. 17
Creating a LabVIEW Project and Running a VI on an FPGA Target ................................................. 19
NI 6583 Component-Level Intellectual Property (CLIP) .................................................................... 23
Specifications....................................................................................................................................... 25
Compliance and Certifications............................................................................................................. 29
Where to Go for Support ..................................................................................................................... 30

NI 6583R User Guide and Specifications 2 ni.com
Note Before configuring your NI 6583R, you must install the appropriate software and hardware.
Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation
instructions. Figure 1 shows an example of a properly connected NI FlexRIO device.
Figure 1. NI 6583R
Note NI 6583R refers to the combination of your NI 6583 adapter module and your NI FlexRIO
FPGA module. NI 6583 refers only to your NI 6583 adapter module.
NI 6583 + NI FlexRIO FPGA Module = NI 6583R
NI 6583 NI 6583

©National Instruments Corporation 3 NI 6583R User Guide and Specifications
How to Use Your NI FlexRIO Documentation Set
Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set.
Figure 2. How to Use Your NI FlexRIO Documentation Set
Table 1. NI FlexRIO Documentation Locations and Descriptions
Document Location Description
NI FlexRIO FPGA
Module Installation
Guide and Specifications*
Available in your FPGA module
hardware kit and from the Start Menu.
Contains installation instructions for your
NI FlexRIO system and specifications for your
FPGA module.
NI Adapter Module User
Guide and Specifications*
Available in your adapter module
hardware kit and from the Start Menu.
Contains signal information, examples, and
specifications for your adapter module.
LabVIEW FPGA Module
Help*
Embedded in LabVIEW Help.Contains information about the basic functionality of
LabVIEW FPGA Module.
NI FlexRIO Help*Embedded in LabVIEW FPGA
Module Help.
Contains FPGA module, adapter module, and CLIP
configuration information.
LabVIEW Examples Available in NI Example Finder. Contains examples of how to run FPGA VIs and
Host VIs on your device.
Other useful information on ni.com
ni.com/ipnet Contains LabVIEW FPGA functions and intellectual property to share.
ni.com/flexrio Contains product information and data sheets for NI FlexRIO devices.
* These documents are also available at ni.com/manuals.
LabVIEW FPGA
Module Help
NI FlexRIO
Help
LabVIEW
Examples
INSTALL Hardware
and Software
CONNECT Signals
and Learn About
Your Adapter
Module
LEARN About
LabVIEW FPGA
Module
PROGRAM Your
NI FlexRIO System
in LabVIEW FPGA
Module
NI FlexRIO FPGA Module
Installation Guide and Specifications
NI FlexRIO Adapter Module
User Guide and Specifications
Are
You New to
LabVIEW FPGA
Module?
Yes No
No

NI 6583R User Guide and Specifications 4 ni.com
Front Panel and Connector Pinouts
Figure 3 shows the digital data and control (DDC) connector pin assignments for the NI 6583. DDC A
contains the single-ended lines and DDC B contains the differential lines.
Figure 3. NI 6583 Connector Pin Assignments
Caution Connections that exceed any of the maximum ratings of input or output signals on the
NI 6583R can damage the device and the chassis. NI is not liable for any damage resulting from such
signal connections. For the maximum input and output ratings for each signal, refer to the
Specifications section of this document.
Digital Data and Control B (DDC B)
LVDS
NI 6583
GND
PFI 1+
GND
PFI 2+
GND
PFI 3+
GND
GND
DIO 0+
GND
DIO 1+
GND
DIO 2+
GND
DIO 3+
GND
DIO 4+
GND
DIO 5+
GND
DIO 6+
GND
DIO 7+
GND
DIO 8+
GND
DIO 9+
GND
DIO 10+
GND
DIO 11+
GND
DIO 12+
GND
DIO 13+
GND
DIO 14+
GND
DIO 15+
GND
GND
GND
GND
GND
PFI 1–
PFI 2–
PFI 3– / GND
DIO 0–
DIO 1–
DIO 2–
DIO 3–
DIO 4–
DIO 5–
DIO 6–
DIO 7–
DIO 8–
DIO 9–
DIO 10–
DIO 11–
DIO 12–
DIO 13–
DIO 14–
DIO 15–
1
3
2
4
6
5
7
98
10
12
11
13
15
14
16
18
17
19
21
20
22
24
23
25
27
26
28
30
29
31
3332
34
36
35
37
39
38
40
42
41
43
4544
46
48
47
49
51
50
52
54
53
55
57
56
58
6059
61
63
62
64
66
65
67
6968
70
72
71
73
RESERVED
RESERVED
DDC CLK OUT–
DDC CLK OUT+
RESERVED
RESERVED
STROBE–
STROBE+
RESERVED
RESERVED
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
DDC CLK OUT
GND
DIO 1
PFI 3
DIO 3
GND
DIO 5
PFI 1
DIO 7
GND
DIO 9
GND
DIO 11
GND
DIO 13
GND
DIO 15
GND
DIO 17
GND
DIO 19
GND
DIO 21
GND
DIO 23
RESERVED
DIO 25
GND
DIO 27
GND
DIO 29
GND
DIO 31
GND
STROBE
GND
DIO 0
PFI 2
DIO 2
GND
DIO 4
RESERVED
DIO 6
GND
DIO 8
GND
DIO 10
GND
DIO 12
RESERVED
DIO 14
GND
DIO 16
GND
DIO 18
GND
DIO 20
GND
DIO 22
GND
DIO 24
GND
DIO 26
GND
DIO 28
GND
DIO 30
Digital Data and Control A (DDC A)
Single-ended

©National Instruments Corporation 5 NI 6583R User Guide and Specifications
Note If you design a custom cabling solution with the DDC B differential connector (779157-01)
and NI SHB12X-B12X cable (192344-01), the NI 6583 pinout is reversed at the end connector.
For example, the signal shown on pin 1 shown in Figure 3 maps to pin 73 at the end connector.
Pin and Signal Tables
Table 2 contains pin location and single-ended signal information for DDC A on the NI 6583.
Table 2. NI 6583 DDC A Connector Pins
Signal Name Pin(s) Signal Type Signal Description
DDC CLK OUT 33 Clock Terminal for the single-ended exported Sample clock.
STROBE 67 Clock External Sample clock source that can be used for source
synchronous acquisition.
DIO <0..31> 1, 3, 5, 7, 9, 11, 13, 15,
17, 19, 21, 23, 25, 27,
29, 31, 35, 37, 39, 41,
43, 45, 47, 49, 51, 53,
55, 57, 59, 61, 63, 65
Data Bidirectional single-ended digital I/O data channels
0 through 31.
PFI <1..3> 26, 30, 64 Control/Data Bidirectional single-ended digital I/O trigger channels
1 through 3.
GND 2, 4, 6, 10, 12, 14, 16,
18, 20, 22, 24, 28, 32,
34, 36, 38, 40, 42, 44,
46, 48, 50, 54, 56, 58,
62, 66, 68
Ground Ground reference for signals.
RESERVED 8, 52, 60 —These terminals are reserved for future use. Do not connect
to these pins.

NI 6583R User Guide and Specifications 6 ni.com
Table 3 contains pin location and differential signal information for DDC B on the NI 6583.
Table 3. NI 6583 DDC B Connector Pins
Signal Name Pin(s) Signal Type Signal Description
DDC CLK OUT+ 65 Clock Positive terminal for the differential exported Sample clock.
DDC CLK OUT– 66 Clock Negative terminal for the differential exported Sample clock.
STROBE+ 62 Clock Positive external Sample clock source that can be used for
dynamic acquisition.
STROBE– 63 Clock Negative external Sample clock source that can be used for
dynamic acquisition.
DIO <0..15>+ 14, 17, 20, 23, 26,
29, 32, 35, 38, 41,
44, 47, 50, 53, 56,
59
Data Positive bidirectional digital I/O data channels 0 through 15.
DIO <0..15>– 15, 18, 21, 24, 27,
30, 33, 36, 39, 42,
45, 48, 51, 54, 57,
60
Data Negative bidirectional digital I/O data channels 0 through 15
PFI <1..3>+ 2, 5, 8 Control Positive bidirectional digital I/O trigger channels 1 through 3.
PFI <1..3>– 3, 6, 9 Control Negative bidirectional digital I/O trigger channels 1 through 3.
GND 1, 4, 7, 10, 13, 16,
19, 22, 25, 28, 31,
34, 37, 40, 43, 46,
49, 52, 55, 58, 61,
64, 67, 70, 73
Ground Ground reference for signals.
RESERVED 11, 12, 68, 69, 71,
72
—These terminals are reserved for future use. Do not connect
to these pins.

©National Instruments Corporation 7 NI 6583R User Guide and Specifications
Block Diagrams
Figures 4 through 7 show the data flow through the NI 6583R. Single-ended data lines use standardized
voltage levels to interpret data as either a binary zero or a one in high-speed digital data transfers.
Differential data lines provide a low-noise, low-power, low-amplitude differential method for
high-speed digital data transfer.
Figure 4. Clock Input Signals
Figure 5. Differential Data and PFI Lines
DDC A STROBE
UserGclkLvds on
NI FlexRIO
FPGA Module
(I/O Module Clock 1)
UserGclkLvttl on
NI FlexRIO
FPGA Module
(I/O Module Clock 0)
DDC B STROBE
DDC B STROBE
100 Ω
Data from
NI FlexRIO
FPGA Module
(GPIO Output)
Direction Control
from NI FlexRIO
FPGA Module
(GPIO Direction)
Data to
NI FlexRIO
FPGA Module
(GPIO Input)
DDC B Channel
DDC B Channel
100 Ω

NI 6583R User Guide and Specifications 8 ni.com
Figure 6. Single-Ended Data and PFI Lines
Figure 7. Clock Output Signals
Data to and from
NI FlexRIO
FPGA Module
(GPIO I/O)
Direction Control
from NI FlexRIO
FPGA Module
(GPIO Direction)
DDC A Channel
50 Ω
Clock from
NI FlexRIO
FPGA Module
(GPIO Output)
Output Enable
from NI FlexRIO
FPGA Module
(GPIO Direction)
Clock from
NI Flex RIO
FPGA Module
(GPIO Output)
Output Enable
from NI FlexRIO
FPGA Module
(GPIO Direction)
DDC B CLK OUT
DDC B CLK OUT
100 Ω
DDC A CLK OUT
50 Ω

©National Instruments Corporation 9 NI 6583R User Guide and Specifications
Tables 4 and 5 list the NI 6583 connector signals and corresponding NI FlexRIO FPGA module signals
necessary for designing custom component-level IP (CLIP). The _CC suffix on the single-ended and
differential signals identifies channels that are capable of receiving a regional clock. Refer to the Block
Diagrams section of this document for more information about connecting signals from the NI 6583 to
the FPGA module.
Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals
NI 6583 NI FlexRIO FPGA Module
Connector Signal Name GPIO I/O GPIO Direction
DDC A (Single-ended I/O) DIO 0 GPIO_16_n GPIO_16
DIO 1 GPIO_2_n GPIO_2
DIO 2 GPIO_19_n GPIO_19
DIO 3 GPIO_5_n_CC GPIO_5_CC
DIO 4 GPIO_20_n GPIO_20
DIO 5 GPIO_4_n_CC GPIO_4_CC
DIO 6 GPIO_7_n_CC GPIO_7_CC
DIO 7 GPIO_3_n GPIO_3
DIO 8 GPIO_23_n_CC GPIO_23_CC
DIO 9 GPIO_6_n_CC GPIO_6_CC
DIO 10 GPIO_22_n GPIO_22
DIO 11 GPIO_21_n GPIO_21
DIO 12 GPIO_25_n_CC GPIO_25_CC
DIO 13 GPIO_10_n GPIO_10
DIO 14 GPIO_24_n_CC GPIO_24_CC
DIO 15 GPIO_9_n GPIO_9
DIO 16 GPIO_12_n GPIO_12
DIO 17 GPIO_8_n GPIO_8
DIO 18 GPIO_27_n GPIO_27
DIO 19 GPIO_28_n GPIO_28
DIO 20 GPIO_11_n GPIO_11
DIO 21 GPIO_26_n_CC GPIO_26_CC
DIO22 GPIO_30_n GPIO_30
DIO 23 GPIO_15_n GPIO_15
DIO 24 GPIO_29_n GPIO_29
DIO 25 GPIO_14_n GPIO_14

NI 6583R User Guide and Specifications 10 ni.com
Note For the DIO and PFI lines, drive the GPIO Direction high for output and low for input.
For CLK OUT, drive the GPIO Direction high for enable and low for disable.
DDC A (Single-ended I/O) DIO 26 GPIO_50_n GPIO_50
DIO 27 GPIO_13_n GPIO_13
DIO 28 GPIO_32_n GPIO_32
DIO 29 GPIO_31_n GPIO_31
DIO 30 GPIO_49_n GPIO_49
DIO 31 GPIO_33_n GPIO_33
PFI 1 GPIO_0_n GPIO_0
PFI 2 GPIO_18_n GPIO_18
PFI 3 GPIO_1_n GPIO_1
STROBE GClk_SE —
CLK OUT GPIO_17_n GPIO_17
(as enable)
Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals (Continued)
NI 6583 NI FlexRIO FPGA Module
Connector Signal Name GPIO I/O GPIO Direction