Nuvoton ISD1700 series Guide

PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 1 - Revision 1.31
ISD1700 Series
Design Guide

PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 2 - Revision 1.31
TABLE OF CONTENTS
1GENERAL DESCRIPTION ..............................................................................................................6
2FEATURES......................................................................................................................................7
3BLOCK DIAGRAM...........................................................................................................................8
4PINOUT CONFIGURATION............................................................................................................9
5PIN DESCRIPTION .......................................................................................................................10
6FUNCTIONAL DESCRIPTION ......................................................................................................14
6.1 Detailed Description...............................................................................................................14
6.1.1 Audio Quality................................................................................................................14
6.1.2 Message Duration........................................................................................................14
6.1.3 Flash Storage...............................................................................................................14
6.2 Memory Array Architecture ....................................................................................................14
6.3 Modes of Operations..............................................................................................................16
6.3.1 Standalone (Push-Button) Mode .................................................................................16
6.3.2 SPI Mode .....................................................................................................................16
7ANALOG PATH CONFIGURATION (APC)...................................................................................17
7.1 APC Register .........................................................................................................................17
7.2 Device Analog Path Configurations .......................................................................................18
8STANDALONE (PUSH-BUTTON) OPERATIONS ........................................................................19
8.1 Sound Effect (SE) Mode ........................................................................................................19
8.1.1 Sound Effect (SE) Features.........................................................................................19
8.1.2 Entering SE Mode........................................................................................................19
8.1.3 SE Editing ....................................................................................................................19
8.1.4 Exiting SE Mode ..........................................................................................................20
8.1.5 Sound Effect Duration..................................................................................................20
8.2 Operation Overview ...............................................................................................................20
8.2.1 Record Operation ........................................................................................................21
8.2.2 Playback Operation .....................................................................................................21
8.2.3 Forward Operation.......................................................................................................22
8.2.4 Erase Operation...........................................................................................................23
8.2.5 Reset Operation...........................................................................................................25
8.2.6 VOL Operation.............................................................................................................25
8.2.7 FT (Feed-Through) Operation .....................................................................................26
8.3 vAlert Feature (Optional)........................................................................................................26
8.4 Analog Inputs .........................................................................................................................26

PRELIMINARY ISD1700 SERIES
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8.4.1 Microphone Input .........................................................................................................26
8.4.2 AnaIn Input...................................................................................................................27
8.5 System Management .............................................................................................................27
9CIRCULAR MEMORY ARCHITECTURE (CMA) ..........................................................................28
9.1 Restoring Circular Memory Architecture................................................................................30
10 SERIAL PERIPHERAL INTERFACE (SPI) MODE........................................................................31
10.1 Microcontroller Interface ........................................................................................................31
10.2 SPI Interface Overview ..........................................................................................................31
10.2.1SPI Transaction Format...............................................................................................31
10.2.2MOSI Data Format.......................................................................................................32
10.2.3MISO Data Format.......................................................................................................33
10.3 SPI Command Overview........................................................................................................34
10.4 Switching from SPI mode to Standalone Mode .....................................................................35
10.5 ISD1700 Device Registers.....................................................................................................35
10.5.1Status Register 0 (SR0)...............................................................................................35
10.5.2Status Register 1 (SR1)...............................................................................................37
10.5.3APC Register ...............................................................................................................37
10.5.4Playback Pointer (PLAY_PTR)....................................................................................38
10.5.5Record Pointer (REC_PTR) ........................................................................................38
10.5.6DEVICEID Register .....................................................................................................38
11 SPI COMMAND REFERENCE......................................................................................................39
11.1 SPI Priority Commands..........................................................................................................41
11.1.1PU (0x01) Power Up....................................................................................................41
11.1.2STOP (0x02) ................................................................................................................42
11.1.3RESET (0x03)..............................................................................................................42
11.1.4CLR_INT(0x04)............................................................................................................43
11.1.5RD_STATUS (0x05) ....................................................................................................43
11.1.6PD (0x07) Power Down ...............................................................................................44
11.1.7DEVID (0x09) Read Device ID ....................................................................................45
11.2 Circular Memory Commands .................................................................................................45
11.2.1PLAY (0x40).................................................................................................................46
11.2.2REC (0x41) ..................................................................................................................46
11.2.3ERASE (0x42)..............................................................................................................47
11.2.4G_ERASE (0x43) Global Erase...................................................................................48
11.2.5FWD (0x48)..................................................................................................................48
11.2.6CHK_MEM (0x49) Check Circular Memory.................................................................49

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11.2.7RD_PLAY_PTR (0x06) ................................................................................................50
11.2.8RD_REC_PTR (0x08)..................................................................................................50
11.3 Analog Configuration Commands..........................................................................................51
11.3.1RD_APC (0x44) Read APC Register ..........................................................................51
11.3.2WR_APC1 (0x45) Load APC Register ........................................................................51
11.3.3WR_APC2 (0x65) Load APC Register ........................................................................52
11.3.4WR_NVCFG (0x46) Write APC data into Non-Volatile Memory .................................53
11.3.5LD_NVCFG (0x47) Load APC register from Non-Volatile Memory.............................53
11.4 Direct Memory Access Commands .......................................................................................54
11.4.1SET PLAY (0x80).........................................................................................................54
11.4.2SET_REC (0x81) .........................................................................................................55
11.4.3SET_ERASE (0x82) ....................................................................................................56
11.5 Additional Command..............................................................................................................56
11.5.1EXTCLK (0x4A) ...........................................................................................................57
11.6 General Guidelines for Writing Program Code ......................................................................58
11.7 Examples of Various Operating Sequences ..........................................................................59
11.7.1Record, Stop and Playback operations .......................................................................60
11.7.2SetRec and SetPlay operations...................................................................................61
11.7.3Wr_APC2, SetRec and SetPlay operations.................................................................62
11.7.4Playback 3 Messages as 1 Message (using SetPlay).................................................63
12 TIMING DIAGRAMS ......................................................................................................................64
12.1 Record Operation...................................................................................................................64
12.2 Playback Operation................................................................................................................65
12.3 Erase Operation .....................................................................................................................66
12.4 Forward Operation .................................................................................................................67
12.5 Global Erase Operation .........................................................................................................68
12.6 Reset Operation .....................................................................................................................68
12.7 Looping Playback Operation..................................................................................................69
12.8 Global Erase Operation to Restore Circular Memory Architecture........................................70
12.9 Playback Operation with AUD Output....................................................................................70
12.10 SPI Operation ..................................................................................................................71
13 ABSOLUTE MAXIMUM RATINGS ................................................................................................72
13.1 Operating Conditions .............................................................................................................73
14 ELECTRICAL CHARACTERISTICS .............................................................................................74
14.1 DC Parameters ......................................................................................................................74
14.2 AC Parameters.......................................................................................................................75

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15 TYPICAL APPLICATION CIRCUITS.............................................................................................76
15.1 Good Audio Design Practices ................................................................................................79
16 ORDERING INFORMATION .........................................................................................................80
17 VERSION HISTORY......................................................................................................................81

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1 GENERAL DESCRIPTION
The Nuvoton®ISD1700 ChipCorder®Series is a high quality, fully integrated, single-chip multi-
message voice record and playback device ideally suited to a variety of electronic systems. The
message duration is user selectable in ranges from 26 seconds to 120 seconds, depending on the
specific device. The sampling frequency of each device can also be adjusted from 4 kHz to 12 kHz
with an external resistor, giving the user greater flexibility in duration versus recording quality for each
application. Operating voltage spans a range from 2.4 V to 5.5 V to ensure that the ISD1700 devices
are optimized for a wide range of battery or line-powered applications.
The ISD1700 is designed for operation in either standalone or microcontroller (SPI) mode. The device
incorporates a proprietary message management system that allows the chip to self-manage address
locations for multiple messages. This unique feature provides sophisticated messaging flexibility in a
simple push-button environment. The devices include an on-chip oscillator (with external resistor
control), microphone preamplifier with Automatic Gain Control (AGC), an auxiliary analog input, anti-
aliasing filter, Multi-Level Storage (MLS) array, smoothing filter, volume control, Pulse Width
Modulation (PWM) Class D speaker driver, and current/voltage output.
The ISD1700 devices also support an optional “vAlert” (voiceAlert) feature that can be used as a new
message indicator. With vAlert, the device flashes an external LED to indicate that a new message is
present. Besides, four special sound effects are reserved for audio confirmation of operations, such as
“Start Record”, “Stop Record”, “Erase”, “Forward”, “Global Erase”, and etc.
Recordings are stored into on-chip Flash memory, providing zero-power message storage. This unique
single-chip solution is made possible through Nuvoton’s patented Multi-Level Storage (MLS)
technology. Audio data are stored directly in solid-state memory without digital compression, providing
superior quality voice and music reproduction.
Voice signals can be fed into the chip through two independent paths: a differential microphone input
and a single-ended analog input. For outputs, the ISD1700 provides a Pulse Width Modulation (PWM)
Class D speaker driver and a separate analog output simultaneously. The PWM can directly drive a
standard 8Ωspeaker or typical buzzer, while the separate analog output can be configured as a single-
ended current or voltage output to drive an external amplifier.
While in Standalone mode, the ISD1700 devices automatically enter into power down mode for power
conservation after an operation is completed.
In the SPI mode, the user has full control via the serial interface in operating the device. This includes
random access to any location inside the memory array by specifying the start address and end
address of operations. SPI mode also allows access to the Analog Path Configuration (APC) register.
This register allows flexible configuration of audio paths, inputs, outputs and mixing. The APC default
configuration for standalone mode can also be modified by storing the APC data into a non-volatile
register (NVCFG) that is loaded at initialization. Utilizing the capabilities of ISD1700 Series, designers
have the control and flexibility to implement voice functionality into the high-end products.
Notice: The specifications are subject to change without notice. Please contact Nuvoton Sales Offices or
Representatives to verify current or future specifications. Also, refer to the website for any related application
notes.

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2 FEATURES
yIntegrated message management systems for single-chip, push-button applications
oREC:level-trigger for recording
oPLA
Y
:edge-trigger for individual message or level-trigger for looping playback sequentially
oERASE:edge-triggered erase for first or last message or level-triggered erase for all messages
oFWD :edge-trigger to advance to the next message or fast message scan during the playback
oVOL : 8 levels output volume control
oINTRDY : ready or busy status indication
oRESET : return to the default state
oAutomatic power-down after each operation cycle
ySelectable sampling frequency controlled by an external oscillator resistor
Sampling Frequency 12 kHz 8 kHz 6.4 kHz 5.3 kHz 4 kHz
Rosc 53 kΩ80 kΩ100 kΩ120 kΩ160 kΩ
ySelectable message duration
oA wide range selection from 30 secs to 240 secs at 8 kHz sampling frequency
yMessage and operation indicators
oFour customizable Sound Effects (SEs) for audible indication
oOptional vAlert (voiceAlert) to indicate the presence of new messages
oLED: stay on during recording, blink during playback, forward and erase operations
yDual operating modes
oStandalone mode:
Integrated message management techniques
Automatic power-down after each operation cycle
oSPI mode:
Fully user selectable and controllable options via APC register and various SPI commands
yTwo individual input channels
oMIC+/MIC-: differential microphone inputs with AGC (Automatic Gain Control)
oAnaIn: single-ended auxiliary analog input for recording or feed-through
yDual output channels
oDifferential PWM Class D speaker outputs directly drives an 8 speaker or a typical buzzer
oConfigurable AUD (current) or AUX (voltage) single-ended output drives external audio amplifier
yChipCorder standard features
oHigh-quality, natural voice and audio reproduction
o2.4V to 5.5V operating voltage
o100-year message retention (typical)
o100,000 record cycles (typical)
yTemperature options:
oCommercial: 0°C to +50°C (die); 0°C to +70°C (packaged units)
oIndustrial: -40°C to +85°C (packaged units)
yPackaging types: available in die, PDIP, SOIC and TSOP
yPackage option: Lead-free packaged units

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3 BLOCK DIAGRAM
Internal
Clock Timing
Nonvolatile
Multi-Level Storage
Array
Power Conditioning
Automatic
Gain Control
Anti-
Aliasing
Filter Smoothing
Filter
Sampling
Clock
SP+
SP-
AGC
MIC-
MIC+
R
OSC
V
CCA
AUD /
AUX
Amp
SPI Interface
V
CCD
Device Control
V
SSD
V
SSA
V
SSP1
V
CCP
MISOMOSISCLKSSREC PLAY ERASE
Volume
Control
AnaIn
Amp
MUX
AGC
Amp
AnaIn
Amp
V
SSP2
FT
FWD VOL LEDINT/RDYRESET

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4 PINOUT CONFIGURATION
SOIC / PDIP
ISD1700
VCCD
PLAY
RESET
INT / RDY
FWD
VSSA
FT
LED
28
27
26
25
24
23
22
MIC-
MIC+
VCCA
21
SP-
ERASE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
19
18
17
16
15
REC
MOSI
SS
SCLK
MISO
AnaIn
VSSP2
VCCP
VSSP1
Sp+
AUD / AUX
AGC
VOL
ROSC
VSSD
TSOP
ISD1700
VSSA
MIC-
MIC+
SP-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AnaIn
VSSP2
VCCP
V
VSSP1
Sp+
AUD/AUX
AGC
ROSC
VOL
CCA
VCCD
MOSI
SCLK
MISO
INT / RDY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REC
VSSD
LED
RESET
SS
FT
PLAY
ERASE
FWD

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5 PIN DESCRIPTION
PIN
NAME PDIP / SOIC TSOP FUNCTIONS [3]
VCCD 1 22
Digital Power Supply: It is important to have a separate path for each
power signal including VCCD, VCCA and VCCP to minimize the noise
coupling. Decoupling capacitors should be as close to the device as
possible.
LED 2 23
LED: With an LED connected, this output turns an LED on during
recording and blinks LED during playback, forward and erase operations.
RESET 3 24
RESET: When Low, the device enters into a known state and initializes all
pointers to the default state. This pin has an internal pull-up resistor [1].
Due to debounce is absent, this pin must be tied to Vcc if not used.
MISO 4 25 Master In Slave Out: Data is shifted out on the falling edge of SCLK.
When the SPI is inactive ( SS = high), it’s tri-state.
MOSI 5 26
Master Out Slave In: Data input of the SPI interface when the device is
configured as slave. Data is latched into the device on the rising edge of
SCLK. This pin has an internal pull-up resistor [1].
SCLK 6 27
Serial Clock: Clock of the SPI interface. It is usually generated by the
master device (typically microcontroller) and is used to synchronize the
data transfer in and out of the device through the MOSI and MISO lines,
respectively. This pin has an internal pull-up resistor [1].
SS 7 28
Slave Select: This input, when low, selects the device as slave device
and enables the SPI interface. This pin has an internal pull-up resistor [1].
VSSA 8 1
Analog Ground: It is important to have a separate path for each ground
signal including VSSA, VSSD, VSSP1 and VSSP2 to minimize the noise
coupling.
AnaIn 9 2
AnaIn: Auxiliary analog input to the device for recording or feed-through.
An AC-coupling capacitor (typical 0.1uF) is necessary and the amplitude
of the input signal must not exceed 1.0 Vpp. Depending upon the D3 of
APC register, AnaIn signal can be directly recorded into the memory,
mixed with the Mic signal then recorded into the memory or buffered to
the speaker and AUD/AUX outputs via feed-through path.
MIC+ 10 3
MIC+: Non-inverting input of the differential microphone signal. The input
signal should be AC-coupled to this pin via a series capacitor. The
capacitor value, together with an internal 10 Kresistance on this pin,
determines the low-frequency cutoff for the pass band filter. The Mic
analog path is also controlled by D4 of APC register.
MIC- 11 4
MIC-: Inverting input of the differential microphone signal. The input signal
should be AC-coupled to the MIC+ pin. It provides input noise-
cancellation, or common-mode rejection, when the microphone is
connected differentially to the device. The Mic analog path is also
controlled by D4 of APC register.
VSSP2 12 5
Ground for Negative PWM Speaker Driver: It is important to have a
separate path for each ground signal including VSSA, VSSD, VSSP1 and VSSP2
to minimize the noise coupling.

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FUNCTIONS [3]PIN PDIP / TSOP
NAME SOIC
SP- 13 6
SP-: The negative Class D PWM provides a differential output with SP+
pin to directly drive an 8 speaker or typical buzzer. During power down
or not used, this pin is tri-stated. This output can be controlled by D8 of
APC register. The factory default is set at on state.
VCCP 14 7
Power Supply for PWM Speaker Driver: It is important to have a
separate path for each power signal including VCCD, VCCA and VCCP to
minimize the noise coupling. Decoupling capacitors to VSSP1 and VSSP2
should be as close to the device as possible. The VCCP supply and VSSP
ground pins have large transient currents and need low impedance
returns to the system supply and ground, respectively.
SP+ 15 8
SP+: The positive Class D PWM provides a differential output with the
SP- pin to directly drive an 8 speaker or typical buzzer. During power
down or not used, this pin is tri-stated. This output can be controlled by
D8 of APC register. The factory default is set at on state.
VSSP1 16 9
Ground for Positive PWM Speaker Driver: It is important to have a
separate path for each ground signal including VSSA, VSSD, VSSP1 and VSSP2
to minimize the noise coupling.
AUD /
AUX
17 10
Auxiliary Output: Depending upon the D7 of APC register, this output is
either an AUD or AUX output. AUD is a single-ended current output,
whereas AUX is a single-ended voltage output. They can be used to drive
an external amplifier. The factory default is set to AUD. This output can be
powered down by D9 of APC register. The factory default is set to On
state. For AUD output, there is a ramp up at beginning and ramp down at
the end to reduce the pop.
AGC 18 11
Automatic Gain Control (AGC): The AGC adjusts the gain of the
preamplifier dynamically to compensate for the wide range of microphone
input levels. The AGC allows the full range of signals to be recorded with
minimal distortion. The AGC is designed to operate with a nominal
capacitor of 4.7 µF connected to this pin.
Connecting this pin to ground (VSSA) provides maximum gain to the
preamplifier circuitry. Conversely, connecting this pin to the power supply
(VCCA) provides minimum gain to the preamplifier circuitry.
VOL 19 12
Volume: This control has 8 levels of volume adjustment. Each Low going
pulse decreases the volume by one level. Repeated pulses decrease
volume level from current setting to minimum then increase back to
maximum, and continue this pattern. During power-up or RESET , a
default setting is loaded from non-volatile configuration. The factory
default is set to maximum. This output can also be controlled by <D2:D0>
of APC register. This pin has an internal pull-up device [1] and an internal
debounce (TDeb) [2] for start and end allowing the use of a push button
switch.
ROSC 20 13
Oscillator Resistor: A resistor connected from ROSC pin to ground
determines the sample frequency of the device, which sets the duration.
Please refer to the Duration Section for details.

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FUNCTIONS [3]PIN PDIP / TSOP
NAME SOIC
VCCA 21 14
Analog Power Supply. It is important to have a separate path for each
power signal including VCCD, VCCA and VCCP to minimize the noise
coupling. Decoupling capacitors to VSSA should be as close to the device
as possible.
FT 22 15
Feed-through: In Standalone mode, when FT is engaged low, the AnaIn
feed-through path is activated. As a result, the AnaIn signal is transmitted
directly from AnaIn to both Speaker and AUD/AUX outputs with Volume
Control. However, SPI overrides this input, while in SPI mode, and feed-
through path is controlled by a D6 of APC register. This pin has an
internal pull-up device [1] and an internal debounce (TDeb) [2] for start and
end allowing the use of a push button switch.
PLA
Y
23 16
Playback: Pulsing PLA
Y
to Low once initiates a playback operation.
Playback stops automatically when it reaches the end of the message.
Pulsing it to Low again during playback stops the operation.
Holding PLA
Y
Low constantly functions as a sequential playback
operation loop. This looping continues until PLA
Y
returns to High. This
pin has an internal pull-up device [1] and an internal debounce (TDeb) [2] for
start and end allowing the use of a push button switch.
REC
24 17
Record: The device starts recording whenever REC switches from High
to Low and stays at Low. Recording stops when the signal returns to
High. This pin has an internal pull-up device [1] and an internal debounce
(TDeb) [2] for start allowing the use of a push button switch.
ERASE 25 18
Erase: When active, it starts an erase operation. Erase operation will take
place only when the playback pointer is positioned at either the first or last
message. Pulsing this pin to Low enables erase operation and deletes the
current message. Holding this pin Low for more than 3 sec. initiates a
global erase operation, and will delete all the messages. This pin has an
internal pull-up device [1] and an internal debounce (TDeb) [2] for start and
end allowing the use of a push button switch.
FWD 26 19
Forward: When triggered, it advances to the next message from the
current location, when the device is in power down status. During
playback cycle, pulsing this pin Low stops the current playback operation
and advances to the next message, and then re-starts the playback
operation of the new message. This pin has an internal pull-up device [1]
and an internal debounce (TDeb) [2] for start and end allowing the use of a
push button switch.
INTRDY 27 20
An open drain output.
Ready (Standalone mode):
This pin stays Low during record, play, erase and forward operations and
stays High in power down state
Interrupt (SPI mode):
After completing the SPI command, an active low interrupt is generated.
Once the interrupt is cleared, it returns to High.

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PIN
NAME PDIP / SOIC TSOP FUNCTIONS [3]
VSSD 28 21 Digital Ground: It is important to have a separate path for each ground
signal including VSSA, VSSD, VSSP1 and VSSP2 to minimize the noise
coupling.
Note: [1] 600 kΩ
[2] TDeb = Refer to AC Timing
[3] For any unused pins, left floated.

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6 FUNCTIONAL DESCRIPTION
6.1 DETAILED DESCRIPTION
6.1.1 Audio Quality
Nuvoton’s patented ChipCorder®Multi-Level Storage (MLS) technology provides a natural,
high-quality record and playback solution on a single chip. The input voice signals are stored
directly in the Flash memory and are reproduced in their natural form without any of the
compression artifacts caused by digital speech solutions.
6.1.2 Message Duration
The ISD1700 Series offer record and playback duration from 20 seconds to 480 seconds.
Sampling frequency and message duration, TDur, are determined by an external resistor
connected to the ROSC pin.
Table 6.1 Duration vs. Sampling Frequency
Sample Freq. ISD1730 ISD1740 ISD1750 ISD1760 ISD1790 ISD17120 ISD17150 ISD17180 ISD17210 ISD17240
12 kHz 20 secs 26 secs 33 secs 40 secs 60 secs 80 secs 100 secs 120 secs 140 secs 160 secs
8 kHz 30 secs 40 secs 50 secs 60 secs 90 secs 120 secs 150 secs 180 secs 210 secs 240 secs
6.4 kHz 37 secs 50 secs 62 secs 75 secs 112 secs 150 secs 187 secs 225 secs 262 secs 300 secs
5.3 kHz 45 secs 60 secs 75 secs 90 secs 135 secs 181 secs 226 secs 271 secs 317 secs 362 secs
4 kHz 60 secs 80 secs 100 secs 120 secs 180 secs 240 secs 300 secs 360 secs 420 secs 480 secs
6.1.3 Flash Storage
The ISD1700 devices utilize embedded Flash memory to provide non-volatile storage. A
message can be retained for a minimum of 100 years without power. Additionally, each
device can be re-recorded over 100,000 times (typical).
6.2 MEMORY ARRAY ARCHITECTURE
The memory array provides storage of four special Sound Effects (SEs) as well as the voice data.
The memory array is addressed by rows. A row is the minimum storage resolution by which the
memory can be addressed. The memory assignment is automatically handled by the internal
message management system in standalone mode. While in SPI mode, one has the full access to
the entire memory via the eleven address bits. Table 6.2 shows the minimum storage resolution
with respect to the sampling frequency.
Table 6.2 Minimum Storage Resolution vs. Sampling Frequency
Sampling Frequency 12 kHz 8 kHz 6.4 kHz 5.3 kHz 4 kHz
Minimum Storage Resolution 83.3 msec 125 msec 156 msec 187 msec 250 msec
For example, at 8 kHz sampling frequency, the minimum storage resolution is 125 msec, so each
Sound Effect (SE) is approximately 0.5 second long.
Table 6.3 shows the maximum row address of each device in the ISD1700 family. The four sound
effects (SE) occupy the first sixteen rows in the memory array with four rows for each SE. That

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means from address 0x000 to address 0x00F. The remaining memory is dedicated to voice data
storage. Hence, the address of voice message storage will start from 0x010 to the end of memory
array.
Table 6.3 Device Maximum Row Address
Device ISD1730 ISD1740 ISD1750 ISD1760 ISD1790 ISD17120 ISD17150 ISD17180 ISD17210 ISD17240
Maximum
Address 0x0FF 0x14F 0x19F 0x1EF 0x2DF 0x3CF 0x4BF 0x5AF 0x69F 0x78F
Below figure shows the memory array architecture for ISD1700 series.
000 - 003 SE1
004 - 007 SE2
008 - 00B SE3
00C - 00F SE4
010 1st row of Voice Message
78F Last row of ISD17240
Accessible by
SPI Set Commands
or SE mode
Accessible by
SPI Set Commands
or
Standalone Alike
SPI Commands
3CF Last row of ISD17120
5AF Last row of ISD17180
4BF Last row of ISD17150
69F Last row of ISD17180
1EF Last row of ISD1760
2DF Last row of ISD1790
0FF Last row of ISD1730
14F Last row of ISD1740
19F Last row of ISD1750

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6.3 MODES OF OPERATIONS
The ISD1700 Series can operate in either Standalone (Push-Button) or microcontroller (SPI)
mode.
6.3.1 Standalone (Push-Button) Mode
Standalone operation entails use of the REC , PLA
Y
, FT , FWD , ERASE , VOL and
RESET pins to trigger operations. The internal state machine automatically configures the
audio path according to the desired operation. In this mode, the internal state machine takes
full control on message management. This allows the user to record, playback, erase, and
forward messages without the needs to know the exact addresses of the messages stored
inside the memory. For additional information, refer to Standalone Mode sections.
6.3.2 SPI Mode
In SPI mode, control of the device is achieved through the 4-wire serial interface. Commands
similar to the push button controls, such as REC , PLA
Y
, FT , FWD , ERASE , VOL and
RESET , can be executed through the SPI interface. In addition, there are commands that
allow the modification of the analog path configuration, as well as commands that direct
access the memory address of the array, plus others. The SPI mode allows full control of the
device and the ability to perform complex message management rather than conform to the
circular memory architecture as push-button mode. Refer to SPI Mode sections for details.
In addition, it is suggested that both the microcontroller and the ISD1700 device have the
same power supply level for design simplicity.
In either mode, it is strongly recommended that any unused pins, no matter input or output, must
be left floated or unconnected. Otherwise, it will cause the device becoming malfunction.

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7 ANALOG PATH CONFIGURATION (APC)
The analog path of the ISD1700 can be configured to accommodate a wide variety of signal path
possibilities. This includes the source of recording signals, mixing of input signals, mixing the playback
signal with an input signal to the outputs, feed-through signal to the outputs and which outputs being
activated.
The active analog path configuration is determined by a combination of the internal state of the device,
i.e. desired operation (record or playback), the status of the FT and the contents of the APC register.
The APC register is initialized by the internal non-volatile configuration (NVCFG) bits upon power-on-
reset or reset function. The APC register can be read and loaded using SPI commands.
The factory default of NVCFG bits, <D11:D0>, is 0100 0100 0000 = 0x440. This configures the device
with recording through the MIC inputs, FT via AnaIn input, playback from MLS, SE editing feature
enabled, maximum volume level, active PWM driver and AUD current outputs. One can use SPI
commands to modify the APC register and store it permanently into the NVCFG bits.
7.1 APC REGISTER
Details of the APC register are shown in Table 7.1.
Table 7.1 APC Register
Bit Name Description Default
D0 VOL0 Volume control bits <D2:D0>: These provide 8 steps of
-4dB per step volume adjustment. Each bit changes
the volume by one step, where 000 = maximum and
111 = minimum.
000 (maximum)
D1 VOL1
D2 VOL2
D3 Monitor_Input Monitor input signal at outputs during recording. 0 = Monitor_input is
Disabled
D3 = 0 Disable input signal to outputs during record
D3 = 1 Enable input signal to outputs during record
D4 Mix_Input Combined with FT in standalone mode or SPI_FT bit
(D6) in SPI mode, D4 controls the input selection for
recording.
0 = Mix_Input is Off
D4 = 0 FT / D6= 0 AnaIn REC
FT / D6= 1 Mic REC
D4 = 1 FT / D6= 0 (Mic + AnaIn) REC
FT / D6= 1 Mic REC
D5 SE_Editing Enable or disable editing of Sound Effect in Standalone
mode: where 0 = Enable, 1 = Disable
0 = Enable
SE_Editing

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Bit Name Description Default
D6 SPI_FT For SPI mode only. Once SPI_PU command is sent,
the FT is disabled and replaced by this control bit
(D6) with the same functionality. After exiting SPI mode
through the PD command, the FT resumes control of
feed-through (FT) function.
1 = SPI_FT is Off
D6 = 0 FT function in SPI mode is On
D6 = 1 FT function in SPI mode is Off
D7 Analog Output:
AUD/AUX
Select AUD or AUX: 0 = AUD, 1 = AUX 0 = AUD
D8 PWM SPK PWM Speaker +/- outputs: 0 = Enabled, 1 = Disabled 0 = PWM enabled
D9 PU Analog
Output
PowerUp analog output: 0 = On, 1 = Off 0 = On
D10 vAlert vAlert: 0 = On, 1 = Off. 1 = Off
D11 EOM Enable EOM Enable for SetPlay operation: 0 = Off, 1 = On.
When this bit is set to 1, SetPlay operation will stop at
EOM location, rather than the End Address.
0 = Off
7.2 DEVICE ANALOG PATH CONFIGURATIONS
Table 7.2 demonstrates the possible analog path configurations with ISD1700. The device can be
in power-down, power-up, recording, playback and/or feed-through state depending upon the
operation requested by the push-buttons or related SPI commands. The active path in each of
these states is determined by D3 and D4 of the APC register, as well as either D6 of the APC
register in SPI mode or the FT status in standalone mode. In addition,.D7~D9 of the APC
register determine which output drivers are activated.
Table 7.2 Operational Paths
APC Register Operational Paths
D6/FT D4 Mix D3 Mon Idle Record Playback
0 0 0 AnaIn FT AnaIn Rec (AnaIn + MLS) --> o/p
0 0 1 AnaIn FT AnaIn Rec + AnaIn FT (AnaIn + MLS) --> o/p
0 1 0 (Mic + AnaIn) FT (Mic + AnaIn) Rec (AnaIn + MLS) --> o/p
0 1 1 (Mic + AnaIn) FT
(Mic + AnaIn) Rec +
(Mic + AnaIn) FT (AnaIn + MLS) --> o/p
1 0 0 FT Disable Mic Rec MLS --> o/p
1 0 1 FT disable Mic Rec + Mic FT MLS --> o/p
1 1 0 FT disable Mic Rec MLS --> o/p
1 1 1 FT disable Mic Rec + Mic FT MLS --> o/p

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8 STANDALONE (PUSH-BUTTON) OPERATIONS
One can utilize the REC , PLA
Y
, FT , FWD , ERASE, VOL or RESET control to initiate a desired
operation. As completed, the device automatically enters into the power-down state. An unique
message management system is executed under this mode, which links to an optional special Sound
Effect (SE) feature to review certain operating status of the device. Hence, it is benefit to understand
how SE functions first.
8.1 SOUND EFFECT (SE) MODE
SE mode can be manipulated by several control pins as described below. There are four special
sound effects (SE1, SE2, SE3, and SE4). Audio clips can be programmed into the SEs as various
indications. Each SE occupies four designated memory rows and the first sixteen memory rows are
reserved for these four SEs evenly and sequentially.
8.1.1 Sound Effect (SE) Features
The functions of SEs are used to indicate the status of the following operations:
oSE1: Beginning of recording, forward or global erase warning
oSE2: End of recording, single erase or forward from last message
oSE3: Invalid erase operation
oSE4: Successful global erase
In general, the LED flashes once for SE1, twice for SE2, and so forth. It is crucial to recognize
that the LED flashes accordingly regardless the SEs are programmed or not. When none of
them is programmed, the blinking periods of SE1, SE2, SE3 and SE4 are defined as TLS1,
TLS2, TLS3 and TLS4, respectively. Once they are programmed, during operation, the device
flashes LED and plays the related SE simultaneously. Nevertheless, the period of blinking
LED, under this condition, is limited by the duration of the recorded SE. In addition, they are
defined as TSE1, TSE2, TSE3 and TSE4, respectively. These timing parameters also apply to the
conditions elaborated in the following related sections. (Refer to AC timing parameter for
details.)
8.1.2 Entering SE Mode
•First press and hold FWD Low for 3 seconds or more roughly. This action on FWD will
usually blink LED once (and play SE1 simultaneously if SE1 is recorded). However, if
playback pointer is at the last message or memory is empty, the chip will blink the LED
twice (and play SE2 simultaneously if SE2 is recorded).
•While holding
FWD Low, press and hold the REC Low until the LED blinks once.
•The LED flashing once again indicates that the device is now in SE mode. Once entering
into SE mode, the SE1 is always the first one to be accessible.
8.1.3 SE Editing
•After into SE editing mode, one can perform record, play, or erase operation on each SE
by pressing the appropriate buttons. For example, to record SE, simply press and hold

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REC . Similarly for play or erase function, pulse PLA
Y
or ERASE , respectively. Record
source can be either Mic+/- or AnaIn.
•A subsequent
FWD operation moves the record and playback pointers to the next SE
sequentially. The LED will also blink one to four times after such operation to indicate
which SE is active. If FWD is pressed while in SE4, the LED will flash once to indicate
that SE1 is again active.
•While the LED is blinking, the device will ignore any input commands. One must wait
patiently until the LED stops blinking completely before any record, play, erase or
forward input should be sent.
8.1.4 Exiting SE Mode
•The required steps are the same as Entering SE mode. First press and hold FWD until
the LED stops blinking (and related SE is played if SEs are programmed). Then,
simultaneously press and hold the REC Low until the LED blinks twice (and device will
play SE2 if SE2 is programmed). The device now exits the SE editing mode.
8.1.5 Sound Effect Duration
The duration of SEs is determined by the sampling frequency selected and illustrated in
below table.
Table 8.1 Sound Effect Duration vs. Sampling Frequency
Sampling Frequency 12 kHz 8 kHz 6.4 kHz 5.3 kHz 4 kHz
Duration of SE 0.33 sec 0.5 sec 0.625 sec 0.75 sec 1 sec
8.2 OPERATION OVERVIEW
After power is applied or power-on-reset (POR), the device is in the factory default state and two
internal record and playback pointers are initialized. (These two pointers are discussed later.) Then
the active analog path is determined by the state of the FT , the status of the APC register and the
desired operation.
Up to four optional sound effects (SE1~SE4) can be programmed into the device to provide audible
feedback to alert the user about the operating status. Simultaneously, the LED output provides
visual indication about the operating status. During the active state of LED output, no new
command will be accepted.
An unique message management technique is implemented. Under this mode, the recorded
messages are stored sequentially into the embedded memory from the beginning to the end in a
circular fashion automatically.
Two internal pointers, the record pointer and playback pointer, determine the location where an
operation starts. After POR, these pointers are initialized as follows:
•If no messages are present, both point to the beginning of memory.