NVIS 5586A User manual

Advanced 8086 Microprocessor Trainer
Nvis 5586A
Learning Material
Ver 1.0
Designed & Manufactured by:
141-B, Electronic Complex, Pardesipura, Indore- 452 010 India, Tel.: [phone],
Telefax: 91-731-4202959, Toll free: 1800-103-5050, E-mail: [e-mail]
Website: www.nvistech.com

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Advanced 8086 Microprocessor Trainer
Nvis 5586A
Table of Contents
1. Introduction 4
2. Technical Specifications 5
3. Safety Instructions 6
4. Theory 7
5. Capabilities 34
6. Hardware Description 35
7. Command Description 36
8. Memory Address & Port Address 65
9. Subroutines 68
10. Serial Communication 95
11. MASM Macro Assembler 100
12. Sample Programs 104
13. On-Board Interface 163
14. Parallel Communication between two Nvis 5586A 168
Trainers using 8255 in I/O mode
15. Serial Communication between two Nvis 5586A 169
Trainers
16. Connector Details 170
17. Jumper/DIP switch Details 178
18. Frequently Asked Questions 180
19. Warranty 188
20. List of Service Centers 189
21. References 190

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Introduction
General Description:
Nvis 5586A is a single board microprocessor training/development kit configured around the
Intel‘s 16 bit Microprocessor 8086. This kit can be used to train engineers, to control any
industrial process and to develop software for 8086 systems.
The kit has been designed to operate in the maximum mode. Co-processor 8087 and I/O
Processor 8089 can be added on board.
The kit communicates with the outside world through an IBM PC compatible Keyboard with
20x2 LCD Display. The kit also has the capacity of interacting with PC.
Nvis 5586A is packed up with powerful monitor in 128K Bytes of factory programmed
EPROMS and 32K Bytes of Read/Write Memory. The total memory on the board is 144K
Bytes. The system has 72 programmable I/O lines. The serial I/O Communication is made
possible through 8251.
For control applications, three 16 bit Timer/Counters are available through 8253. For real
time applications, the 8 level of interrupt are provided through 8259. Nvis 5586A provides
onboard battery backup for onboard RAM. This saves the user‘s program in case of power
failure.
The onboard resident system monitor software is very powerful. It provides various software
commands like BLOCK MOVE, SINGLE STEP, EXECUTE, FILL etc which are helpful in
debugging/developing software. An onboard line assembler provides user to write program in
assembling language.

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Technical Specifications
Central Processor : 8086, 16 bit Microprocessor operating in max. mode.
Co-Processor Support: Support 8087 Numeric Data Processor.
I/O Processor Support: Support 8089 I/O Processor.
EPROM : 128K Bytes of EPROM Loaded with monitor program.
RAM : 32K bytes of CMOS RAM with Battery Backup using 3.6V
Ni-Cd Battery.
Parallel : 72 I/O lines using three nos. of 8255.
Serial : RS-232-C Interface using 8251.
Interrupt : 8 different level interrupt using 8259.
Timer/Counter : Three 16 bit Timer/Counter using 8253.
Keyboard & Display: 105 IBM PC Keyboard & 20x2 LCD Display.
BUS : All address, data and control signals (TTL Compatible)
available at 50 Pin & 20 Pin FRC Connector.
Power Supply : 5V/ 2 Amps, ±12V/250mA
Physical Size : 32.6cm x 25.2cm
Operating Temp. : 0 to 50°C.
Included Accessories
26 Pin FRC Cable 3 No
50 Pin FRC Cable 1 No
RS232 Cable 1 No
SMPS Supply 1 No
Jumpers 4 No
Phoenix Connector 1No
Keyboard 1No
Keyboard Adaptor 1No
20PinFRC Cable 1No

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Safety Instructions
Read the following safety instructions carefully before operating the instrument. To avoid
any personal injury or damage to the instrument or any product connected to the instrument.
Do not operate the instrument if suspect any damage to it.
The instrument should be serviced by qualified personnel only.
For your safety:
Use proper Mains cord : Use only the mains cord designed for this instrument. Ensure
that the mains cord is suitable for your country.
Ground the Instrument : This instrument is grounded through the protective earth
conductor of the mains cord. To avoid electric shock, the
grounding conductor must be connected to the earth ground.
Before making connections to the input terminals, ensure that
the instrument is properly grounded..
Use in proper Atmosphere : Please refer to operating conditions given in the manual.
1. Do not operate in wet / damp conditions.
2. Do not operate in an explosive atmosphere.
3. Keep the product dust free, clean and dry.

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Theory
It is a 16 bit microprocessor. 8086 has a 20 bit address bus can access upto 220 memory
locations (1 MB). It can support upto 64K I/O ports. It provides 14, 16-bit registers. It has
multiplexed address and data bus AD0- AD15 and A16 –A19. It requires single phase clock
with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes,
Minimum and Maximum. It can prefetches upto 6 instruction bytes from memory and queues
them in order to speed up instruction execution. It requires +5V power supply. It is a 40 pin
dual in line package.
Minimum and Maximum Modes:
The minimum mode is selected by applying logic 1 to the MN / MX* input pin. This is a
single microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX* input pin. This is a
multi microprocessor configuration.

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Pin diagram of 8086
Internal Architecture of 8086
8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction
fetching, reading and writing operands for memory and calculating the addresses of the
memory operands. The instruction bytes are transferred to the instruction queue. EU executes

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instructions from the instruction system byte queue. Both units operate asynchronously to
give the 8086 an overlapping instruction fetch and execution mechanism which is called as
Pipelining. This results in efficient use of the system bus and system performance. BIU
contains Instruction queue, Segment registers, Instruction pointer, and Address adder. EU
contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
Bus Interface Unit:
It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is
responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetching,
Instruction queuing,
Operand fetch and storage,
Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.This queue permits prefetch of up to six bytes of instruction code. Whenever the
queue of the BIU is not full, it has room for at least two more bytes and at the same time the
EU is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction. These prefetching instructions
are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a
single memory cycle. After a byte is loaded at the input end of the queue, it automatically
shifts up through the FIFO to the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after the other
from the output of the queue. If the queue is full and the EU is not requesting access to
operand in memory, these intervals of no bus activity, which may occur between bus cycles,
are known as idle state.
If the BIU is already in the process of fetching an instruction when the EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus
cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20 bit physical address
that is output on the address bus. This address is formed by adding an appended 16 bit
segment address and a 16 bit offset address.
For example, the physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents of
the instruction pointer IP register.

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The BIU is also responsible for generating bus control signals such as those for memory read
or write and I/O read or write.
Execution Unit:
The Execution unit is responsible for decoding and executing all instructions. The EU
extracts instructions from the top of the queue in the BIU, decodes them, generates operands
if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to
memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction. If the queue is empty, the EU waits
for the next instruction byte to be fetched and shifted to top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions. Whenever this happens, the BIU
automatically resets the queue and then begins to fetch instructions from this new location to
refill the queue.

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Minimum Mode Interface
When the Minimum mode operation is selected, the 8086 provides all control signals needed
to implement the memory and I/O interface. The minimum mode signal can be divided into
the following basic groups: address/data bus, status, control, interrupt and DMA.
Address/Data Bus: These lines serve two functions. As an address bus is 20 bits long and
consists of signal lines A0 through A19. A19 represents the MSB and A0 represents the LSB.
A 20-bit address gives the 8086 a 1Mbyte memory address space.

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More over it has an independent I/O address space which is 64K bytes in length. The 16 data
bus lines D0 through D15 are actually multiplexed with address lines A0 through A15
respectively. By multiplexed we mean that the bus work as an address bus during first
machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 is the
LSB.
When acting as a data bus, they carry read/write data for memory, input/output data for I/O
devices, and interrupt type codes from an interrupt controller.
Status signal:
The four most significant address lines A19 through A16 are also multiplexed but in this case
with status signals S6 through S3. These status bits are output on the bus at the same time
that data are transferred over the other bus lines.
Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal
segment registers is used to generate the physical address that was output on the address bus
during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of the
segment address.
Memory Segment Status Codes

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Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic
level of the internal enable flag. The last status bit S6 is always at the logic 0 level.
Control Signals: The control signals are provided to support the 8086 memory I/O
interfaces. They control functions such as when the bus is to carry a valid address in which
direction data are to be transferred over the bus, when valid write data are on the bus and
when to put read data on the system bus.
ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the
bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
Another control signal that is produced during the bus cycle is BHE i.e. bank high enable.
Logic 0 on this used as a memory enable signal for the most significant byte half of the data
bus D8 through D1. These lines also serve a second function, which is as the S7 status line.
Using the M/IO* and DT/R* lines, the 8086 signals which type of bus cycle is in progress
and in which direction data are to be transferred over the bus. The logic level of M/IO* tells
external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at
this output signals a memory operation and logic 0 an I/O operation. The direction of data
transfer over the bus is signaled by the logic level output at DT/R*. When this line is logic 1
during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data
are either written into memory or output to an I/O device. On the other hand, logic 0 at
DT/R* signals that the bus is in the receive mode. This corresponds to reading data from
memory or input of data from an input port. The signals read RD and write WR indicate that
a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to
intimate external device about valid write or output data are on the bus. On the other hand,
RD indicates that the 8086 is performing a read of data of the bus. During read operations,
one other control signal is also supplied. This is DEN (data enable) and it signals external
devices when they should put data on the bus. There is one other control signal that is
involved with the memory and I/O interface. This is the READY signal. READY signal is
used to insert wait states into the bus cycle such that it is extended by a number of clock
periods. This signal is provided by an external clock generator device and can be supplied by

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the memory or I/O subsystem to signal the 8086 when they are ready to permit the data
transfer to be completed.
Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and
interrupt acknowledge (INTA). INTR is an input to the 8086 that can be used by an external
device to signal that it needs to be serviced. Logic 1 at INTR represents an active interrupt
request. When an interrupt request has been recognized by the 8086, it indicates this fact to
external circuit with pulse to logic 0 at the INTA output. The TEST input is also related to
the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check
the logic level at the TEST input. If the logic 1 is found, the MPU suspend operation and
goes into the idle state. The 8086 no longer executes instructions; instead it repeatedly checks
the logic level of the TEST input waiting for its transition back to logic 0. As TEST switches
to 0, execution resume with the next instruction in the program. This feature can be used to
synchronize the operation of the 8086 to an event in external hardware. There are two more
inputs in the interrupt interface: the non-maskable interrupt NMI and the reset interrupt
RESET. On the 0-to-1 transition of NMI control is passed to a non-maskable interrupt
service routine. The RESET input is used to provide a hardware reset for the 8086. Switching
RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service
routine.
DMA Interface signals: The direct memory access DMA interface of the 8086 minimum
mode consist of the HOLD and HLDA signals. When an external device wants to take
control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At
the completion of the current bus cycle, the 8086 enters the hold state. In the hold state,
signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO*, DT/R*, RD, WR,
DEN and INTR are all in the high Z state. The 8086 signals external device that it is in this
state by switching its HLDA output to logic 1 level.
Maximum Mode Interface: When the 8086 is set for the maximum-mode configuration; it
provides signals for implementing a multiprocessor / coprocessor system environment. By
multiprocessor environment we mean that one microprocessor exists in the system and that
each processor is executing its own program. Usually in this type of system environment,
there are some system resources that are common to all processors. They are called as global
resources. There are also other resources that are assigned to specific processors. These are
known as local or private resources.
Coprocessor also means that there is a second processor in the system. In this, both
processors does not access the bus at the same time. One passes the control of the system bus
to the other and then may suspend its operation. In the maximum-mode 8086 system,
facilities are provided for implementing allocation of global resources and passing bus
control to other microprocessor or coprocessor.

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8086 Maximum Mode Block Diagram
8288 Bus Controller –Bus Command and Control Signals: 8086 does not directly
provide all the signals that are required to control the memory, I/O and interrupt interfaces.
Specially the WR*, M/IO*, DT/R*, DEN, ALE and INTA, signals are no longer produced by
the 8086. Instead it outputs three status signals S0*, S1*, S2* prior to the initiation of each
bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.
S2*S1*S0* are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.
The 8288 chip receive the status signal S2*, S1* and S0* and the clock from 8086. Theses
status signals are decoded to generate MRDC* (Memory read command), MWTC* (memory
write command), IORC* (I/O read command), IOWC* (I/O write command), INTA*
(Interrupt acknowledgement) signal. In addition, it can generate advanced memory and I/O
write signals AMWC* (Advanced memory write command), AIOWC* (Advanced I/O write
command) that are enabled one clock cycle earlier than the normal write control signals
because some device require wider cycle.

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MRDC*
Memory ReaD Command
MWTC*
Memory WriTe Command
IORC*
Input/Output Read Command
IOWC*
Input/Output Write Command
INTA*
INTerrupt Acknowledge
AMWC*
Advanced Memory Write Command
AIOWC*
Advanced Input/Output Write Command
CEN
Command Enable
IOB
Input/output Bus only
MCE/PDEN*
Master Cascade/Peripheral Data Enable
The 8288 also can generate bus control signals DEN, DT/R*, ALE, MCE/ (PDEN)* i.e.
Master Cascade/Peripheral Data Enable. The function of the 1 st three signals are the same as
those in the minimum mode. The signal MCE/ (PDEN)* has 2-functions depending on the
mode in which 8288 is operating. The 8288 can either operate in I/O bus mode or system bus
mode. When CEN (command enable) and IOB (I/O bus) input pin are wired high, the 8288
operate in I/O bus mode. In this mode, the signal PDNE* functions in the same way as DEN
but it is active only during I/O instruction. This facility enables 8288 to control 2 set of
buses: System bus and I/O bus separately
With AEN* (Address enable) and CEN inputs low, the 8288 functions in system bus mode.
When multiple processors are sharing the same bus, active processors can be selected by

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enabling the corresponding 8288 via AEN* input. In this mode, the signal MCE (Master
cascade enable) is used for selecting the appropriate interrupt controller.
Bus Status Codes:
The 8288 produces one or two of these eight command signals for each bus cycles. For
instance, when the 8086 outputs the code S2*S1*S0* equals 001; it indicates that an I/O
read cycle is to be performed. In the code 111 is output by the 8086, it is signaling that no
bus activity is to take place. The control outputs produced by the 8288 are DEN, DT/R* and
ALE. These 3 signals provide the same functions as those described for the minimum system
mode. This set of bus commands and control signals is compatible with the Multibus and
industry standard for interfacing microprocessor systems.
Queue Status Signals: Two new signals that are produced by the 8086 in the maximum-
mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status
code, QS1QS0.
Following table shows the four different queue status.

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Local Bus Control Signal: Request / Grant Signals:
In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also
changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively.
They provide a prioritized bus access mechanism for accessing the local bus.
Minimum Mode 8086 System
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic 1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system.
The remaining components in the system are latches, transreceiver, clock generator, memory
and I/O devices. Some type of chip selection logic may be required for selecting memory or
I/O devices, depending upon the address map of the system. Latches are generally buffered
output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address
from the multiplexed address/data signals and are controlled by the ALE signal generated by
8086. Transreceiver are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals. They are controlled by two signals namely, DEN and DT/R*. The DEN
signal indicates the direction of data, i.e. from or to the processor. The system contains
memory for the monitor and users program storage. Usually, EPROM is used for monitor
storage, while RAM for user‘s program storage. A system may contain I/O devices. The
clock generator generates the clock from the crystal oscillator and then shapes it and divides
to make it more precise so that it can be used as an accurate timing reference for the system.
The clock generator also synchronizes some external signal with the system clock.
It has 20 address lines and 16 data lines; the 8086 CPU requires three octal address latches
and two octal data buffers for the complete address and data separation. The working of the
minimum mode configuration system can be better described in terms of the timing diagrams
rather than qualitatively describing the operations. The opcode fetch and read cycles are
similar. Hence the timing diagram can be categorized in two parts, the first is the timing
diagram for read cycle and the second is the timing diagram for write cycle. The read cycle
begins in T1 with the assertion of address latch enable (ALE) signal and also M/IO* signal.
During the negative going edge of this signal, the valid address is latched on the local bus.
The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO* signal
indicates a memory or I/O operation. At T2, the address is removed from the local bus and is
sent to the output. The bus is then tristated. The read (RD)* control signal is also activated in
T2. The read (RD)* signal causes the address device to enable its data bus drivers. After RD*
goes low, the valid data is available on the data bus. The addressed device will drive the
READY line high. When the processor returns the read signal to high level, the addressed
device will again tristate its bus drivers.

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Read Cycle Timing Diagram for Minimum Mode
A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO* signal is again asserted to indicate a memory or I/O operation. In T2, after sending
the address in T1, the processor sends the data to be written to the addressed location. The
data remains on the bus until middle of T4 state. The WR* becomes active at the beginning
of T2 (unlike RD* is somewhat delayed in T2 to provide time for floating). The BHE and
A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or
write. The M/IO*, RD* and WR* signals indicate the type of data transfer as specified in
table below.

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Write Cycle Timing Diagram for Minimum Mode
Hold Response sequence:
The HOLD pin is checked at leading edge of each clock pulse. If it is received active by the
processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU
activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given
to another requesting master. The control of the bus is not regained by the processor until the
requesting master does not drop the HOLD pin low. When the request is dropped by the
requesting master, the HLDA is dropped by the processor at the trailing edge of the next
clock.