ARM Cortex-A35 Product manual

Arm® Cortex®-A35 Processor
Revision: r1p0
Technical Reference Manual
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved.
100236_0100_00_en

Arm® Cortex®-A35 Processor
Technical Reference Manual
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved.
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Document History
Issue Date Confidentiality Change
0000-00 04 December 2015 Confidential First release for r0p0
0001-00 18 March 2016 Confidential First release for r0p1
0002-00 04 March 2017 Non-Confidential First release for r0p2
0100-00 28 February 2019 Non-Confidential First release for r1p0
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Arm® Cortex®-A35 Processor
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LES-PRE-20349
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Arm® Cortex®-A35 Processor
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Contents
Arm® Cortex®-A35 Processor Technical Reference
Manual
Preface
About this book ..................................................... ..................................................... 20
Feedback .................................................................................................................... 25
Part A Functional Description
Chapter A1 Introduction
A1.1 About the Cortex®-A35 processor .................................... .................................... A1-30
A1.2 Features ................................................................................................................ A1-31
A1.3 Implementation options ............................................ ............................................ A1-32
A1.4 Supported standards and specifications ............................... ............................... A1-34
A1.5 Test features .......................................................................................................... A1-35
A1.6 Design tasks .......................................................................................................... A1-36
A1.7 Product revisions ................................................. ................................................. A1-37
Chapter A2 Technical Overview
A2.1 Components .......................................................................................................... A2-40
A2.2 Interfaces .............................................................................................................. A2-44
A2.3 About system control .............................................. .............................................. A2-46
A2.4 About the Generic Timer ........................................... ........................................... A2-47
A2.5 About the memory model ...................................................................................... A2-48
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Chapter A3 Clocks, Resets, and Input Synchronization
A3.1 Clocks ......................................................... ......................................................... A3-50
A3.2 Input synchronization ............................................................................................ A3-51
A3.3 Resets ......................................................... ......................................................... A3-52
Chapter A4 Power Management
A4.1 Power domains .................................................. .................................................. A4-58
A4.2 Power modes ........................................................................................................ A4-61
A4.3 Core Wait for Interrupt ............................................. ............................................. A4-62
A4.4 Core Wait for Event ............................................... ............................................... A4-63
A4.5 L2 Wait for Interrupt .............................................................................................. A4-64
A4.6 Powering down an individual core .................................... .................................... A4-65
A4.7 Powering up an individual core ...................................... ...................................... A4-66
A4.8 Powering down the processor without system driven L2 flush .............................. A4-67
A4.9 Powering up the processor without system driven L2 flush .................................. A4-68
A4.10 Powering down the processor with system driven L2 flush ................. ................. A4-69
A4.11 Powering up the processor with system driven L2 flush ................... ................... A4-70
A4.12 Entering Dormant mode ........................................................................................ A4-71
A4.13 Exiting Dormant mode ............................................. ............................................. A4-72
A4.14 Event communication using WFE or SEV .............................. .............................. A4-73
A4.15 Communication to the Power Management Controller .................... .................... A4-74
A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals ........................ ........................ A4-75
A4.17 Q-channel .............................................................................................................. A4-76
Chapter A5 Cache Behavior and Cache Protection
A5.1 Cached memory types .......................................................................................... A5-78
A5.2 Coherency between data caches with the MOESI protocol .................................. A5-79
A5.3 Cache misses, unexpected cache hits, and speculative fetches .......................... A5-80
A5.4 Disabling a cache .................................................................................................. A5-81
A5.5 Invalidating or cleaning a cache ............................................................................ A5-82
A5.6 About read allocate mode .......................................... .......................................... A5-83
A5.7 About cache protection ............................................ ............................................ A5-84
A5.8 Error reporting ................................................... ................................................... A5-86
A5.9 Error injection ........................................................................................................ A5-87
Chapter A6 L1 Memory System
A6.1 About the L1 memory system ....................................... ....................................... A6-90
A6.2 TLB Organization .................................................................................................. A6-91
A6.3 Program flow prediction ........................................................................................ A6-92
A6.4 About the internal exclusive monitor .................................. .................................. A6-93
A6.5 About data prefetching .......................................................................................... A6-95
Chapter A7 L2 Memory System
A7.1 About the L2 memory system ....................................... ....................................... A7-98
A7.2 Snoop and maintenance requests ...................................................................... A7-100
A7.3 Support for memory types ......................................... ......................................... A7-101
A7.4 Memory type information exported from the processor ................... ................... A7-102
A7.5 Handling of external aborts ........................................ ........................................ A7-103
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Chapter A8 AXI Master Interface
A8.1 About the AXI master interface ..................................... ..................................... A8-106
A8.2 AXI privilege information .......................................... .......................................... A8-107
A8.3 AXI transactions .................................................................................................. A8-108
A8.4 Attributes of the AXI master interface .................................................................. A8-110
Chapter A9 ACE Master Interface
A9.1 About the ACE master interface .......................................................................... A9-114
A9.2 ACE configurations .............................................................................................. A9-115
A9.3 ACE privilege information .................................................................................... A9-116
A9.4 ACE transactions ................................................ ................................................ A9-117
A9.5 Attributes of the ACE master interface ................................................................ A9-120
A9.6 Snoop channel properties ......................................... ......................................... A9-122
A9.7 AXI compatibility mode ........................................................................................ A9-123
Chapter A10 CHI Master Interface
A10.1 About the CHI master interface .................................... .................................... A10-126
A10.2 CHI configurations .............................................. .............................................. A10-127
A10.3 Attributes of the CHI master interface ............................... ............................... A10-128
A10.4 CHI channel properties .......................................... .......................................... A10-130
A10.5 CHI transactions ................................................................................................ A10-131
Chapter A11 ACP Slave Interface
A11.1 About the ACP ................................................. ................................................. A11-136
A11.2 Transfer size support ............................................ ............................................ A11-137
A11.3 ACP performance .............................................................................................. A11-138
A11.4 ACP user signals ............................................... ............................................... A11-139
Chapter A12 GIC CPU Interface
A12.1 Bypassing the GIC CPU Interface .................................. .................................. A12-142
A12.2 Memory map for the GIC CPU interface ............................. ............................. A12-143
Part B Register Descriptions
Chapter B1 AArch32 system registers
B1.1 AArch32 register summary .................................................................................. B1-150
B1.2 c0 registers .......................................................................................................... B1-152
B1.3 c1 registers .......................................................................................................... B1-155
B1.4 c2 registers .......................................................................................................... B1-156
B1.5 c3 registers .......................................................................................................... B1-157
B1.6 c4 registers .......................................................................................................... B1-158
B1.7 c5 registers .......................................................................................................... B1-159
B1.8 c6 registers .......................................................................................................... B1-160
B1.9 c7 registers .......................................................................................................... B1-161
B1.10 c7 system operations .......................................................................................... B1-162
B1.11 c8 system operations .......................................................................................... B1-165
B1.12 c9 registers .......................................................................................................... B1-167
B1.13 c10 registers ........................................................................................................ B1-168
B1.14 c11 registers ........................................................................................................ B1-169
B1.15 c12 registers ........................................................................................................ B1-170
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B1.16 c13 registers ........................................................................................................ B1-172
B1.17 c14 registers ........................................................................................................ B1-173
B1.18 c15 registers ........................................................................................................ B1-174
B1.19 64-bit registers .................................................................................................... B1-175
B1.20 AArch32 Identification registers ..................................... ..................................... B1-176
B1.21 AArch32 Virtual memory control registers ............................. ............................. B1-178
B1.22 AArch32 Fault handling registers ........................................................................ B1-179
B1.23 AArch32 Other System control registers .............................. .............................. B1-180
B1.24 AArch32 Address registers ........................................ ........................................ B1-181
B1.25 AArch32 Thread registers ......................................... ......................................... B1-182
B1.26 AArch32 Performance monitor registers .............................. .............................. B1-183
B1.27 AArch32 Secure registers ......................................... ......................................... B1-185
B1.28 AArch32 Virtualization registers .......................................................................... B1-186
B1.29 AArch32 GIC system registers ............................................................................ B1-188
B1.30 AArch32 Generic Timer registers ........................................................................ B1-190
B1.31 AArch32 Implementation defined registers ............................ ............................ B1-191
B1.32 Auxiliary Control Register .................................................................................... B1-193
B1.33 Auxiliary Data Fault Status Register ................................. ................................. B1-195
B1.34 Auxiliary ID Register ............................................................................................ B1-196
B1.35 Auxiliary Instruction Fault Status Register ............................. ............................. B1-197
B1.36 Auxiliary Memory Attribute Indirection Register 0 ....................... ....................... B1-198
B1.37 Auxiliary Memory Attribute Indirection Register 1 ....................... ....................... B1-199
B1.38 Configuration Base Address Register ................................ ................................ B1-200
B1.39 Cache Size ID Register ........................................... ........................................... B1-201
B1.40 Cache Level ID Register .......................................... .......................................... B1-204
B1.41 Architectural Feature Access Control Register ......................... ......................... B1-206
B1.42 CPU Auxiliary Control Register ..................................... ..................................... B1-208
B1.43 CPU Extended Control Register .................................... .................................... B1-212
B1.44 CPU Memory Error Syndrome Register .............................................................. B1-214
B1.45 Cache Size Selection Register ............................................................................ B1-217
B1.46 Cache Type Register ............................................. ............................................. B1-219
B1.47 Domain Access Control Register ........................................................................ B1-221
B1.48 Data Fault Address Register ....................................... ....................................... B1-222
B1.49 Data Fault Status Register .................................................................................. B1-223
B1.50 DFSR with Short-descriptor translation table format ..................... ..................... B1-224
B1.51 DFSR with Long-descriptor translation table format ..................... ..................... B1-226
B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00 .............................................. B1-228
B1.53 FCSE Process ID Register .................................................................................. B1-229
B1.54 Hyp Auxiliary Configuration Register ................................. ................................. B1-230
B1.55 Hyp Auxiliary Control Register ............................................................................ B1-231
B1.56 Hyp Auxiliary Data Fault Status Syndrome Register ..................... ..................... B1-233
B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register .................................. B1-234
B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0 ........................................ B1-235
B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1 ........................................ B1-236
B1.60 Hyp Architectural Feature Trap Register .............................. .............................. B1-237
B1.61 Hyp Configuration Register ........................................ ........................................ B1-240
B1.62 Hyp Configuration Register 2 .............................................................................. B1-246
B1.63 Hyp Debug Control Register ....................................... ....................................... B1-248
B1.64 Hyp Data Fault Address Register ........................................................................ B1-251
B1.65 Hyp Instruction Fault Address Register ............................... ............................... B1-252
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B1.66 Hyp IPA Fault Address Register .......................................................................... B1-253
B1.67 Hyp System Control Register .............................................................................. B1-254
B1.68 Hyp Syndrome Register ...................................................................................... B1-258
B1.69 Hyp System Trap Register .................................................................................. B1-259
B1.70 Hyp Translation Control Register ........................................................................ B1-263
B1.71 Hyp Vector Base Address Register .................................. .................................. B1-265
B1.72 Auxiliary Feature Register 0 ................................................................................ B1-266
B1.73 Debug Feature Register 0 ......................................... ......................................... B1-267
B1.74 Instruction Set Attribute Register 0 .................................. .................................. B1-269
B1.75 Instruction Set Attribute Register 1 .................................. .................................. B1-271
B1.76 Instruction Set Attribute Register 2 .................................. .................................. B1-273
B1.77 Instruction Set Attribute Register 3 .................................. .................................. B1-275
B1.78 Instruction Set Attribute Register 4 .................................. .................................. B1-277
B1.79 Instruction Set Attribute Register 5 .................................. .................................. B1-279
B1.80 Memory Model Feature Register 0 ...................................................................... B1-281
B1.81 Memory Model Feature Register 1 ...................................................................... B1-283
B1.82 Memory Model Feature Register 2 ...................................................................... B1-285
B1.83 Memory Model Feature Register 3 ...................................................................... B1-287
B1.84 Processor Feature Register 0 ...................................... ...................................... B1-289
B1.85 Processor Feature Register 1 ...................................... ...................................... B1-291
B1.86 Instruction Fault Address Register ...................................................................... B1-293
B1.87 Instruction Fault Status Register .................................... .................................... B1-294
B1.88 IFSR with Short-descriptor translation table format ...................... ...................... B1-295
B1.89 IFSR with Long-descriptor translation table format ...................... ...................... B1-297
B1.90 Interrupt Status Register .......................................... .......................................... B1-299
B1.91 L2 Auxiliary Control Register ....................................... ....................................... B1-301
B1.92 L2 Control Register .............................................. .............................................. B1-303
B1.93 L2 Extended Control Register ...................................... ...................................... B1-305
B1.94 L2 Memory Error Syndrome Register ................................ ................................ B1-307
B1.95 Memory Attribute Indirection Registers 0 and 1 .................................................. B1-310
B1.96 Main ID Register ................................................ ................................................ B1-313
B1.97 Multiprocessor Affinity Register ..................................... ..................................... B1-315
B1.98 Non-Secure Access Control Register ................................ ................................ B1-317
B1.99 Normal Memory Remap Register ........................................................................ B1-319
B1.100 Physical Address Register .................................................................................. B1-321
B1.101 Primary Region Remap Register .................................... .................................... B1-322
B1.102 Revision ID Register ............................................. ............................................. B1-325
B1.103 Reset Management Register .............................................................................. B1-326
B1.104 Secure Configuration Register ............................................................................ B1-328
B1.105 System Control Register .......................................... .......................................... B1-331
B1.106 Secure Debug Control Register .......................................................................... B1-335
B1.107 Secure Debug Enable Register ..................................... ..................................... B1-337
B1.108 TCM Type Register .............................................. .............................................. B1-339
B1.109 TLB Type Register ............................................... ............................................... B1-340
B1.110 Translation Table Base Control Register .............................. .............................. B1-341
B1.111 TTBCR with Short-descriptor translation table format .................... .................... B1-342
B1.112 TTBCR with Long-descriptor translation table format .................... .................... B1-343
B1.113 Translation Table Base Register 0 ...................................................................... B1-346
B1.114 TTBR0 with Short-descriptor translation table format .................... .................... B1-347
B1.115 TTBR0 with Long-descriptor translation table format .......................................... B1-349
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B1.116 Translation Table Base Register 1 ...................................................................... B1-350
B1.117 TTBR1 with Short-descriptor translation table format .................... .................... B1-351
B1.118 TTBR1 with Long-descriptor translation table format .......................................... B1-353
B1.119 Vector Base Address Register ............................................................................ B1-354
B1.120 Virtualization Multiprocessor ID Register ............................................................ B1-355
B1.121 Virtualization Processor ID Register ................................. ................................. B1-356
B1.122 Virtualization Translation Control Register .......................................................... B1-357
Chapter B2 AArch64 system registers
B2.1 AArch64 register summary .................................................................................. B2-362
B2.2 AArch64 Identification registers .......................................................................... B2-363
B2.3 AArch64 Exception handling registers ................................................................ B2-365
B2.4 AArch64 Virtual memory control registers ............................. ............................. B2-366
B2.5 AArch64 Other System control registers .............................. .............................. B2-368
B2.6 AArch64 Cache maintenance operations ............................................................ B2-369
B2.7 AArch64 TLB maintenance operations ............................... ............................... B2-370
B2.8 AArch64 Address translation operations .............................. .............................. B2-371
B2.9 AArch64 Miscellaneous operations .................................. .................................. B2-372
B2.10 AArch64 Performance monitor registers .............................. .............................. B2-373
B2.11 AArch64 Reset registers .......................................... .......................................... B2-375
B2.12 AArch64 Secure registers ......................................... ......................................... B2-376
B2.13 AArch64 Virtualization registers .......................................................................... B2-377
B2.14 AArch64 EL2 TLB maintenance operations ........................................................ B2-379
B2.15 AArch64 GIC system registers ............................................................................ B2-380
B2.16 AArch64 Generic Timer registers ........................................................................ B2-382
B2.17 AArch64 Thread registers ......................................... ......................................... B2-383
B2.18 AArch64 Implementation defined registers ............................ ............................ B2-384
B2.19 Auxiliary Control Register, EL1 ..................................... ..................................... B2-386
B2.20 Auxiliary Control Register, EL2 ..................................... ..................................... B2-387
B2.21 Auxiliary Control Register, EL3 ..................................... ..................................... B2-389
B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 .................... .................... B2-391
B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 .................... .................... B2-392
B2.24 Auxiliary ID Register, EL1 ......................................... ......................................... B2-393
B2.25 Auxiliary Memory Attribute Indirection Register, EL1 .......................................... B2-394
B2.26 Auxiliary Memory Attribute Indirection Register, EL2 .......................................... B2-395
B2.27 Auxiliary Memory Attribute Indirection Register, EL3 .......................................... B2-396
B2.28 Configuration Base Address Register, EL1 ............................ ............................ B2-397
B2.29 Cache Size ID Register, EL1 ....................................... ....................................... B2-398
B2.30 Cache Level ID Register, EL1 ...................................... ...................................... B2-400
B2.31 Architectural Feature Access Control Register, EL1 ..................... ..................... B2-402
B2.32 Architectural Feature Trap Register, EL2 ............................................................ B2-404
B2.33 Architectural Feature Trap Register, EL3 ............................................................ B2-406
B2.34 Cache Size Selection Register, EL1 ................................. ................................. B2-408
B2.35 Cache Type Register, EL0 ......................................... ......................................... B2-410
B2.36 CPU Auxiliary Control Register, EL1 ................................. ................................. B2-412
B2.37 CPU Extended Control Register, EL1 ................................ ................................ B2-416
B2.38 CPU Memory Error Syndrome Register, EL1 ...................................................... B2-418
B2.39 Domain Access Control Register, EL2 ................................................................ B2-421
B2.40 Data Cache Zero ID Register, EL0 ...................................................................... B2-422
B2.41 Exception Syndrome Register, EL1 .................................................................... B2-423
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B2.42 Exception Syndrome Register, EL2 .................................................................... B2-425
B2.43 Exception Syndrome Register, EL3 .................................................................... B2-427
B2.44 Fault Address Register, EL1 ....................................... ....................................... B2-429
B2.45 Fault Address Register, EL2 ....................................... ....................................... B2-430
B2.46 Fault Address Register, EL3 ....................................... ....................................... B2-431
B2.47 Hyp Auxiliary Configuration Register, EL2 .......................................................... B2-432
B2.48 Hypervisor Configuration Register, EL2 .............................................................. B2-433
B2.49 Hypervisor IPA Fault Address Register, EL2 ........................... ........................... B2-440
B2.50 Hyp System Trap Register, EL2 .......................................................................... B2-441
B2.51 AArch64 Debug Feature Register 0, EL1 ............................................................ B2-444
B2.52 AArch64 Instruction Set Attribute Register 0, EL1 .............................................. B2-446
B2.53 AArch64 Memory Model Feature Register 0, EL1 ....................... ....................... B2-448
B2.54 AArch64 Processor Feature Register 0, EL1 ...................................................... B2-450
B2.55 AArch32 Auxiliary Feature Register 0, EL1 ............................ ............................ B2-452
B2.56 AArch32 Debug Feature Register 0, EL1 ............................................................ B2-453
B2.57 AArch32 Instruction Set Attribute Register 0, EL1 .............................................. B2-455
B2.58 AArch32 Instruction Set Attribute Register 1, EL1 .............................................. B2-457
B2.59 AArch32 Instruction Set Attribute Register 2, EL1 .............................................. B2-459
B2.60 AArch32 Instruction Set Attribute Register 3, EL1 .............................................. B2-461
B2.61 AArch32 Instruction Set Attribute Register 4, EL1 .............................................. B2-463
B2.62 AArch32 Instruction Set Attribute Register 5, EL1 .............................................. B2-465
B2.63 AArch32 Memory Model Feature Register 0, EL1 ....................... ....................... B2-467
B2.64 AArch32 Memory Model Feature Register 1, EL1 ....................... ....................... B2-469
B2.65 AArch32 Memory Model Feature Register 2, EL1 ....................... ....................... B2-471
B2.66 AArch32 Memory Model Feature Register 3, EL1 ....................... ....................... B2-473
B2.67 AArch32 Processor Feature Register 0, EL1 ...................................................... B2-475
B2.68 AArch32 Processor Feature Register 1, EL1 ...................................................... B2-477
B2.69 Instruction Fault Status Register, EL2 ................................ ................................ B2-479
B2.70 IFSR32_EL2 with Short-descriptor translation table format ................................ B2-480
B2.71 IFSR32_EL2 with Long-descriptor translation table format ................ ................ B2-482
B2.72 Interrupt Status Register, EL1 ...................................... ...................................... B2-484
B2.73 L2 Auxiliary Control Register, EL1 ...................................................................... B2-486
B2.74 L2 Control Register, EL1 .......................................... .......................................... B2-489
B2.75 L2 Extended Control Register, EL1 .................................. .................................. B2-491
B2.76 L2 Memory Error Syndrome Register, EL1 ............................ ............................ B2-493
B2.77 Memory Attribute Indirection Register, EL1 ............................ ............................ B2-496
B2.78 Memory Attribute Indirection Register, EL2 ............................ ............................ B2-498
B2.79 Memory Attribute Indirection Register, EL3 ............................ ............................ B2-499
B2.80 Monitor Debug Configuration Register, EL2 ........................................................ B2-500
B2.81 Monitor Debug Configuration Register, EL3 ........................................................ B2-503
B2.82 Monitor Debug System Control Register, EL1 .................................................... B2-506
B2.83 Main ID Register, EL1 ............................................ ............................................ B2-510
B2.84 Multiprocessor Affinity Register, EL1 .................................................................. B2-512
B2.85 Physical Address Register, EL1 .......................................................................... B2-514
B2.86 Revision ID Register, EL1 ......................................... ......................................... B2-518
B2.87 Reset Management Register, EL3 ...................................................................... B2-519
B2.88 Reset Vector Base Address Register, EL3 .......................................................... B2-521
B2.89 Secure Configuration Register, EL3 .................................................................... B2-522
B2.90 System Control Register, EL1 ...................................... ...................................... B2-525
B2.91 System Control Register, EL2 ...................................... ...................................... B2-529
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B2.92 System Control Register, EL3 ...................................... ...................................... B2-532
B2.93 Secure Debug Enable Register, EL3 .................................................................. B2-535
B2.94 Translation Control Register, EL1 ................................... ................................... B2-536
B2.95 Translation Control Register, EL2 ................................... ................................... B2-540
B2.96 Translation Control Register, EL3 ................................... ................................... B2-543
B2.97 Translation Table Base Register 0, EL1 .............................................................. B2-546
B2.98 Translation Table Base Register 1, EL1 .............................................................. B2-548
B2.99 Translation Table Base Register 0, EL3 .............................................................. B2-550
B2.100 Vector Base Address Register, EL1 .................................................................... B2-551
B2.101 Vector Base Address Register, EL2 .................................................................... B2-552
B2.102 Vector Base Address Register, EL3 .................................................................... B2-553
B2.103 Virtualization Multiprocessor ID Register, EL2 .................................................... B2-554
B2.104 Virtualization Processor ID Register, EL2 ............................. ............................. B2-555
B2.105 Virtualization Translation Control Register, EL2 .................................................. B2-556
Chapter B3 GIC registers
B3.1 CPU interface register summary .................................... .................................... B3-560
B3.2 Active Priority Register ........................................................................................ B3-561
B3.3 CPU Interface Identification Register .................................................................. B3-562
B3.4 Virtual interface control register summary ............................. ............................. B3-563
B3.5 VGIC Type Register ............................................................................................ B3-564
B3.6 Virtual CPU interface register summary .............................................................. B3-565
B3.7 VM Active Priority Register ........................................ ........................................ B3-566
B3.8 VM CPU Interface Identification Register ............................................................ B3-567
Chapter B4 Generic Timer registers
B4.1 Generic Timer register summary .................................... .................................... B4-570
B4.2 AArch32 Generic Timer register summary .......................................................... B4-571
B4.3 AArch64 Generic Timer register summary .......................................................... B4-572
Part C Debug
Chapter C1 Debug
C1.1 About debug methods ............................................ ............................................ C1-576
C1.2 Debug access .................................................. .................................................. C1-577
C1.3 Effects of resets on debug registers ................................. ................................. C1-578
C1.4 External access permissions to debug registers ........................ ........................ C1-579
C1.5 Debug events ...................................................................................................... C1-580
C1.6 Debug memory map ............................................. ............................................. C1-581
C1.7 Debug signals .................................................. .................................................. C1-583
C1.8 Changing the authentication signals for debug ......................... ......................... C1-584
Chapter C2 PMU
C2.1 About the PMU .................................................................................................... C2-586
C2.2 External register access permissions to the PMU registers ................................ C2-587
C2.3 Performance monitoring events .......................................................................... C2-588
C2.4 PMU interrupts .................................................................................................... C2-592
C2.5 Exporting PMU events ........................................................................................ C2-593
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Chapter C3 ETM
C3.1 About the ETM .................................................................................................... C3-596
C3.2 Configuration options for the ETM unit and trace resources ............... ............... C3-598
C3.3 Resetting the ETM .............................................................................................. C3-600
C3.4 Programming and reading ETM trace unit registers ..................... ..................... C3-601
Chapter C4 CTI
C4.1 About the cross-trigger ........................................................................................ C4-604
C4.2 Cross-trigger inputs and outputs .................................... .................................... C4-605
Chapter C5 Direct access to internal memory
C5.1 About direct access to internal memory .............................................................. C5-608
C5.2 Encoding for tag and data in the L1 instruction cache ........................................ C5-609
C5.3 Encoding for tag and data in the L1 data cache ........................ ........................ C5-610
C5.4 Encoding for the main TLB RAM .................................... .................................... C5-612
C5.5 Encoding for walk cache .......................................... .......................................... C5-617
C5.6 Encoding for IPA cache ...................................................................................... C5-618
Chapter C6 AArch32 debug registers
C6.1 AArch32 debug register summary ................................... ................................... C6-620
C6.2 Debug Breakpoint Control Registers ................................. ................................. C6-622
C6.3 Debug Watchpoint Control Registers .................................................................. C6-625
C6.4 Debug ID Register .............................................................................................. C6-628
C6.5 Debug Device ID Register ......................................... ......................................... C6-630
C6.6 Debug Device ID Register 1 ....................................... ....................................... C6-632
Chapter C7 AArch64 debug registers
C7.1 AArch64 debug register summary ................................... ................................... C7-634
C7.2 Debug Breakpoint Control Registers, EL1 .......................................................... C7-636
C7.3 Debug Watchpoint Control Registers, EL1 ............................ ............................ C7-639
Chapter C8 Memory-mapped debug registers
C8.1 Memory-mapped debug register summary ............................ ............................ C8-644
C8.2 External Debug Reserve Control Register .......................................................... C8-648
C8.3 External Debug Integration Mode Control Register ............................................ C8-650
C8.4 External Debug Device ID Register 0 ................................ ................................ C8-651
C8.5 External Debug Device ID Register 1 ................................ ................................ C8-652
C8.6 External Debug Processor Feature Register ...................................................... C8-653
C8.7 External Debug Feature Register ................................... ................................... C8-655
C8.8 External Debug Peripheral Identification Registers ...................... ...................... C8-657
C8.9 External Debug Peripheral Identification Register 0 ..................... ..................... C8-658
C8.10 External Debug Peripheral Identification Register 1 ..................... ..................... C8-659
C8.11 External Debug Peripheral Identification Register 2 ..................... ..................... C8-660
C8.12 External Debug Peripheral Identification Register 3 ..................... ..................... C8-661
C8.13 External Debug Peripheral Identification Register 4 ..................... ..................... C8-662
C8.14 External Debug Peripheral Identification Register 5-7 ........................................ C8-663
C8.15 External Debug Component Identification Registers .......................................... C8-664
C8.16 External Debug Component Identification Register 0 .................... .................... C8-665
C8.17 External Debug Component Identification Register 1 .................... .................... C8-666
C8.18 External Debug Component Identification Register 2 .................... .................... C8-667
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C8.19 External Debug Component Identification Register 3 .................... .................... C8-668
Chapter C9 ROM table
C9.1 About the ROM table .......................................................................................... C9-670
C9.2 ROM table register interface ....................................... ....................................... C9-671
C9.3 ROM table register summary .............................................................................. C9-672
C9.4 ROM entry registers ............................................................................................ C9-673
C9.5 ROM Table Peripheral Identification Registers ......................... ......................... C9-677
C9.6 ROM Table Peripheral Identification Register 0 .................................................. C9-678
C9.7 ROM Table Peripheral Identification Register 1 .................................................. C9-679
C9.8 ROM Table Peripheral Identification Register 2 .................................................. C9-680
C9.9 ROM Table Peripheral Identification Register 3 .................................................. C9-681
C9.10 ROM Table Peripheral Identification Register 4 .................................................. C9-682
C9.11 ROM Table Peripheral Identification Register 5-7 ....................... ....................... C9-683
C9.12 ROM Table Component Identification Registers ........................ ........................ C9-684
C9.13 ROM Table Component Identification Register 0 ................................................ C9-685
C9.14 ROM Table Component Identification Register 1 ................................................ C9-686
C9.15 ROM Table Component Identification Register 2 ................................................ C9-687
C9.16 ROM Table Component Identification Register 3 ................................................ C9-688
Chapter C10 PMU registers
C10.1 AArch32 PMU register summary ................................... ................................... C10-690
C10.2 Performance Monitors Control Register ............................................................ C10-692
C10.3 Performance Monitors Common Event Identification Register 0 ...................... C10-695
C10.4 Performance Monitors Common Event Identification Register 1 ...................... C10-699
C10.5 AArch64 PMU register summary ................................... ................................... C10-702
C10.6 Performance Monitors Control Register, EL0 ......................... ......................... C10-704
C10.7 Performance Monitors Common Event Identification Register 0, EL0 .............. C10-707
C10.8 Performance Monitors Common Event Identification Register 1, EL0 .............. C10-711
C10.9 Memory-mapped PMU register summary ............................ ............................ C10-714
C10.10 Performance Monitors Configuration Register .................................................. C10-717
C10.11 Performance Monitors Peripheral Identification Registers ................................ C10-719
C10.12 Performance Monitors Peripheral Identification Register 0 ............... ............... C10-720
C10.13 Performance Monitors Peripheral Identification Register 1 ............... ............... C10-721
C10.14 Performance Monitors Peripheral Identification Register 2 ............... ............... C10-722
C10.15 Performance Monitors Peripheral Identification Register 3 ............... ............... C10-723
C10.16 Performance Monitors Peripheral Identification Register 4 ............... ............... C10-724
C10.17 Performance Monitors Peripheral Identification Register 5-7 ............. ............. C10-725
C10.18 Performance Monitors Component Identification Registers .............................. C10-726
C10.19 Performance Monitors Component Identification Register 0 .............. .............. C10-727
C10.20 Performance Monitors Component Identification Register 1 .............. .............. C10-728
C10.21 Performance Monitors Component Identification Register 2 .............. .............. C10-729
C10.22 Performance Monitors Component Identification Register 3 .............. .............. C10-730
Chapter C11 ETM registers
C11.1 ETM register summary ...................................................................................... C11-733
C11.2 Programming Control Register .......................................................................... C11-736
C11.3 Status Register .................................................................................................. C11-737
C11.4 Trace Configuration Register ...................................... ...................................... C11-738
C11.5 Branch Broadcast Control Register ................................. ................................. C11-740
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C11.6 Auxiliary Control Register .................................................................................. C11-741
C11.7 Event Control 0 Register ......................................... ......................................... C11-743
C11.8 Event Control 1 Register ......................................... ......................................... C11-745
C11.9 Stall Control Register ........................................................................................ C11-746
C11.10 Global Timestamp Control Register .................................................................. C11-747
C11.11 Synchronization Period Register ................................... ................................... C11-748
C11.12 Cycle Count Control Register ............................................................................ C11-749
C11.13 Trace ID Register .............................................................................................. C11-750
C11.14 ViewInst Main Control Register .................................... .................................... C11-751
C11.15 ViewInst Include-Exclude Control Register ........................... ........................... C11-753
C11.16 ViewInst Start-Stop Control Register ................................ ................................ C11-754
C11.17 Sequencer State Transition Control Registers 0-2 ............................................ C11-755
C11.18 Sequencer Reset Control Register ................................. ................................. C11-757
C11.19 Sequencer State Register ........................................ ........................................ C11-758
C11.20 External Input Select Register ..................................... ..................................... C11-759
C11.21 Counter Reload Value Registers 0-1 ................................ ................................ C11-760
C11.22 Counter Control Register 0 ....................................... ....................................... C11-761
C11.23 Counter Control Register 1 ....................................... ....................................... C11-763
C11.24 Counter Value Registers 0-1 ...................................... ...................................... C11-765
C11.25 ID Register 8 .................................................. .................................................. C11-766
C11.26 ID Register 9 .................................................. .................................................. C11-767
C11.27 ID Register 10 ................................................. ................................................. C11-768
C11.28 ID Register 11 .................................................................................................... C11-769
C11.29 ID Register 12 ................................................. ................................................. C11-770
C11.30 ID Register 13 ................................................. ................................................. C11-771
C11.31 Implementation Specific Register 0 ................................. ................................. C11-772
C11.32 ID Register 0 .................................................. .................................................. C11-773
C11.33 ID Register 1 .................................................. .................................................. C11-775
C11.34 ID Register 2 .................................................. .................................................. C11-776
C11.35 ID Register 3 .................................................. .................................................. C11-778
C11.36 ID Register 4 .................................................. .................................................. C11-780
C11.37 ID Register 5 .................................................. .................................................. C11-782
C11.38 Resource Selection Control Registers 2-16 ...................................................... C11-784
C11.39 Single-Shot Comparator Control Register 0 ...................................................... C11-785
C11.40 Single-Shot Comparator Status Register 0 ........................... ........................... C11-786
C11.41 OS Lock Access Register ........................................ ........................................ C11-787
C11.42 OS Lock Status Register ......................................... ......................................... C11-788
C11.43 Power Down Control Register ..................................... ..................................... C11-789
C11.44 Power Down Status Register ............................................................................ C11-790
C11.45 Address Comparator Value Registers 0-7 ............................ ............................ C11-791
C11.46 Address Comparator Access Type Registers 0-7 ...................... ...................... C11-792
C11.47 Context ID Comparator Value Register 0 .......................................................... C11-794
C11.48 VMID Comparator Value Register 0 .................................................................. C11-795
C11.49 Context ID Comparator Control Register 0 ........................... ........................... C11-796
C11.50 Integration ATB Identification Register .............................................................. C11-797
C11.51 Integration Instruction ATB Data Register ............................ ............................ C11-798
C11.52 Integration Instruction ATB In Register .............................................................. C11-799
C11.53 Integration Instruction ATB Out Register ............................. ............................. C11-800
C11.54 Integration Mode Control Register .................................................................... C11-801
C11.55 Claim Tag Set Register .......................................... .......................................... C11-802
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C11.56 Claim Tag Clear Register .................................................................................. C11-803
C11.57 Device Affinity Register 0 .................................................................................. C11-804
C11.58 Device Affinity Register 1 .................................................................................. C11-806
C11.59 Software Lock Access Register .................................... .................................... C11-807
C11.60 Software Lock Status Register .......................................................................... C11-808
C11.61 Authentication Status Register .......................................................................... C11-809
C11.62 Device Architecture Register ...................................... ...................................... C11-810
C11.63 Device ID Register .............................................. .............................................. C11-811
C11.64 Device Type Register ........................................................................................ C11-812
C11.65 ETM Peripheral Identification Registers ............................................................ C11-813
C11.66 ETM Peripheral Identification Register 0 ............................. ............................. C11-814
C11.67 ETM Peripheral Identification Register 1 ............................. ............................. C11-815
C11.68 ETM Peripheral Identification Register 2 ............................. ............................. C11-816
C11.69 ETM Peripheral Identification Register 3 ............................. ............................. C11-817
C11.70 ETM Peripheral Identification Register 4 ............................. ............................. C11-818
C11.71 ETM Peripheral Identification Register 5-7 ........................... ........................... C11-819
C11.72 ETM Component Identification Registers .......................................................... C11-820
C11.73 ETM Component Identification Register 0 ............................ ............................ C11-821
C11.74 ETM Component Identification Register 1 ............................ ............................ C11-822
C11.75 ETM Component Identification Register 2 ............................ ............................ C11-823
C11.76 ETM Component Identification Register 3 ............................ ............................ C11-824
Chapter C12 CTI registers
C12.1 Cross trigger register summary .................................... .................................... C12-826
C12.2 External register access permissions to the CTI registers ................................ C12-828
C12.3 CTI Device Identification Register .................................. .................................. C12-829
C12.4 CTI Integration Mode Control Register .............................. .............................. C12-831
C12.5 CTI Peripheral Identification Registers .............................. .............................. C12-832
C12.6 CTI Peripheral Identification Register 0 ............................................................ C12-833
C12.7 CTI Peripheral Identification Register 1 ............................................................ C12-834
C12.8 CTI Peripheral Identification Register 2 ............................................................ C12-835
C12.9 CTI Peripheral Identification Register 3 ............................................................ C12-836
C12.10 CTI Peripheral Identification Register 4 ............................................................ C12-837
C12.11 CTI Peripheral Identification Register 5-7 ............................ ............................ C12-838
C12.12 CTI Component Identification Registers ............................. ............................. C12-839
C12.13 CTI Component Identification Register 0 .......................................................... C12-840
C12.14 CTI Component Identification Register 1 .......................................................... C12-841
C12.15 CTI Component Identification Register 2 .......................................................... C12-842
C12.16 CTI Component Identification Register 3 .......................................................... C12-843
Part D Appendices
Appendix A Signal Descriptions
A.1 About the signal descriptions ................................... ................................... Appx-A-848
A.2 Processor configuration signals ................................. ................................. Appx-A-849
A.3 Clock signals ................................................................................................ Appx-A-850
A.4 Reset signals ............................................... ............................................... Appx-A-851
A.5 GIC signals .................................................................................................. Appx-A-852
A.6 Generic Timer signals .................................................................................. Appx-A-855
A.7 Power management signals .................................... .................................... Appx-A-856
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A.8 L2 error signals ............................................................................................ Appx-A-858
A.9 ACP interface signals ......................................... ......................................... Appx-A-859
A.10 Broadcast signals for the memory interface ........................ ........................ Appx-A-861
A.11 AXI interface signals .................................................................................... Appx-A-862
A.12 ACE interface signals .................................................................................. Appx-A-864
A.13 CHI interface signals .................................................................................... Appx-A-868
A.14 Debug signals .............................................................................................. Appx-A-871
A.15 APB interface signals ......................................... ......................................... Appx-A-873
A.16 ATB interface signals ......................................... ......................................... Appx-A-874
A.17 ETM signals ................................................ ................................................ Appx-A-875
A.18 PMU interface signals .................................................................................. Appx-A-876
A.19 CTI interface signals .................................................................................... Appx-A-877
A.20 DFT interface signals ......................................... ......................................... Appx-A-878
A.21 MBIST interface signals ....................................... ....................................... Appx-A-879
Appendix B AArch32 UNPREDICTABLE Behaviors
B.1 Use of R15 by Instruction ............................................................................ Appx-B-882
B.2 UNPREDICTABLE instructions within an IT Block ................... ................... Appx-B-883
B.3 Load/Store accesses crossing page boundaries .................... .................... Appx-B-884
B.4 Armv8 Debug UNPREDICTABLE behaviors ....................... ....................... Appx-B-885
B.5 Other UNPREDICTABLE behaviors ............................................................ Appx-B-889
Appendix C Revisions
C.1 Revisions .................................................. .................................................. Appx-C-892
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Preface
This preface introduces the Arm® Cortex® ‑ A35 Processor Technical Reference Manual.
It contains the following:
•About this book on page 20.
•Feedback on page 25.
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About this book
This Technical Reference Manual is for the Cortex®‑A35 processor. It provides reference documentation
and contains programming details for registers. It also describes the memory system, the caches, the
interrupts, and the debug features.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.
Intended audience
This manual is written for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses the Cortex®‑A35 processor.
Using this book
This book is organized into the following chapters:
Part A Functional Description
This part describes the main functionality of the Cortex‑A35 processor.
Chapter A1 Introduction
This chapter provides an overview of the Cortex‑A35 processor and its features.
Chapter A2 Technical Overview
This chapter describes the structure of the Cortex‑A35 processor.
Chapter A3 Clocks, Resets, and Input Synchronization
This chapter describes the clocks of the Cortex‑A35 processor. It also describes the reset options.
Chapter A4 Power Management
This chapter describes the power domains and the power modes in the Cortex‑A35 processor.
Chapter A5 Cache Behavior and Cache Protection
This chapter describes the CPU and SCU cache protection features of the Cortex‑A35 processor.
Chapter A6 L1 Memory System
This chapter describes the L1 instruction cache and data cache.
Chapter A7 L2 Memory System
This chapter describes the L2 memory system and the Snoop Control Unit (SCU) that is tightly
integrated with it.
Chapter A8 AXI Master Interface
This chapter describes the AXI master memory interface.
Chapter A9 ACE Master Interface
This chapter describes the ACE master interface.
Chapter A10 CHI Master Interface
This chapter describes the CHI master memory interface.
Chapter A11 ACP Slave Interface
This chapter describes the ACP slave interface.
Chapter A12 GIC CPU Interface
This chapter describes the Generic Interrupt Controller (GIC) CPU interface of the processor.
Part B Register Descriptions
This part describes the non-debug registers of the Cortex‑A35 processor.
Preface
Product revision status
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