NXP Semiconductors MC9S08LC60 User manual

Freescale Semiconductor
Application Note
Document Number: AN3280
Rev. 0, 07/2006
Contents
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1 MC9S08LC60 Introduction
The MC9S08LC60 is an HCS08 device that combines a
liquid crystal display (LCD) driver module with a rich
set of peripherals. This high level of integration reduces
the total system cost by providing a single chip solution
for applications needing a display with up to 160
segments. LCDs are commonplace in many applications,
including thermostats, calculators, digital multi-meters,
medical monitoring devices, toys, and appliances.
The LCD module integration in the MC9S08LC60
provides a high-level of configurability allowing for
lower power operation. In fact, the LCD driver can be
configured to operate a display even when the
MC9S08LC60 enters stop3 sleep mode. Figure 1
provides a block diagram of the MC9S08LC60. In
addition to the built-in LCD driver, the MC9S08LC60
has notable peripherals such as a 12-bit ADC and dual
Flash arrays (for EEPROM emulation), as shown in the
block diagram.
1 MC9S08LC60 Introduction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Type of LCD Glass Compatible with MC9S08LC60 2
1.2 Number of Segments and Using Segments in LCD 3
1.3 LCD Glass Specification . . . . . . . . . . . . . . . . . . . . . 4
2 LCD Module Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 LCD Module Power Supply Configuration. . . . . . . . 4
2.2 LCD Module Clock. . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 LCD Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Interfacing the LCD MCU to an LCD Glass . . . . . . . . . . . 7
3.1 LCD Glass Detailed Description . . . . . . . . . . . . . . . 8
3.2 Mapping LCD Glass Segments to the MCU LCD
RAM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Mapping the MCU LCD RAM to Alphanumeric
Segment Groups . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Example Application Using the DEMO9S08LC60 . . . . . 16
4.1 DEMO9S08LCD60 Overview and Configuration. . 17
4.2 Example Application Software Overview. . . . . . . . 18
4.3 Example Application Operation and Quick Start . . 25
Interfacing an LCD to the
MC9S08LC60
by: Steven Torres
Austin, TX, USA

Interfacing an LCD to the MC9S08LC60, Rev. 0
MC9S08LC60 Introduction
Freescale Semiconductor2
Figure 1. MC9S08LC60 Block Diagram
This application note introduces the MC9S08LC60 and details a procedure for interfacing a LCD glass to
the MC9S08LC60 from a hardware and software perspective. Using the DEMO9S08LC60 EVB hardware,
the relationship between the LCD glass segments and the individual bits in the MC9S08LC60 LCDRAM
registers is demonstrated. The demo validates that the LCD glass was properly interfaced to the
MC9S08LC60.
Sample software to illustrate a basic application that uses a LCD is included in this document. The
document contains both an overview of the demo software and a quickstart for the demo. All code for the
demo is provided in the file AN3280SW1.zip, which can be found on the Freescale web page
(freescale.com).
1.1 Type of LCD Glass Compatible with MC9S08LC60
Two common LCD types are TN (twisted nematics) and STN (super twisted nematics). TN-type LCD
glass is very cost-effective and is compatible with multiplexing LCD drivers using fewer than 16
backplanes. The multiplexing LCD driver uses multiple backplanes to reduce the number of connections
between the LCD and the LCD driver. Using multiplexing, each frontplane pin can be connected to as
many segments as there are backplanes. With up to four backplanes and running in 1/3 bias mode, the
MC9S08LC60 is compatible with TN-type LCD glass.
9S08 CPU
Dual Flash
Arrays
RAM
RTI
Internal
Clock
Generator
BDM
KBI
12-Bit ADC
SCI
(2) SPI
I2C
(2) 16-Bit
Timers
LCD Driver
4/3 BP)
80/64 Pin Package
(40/41 FP x

MC9S08LC60 Introduction
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 3
The multiplexing configuration relates to the LCD duty cycle. The duty cycle indicates the amount of time
the LCD panel segment is energized during each LCD module frame cycle. The available duty cycle
options for the MC9S08LC60 LCD module are 1/2, 1/3, and 1/4. The denominator of the duty cycle
indicates the number of backplanes being used to drive a LCD panel.
This application note does not provide an introduction to LCD theory, types of LCD, LCD waveforms, or
principles of operation. AN3219, XGATE Library: TN/STN LCD Driver, provides a detailed description
of driving TN and STN LCDs using general-purpose input/output (GPIO) pins. Even though the
MC9S08LC60 has a built-in LCD driver module, the discussions presented in AN3219 on multiplex
waveforms and LCD theory are relevant.
1.2 Number of Segments and Using Segments in LCD
Depending on package and LCD configuration, the MC9S08LC60 can support up to 160 segments. The
number of segments is equal to the number of backplanes times the number of frontplanes. With multiplex
LCD drivers like the MC9S08LC60, each frontplane pin can be connected to as many segments as there
are backplanes. With up to 160 segments, the MC9S08LC60 can be used in displays that are numeric,
alpha-numeric, symbolic, or a combination of these. Numeric displays require seven segments for each
digit; alpha-numeric displays require either 14 or 16 segments per character. Table 1 lists the available
configurations and the potential number of digits when using a 7-, 14-, or 16-segment configuration.
Table 1. 9S08LC60 Segment Configuration Based on Package
Package Number of
Backplanes
Number of
Frontplanes
Total Number of
Segments
Potential Number of Characters (Remainder)
7 segment 14 segment 16 segment
64 pin 4 32 128 18 (2) 9 (2) 8 (0)
3 33 99 14 (1) 7 (1) 6 (3)
80 pin 4 40 160 22 (6) 11 (6) 10 (0)
3 41 123 17 (4) 8 (11) 7 (11)

Interfacing an LCD to the MC9S08LC60, Rev. 0
LCD Module Overview
Freescale Semiconductor4
1.3 LCD Glass Specification
When obtaining TN-type LCD glass for an application, several parameters should be considered. These
include:
• LCD operating voltage — Typical values for LCD glass operating voltage are 3 V or 5 V. The
operating voltage is the nominal voltage level threshold to power on a segment.
• Current consumption — The current consumption is related to the total segment area.
• View area — This is related to the size of the LCD glass.
• Driving mode — Duty cycle (1/2, 1/3, and 1/4) and bias (1/3)
• View angle — 3 o’clock, 6 o’clock, 9 o’clock, and 12 o’clock
• View mode — Reflective, transmissive, and transflective
• Operating temperature — Varies
2 LCD Module Overview
2.1 LCD Module Power Supply Configuration
The LCD module provides several configurations for its power supply. The LCD module can be powered
via VDD or, alternatively, by an external LCD power supply connected to the VLCD pin (the VLCD voltage
range is 1.4 to 1.8 V). The LCD module power supply configuration is determined by the VSUPPLY[1:0]
bit field. A block diagram of the power supply architecture is shown in Figure 2. The designer must choose
from one of the power modes shown in Figure 2. This decision will be based on application requirements.
Figure 2. LCD Module Power Supply Configuration Options
+
–
R1
R1
R1
— (~(LCDCPMS) and powersw3)
~(LCDCPMS)
~(LCDCPMS) (BBYPASS
VLL1
(~(BBYPASS)
VOLTAGE DIVIDER
BLOCK
VLCD
VDD
powersw1 —
— powersw2
VLL1
VLL2
VLL3
CHARGE PUMP
and powersw3)
and powersw3)
VSUPPLY[1:0] powersw1 powersw2 powersw3
00 100
01 010
10 001
11 000

LCD Module Overview
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 5
Another factor affecting power supply configuration has to do with the LCD glass panel. Typical driving
voltages for LCD glass panels are 3 V and 5 V. The subsequent sections summarize power supply
configuration options when driving both 3 V and 5 V LCD glass.
2.1.1 Configuration Options for 3 V LCD Glass
When driving 3 V LCD glass, the following configurations are available:
• Power the LCD module via VLCD, where VLCD is nominally 1.5 volts, with the LCD module
configured for doubler mode.
• Power the LCD module via VDD, where VDD is nominally 3 V, with the LCD module voltage
supply switch (VSUPPLY[1:0]) configured to generate VLL3 from VDD
• Power the LCD module via VDD, where VDD is nominally 2 V, with the LCD module voltage
supply switch (VSUPPLY[1:0]) configured to generate VLL2 from VDD
2.1.2 Configuration Options for 5 V LCD Glass
When driving 5 V LCD glass, the following configurations are available:
• Power LCD module via VLCD, where VLCD is nominally 1.67 volts, with the LCD module
configured for tripler mode.
• Power the LCD module via VDD, where VDD is nominally 3.3 volts, with the LCD module voltage
supply switch (VSUPPLY[1:0]) configured to generate VLL2 from VDD
2.2 LCD Module Clock
Figure 3 illustrates the MC9S08LC60 clock source, which can either be sourced from the MC9S08LC60
internal clock reference or an external clock source. The LCD module is designed to operate using a
32.768 kHz clock regardless of clock source, so clock dividers must be used to achieve the target
32.768 kHz clock target. In Figure 3, the 32.768 kHz clock target is labeled LCDCLK. LCDCLK is used
to determine the following LCD operational settings:
• LCD base frequency
• LCD blink rate
• LCD charge pump rate

Interfacing an LCD to the MC9S08LC60, Rev. 0
LCD Module Overview
Freescale Semiconductor6
Figure 3. LCD Module Clock Tree
2.2.1 External Crystal and the LCD Frame Frequency
The lowest-power configuration for the MC9S08LC60 uses the external clock. It is also advantageous to
select the slowest acceptable clock rate for the LCD base frequency, the LCD frame frequency, and the
LCD charge pump rate that supports the LCD glass in the application. Reducing the clock rate reduces the
current consumption of the LCD module.
2.3 LCD Blinking
One of the most outstanding features of the MC9S08LC60 is the flexible support for segment blinking.
Some features of the segment blinking implementation are:
• Blink capability is programmable for the entire display or individual segments
• Multiple programmable options for the blink rate are available
• Blink functionality is available in stop3 mode
The LCDDRMS bit in the LCDCMD register is used in conjunction with the LCDRAM registers to
provide blinking control for individual segments. If the LCDDRMS bit is cleared, the LCDRAM registers
control the display on/off state for segments on the LCD display. If LCDDRMS bit is set, the LCDRAM
registers control the blink enable on/off state for the corresponding segment. See Section 4.2.3.2.1,
“Non-alphanumerics,” for example software functions that use the LCDDRMS bit to toggle the LCDRAM
between its function to control the display on/off state and to control blink enable on/off state.
To configure all LCD segments to blink regardless of the contents of the LCDRAM registers while the
LCDDRMS bit is set, the BLKMODE bit in the LCDBCTL control register must also be set.
Internal Clock
External Clock = 32.768 kHz
Source
÷16
DIV16
÷(1+CLKADJ[5:0])
CLKADJ[5:0]
LCDCLK
÷8÷(2LCLK[2:0])
LCLK[2:0]
÷2
LCD Charge Pump Clock
Source
CPCADJ[1:0] LCD Base Frequency
Source
Blink Rate
Source
BRATE[2:0]
÷2(1+CPCADJ[1:0])
÷6
÷(25+BRATE[2:0])
÷2

Interfacing the LCD MCU to an LCD Glass
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 7
3 Interfacing the LCD MCU to an LCD Glass
This application uses the DEMOLC60 EVB to detail the requirements for interfacing an LCD glass to the
MC9S08LC60. Figure 4 shows the top layer silk screen of the DEMO9S08LC60 with the LCD glass
panel. The LCD glass panel is shown with all LCD segments turned on. This section will review the LCD
glass design in detail and discuss the interfacing of the LCD module to the LCD glass via hardware and
software.
Figure 4. DEMO9S08LC60

Interfacing an LCD to the MC9S08LC60, Rev. 0
Interfacing the LCD MCU to an LCD Glass
Freescale Semiconductor8
3.1 LCD Glass Detailed Description
The LCD panel used in the DEMO9S08LC60 has a viewable area of approximately 75 mm ×25 mm and
is shown in Figure 5. It is a custom 160-segment LCD TN-type glass that combines nine individual
alphanumeric segment groups with numerous individual segments in the form of labels, punctuation,
icons, etc. The alphanumeric segment groups are labeled 1 to 9 starting from the leftmost character
position. The LCD panel is manufactured by S-Tek Displays (part number GD3980P).
Figure 5. Custom LCD from S-Tek Displays
The LCD panel’s segment layout is not the only important aspect of its design. Other LCD glass
specifications, such as those mentioned in Section 1.1, also dictate how the LCD glass must be driven by
an LCD driver for optimal performance. Table 2 provides a summary of GD3980P parameters.
Table 2. GD3890P Parameters
GD3890P Parameters Units Values
Driving Voltage Volts 3
Duty 1/4
Driving Frequency Hz 64
Operating Temperature C 0-50
Display Mode Positive, Reflective
Viewing Angle o’clock 6

Interfacing the LCD MCU to an LCD Glass
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 9
Figure 6 shows all 160 segments labeled individually. This information is provided by the LCD
manufacturer. See the appendix for the full GD3980P specification for S-Tek Displays.
Figure 6. Segment Labels

Interfacing an LCD to the MC9S08LC60, Rev. 0
Interfacing the LCD MCU to an LCD Glass
Freescale Semiconductor10
Table 3 lists the LCD glass pin out along with each of the 160 segment labels. The LCD glass has a total
of 44 pins, including four pins for backplane connections and 40 for frontplane connections.
Table 3. LCD Pin-Out Specification
PIN COM1 COM2 COM3 COM4 PIN COM1 COM2 COM3 COM4
1 COM1 — — — 23 9K 9L 9D COL4
2 — COM2 — — 24 9B 9C DT9 V1
3 — — COM3 — 25 V2 AM PM OM
4 — — — COM4 26 KWh Amps Volts Program
5 1H 1F 1E 1N 27 VOL V3 V4 V5
6 1A1J1G1M 28T4T3T2T1
71K1L1DTIME 296B6CDT6T
8 1B 1C DT1 DT 30 6K 6L 6D K3
92H2F2E2N 316A6J6G6M
10 2A 2J 2G 2M 32 6H 6F 6E 6N
11 2K 2L 2D DATE 33 5B 5C COL2 DT5
12 2B 2C COL1 DT2 34 5K 5L 5D VOLUME
13 7H 7F 7E 7N 35 5L 5J 5G 5M
14 7A 7J 7G 7M 36 5H 5F 5E 5N
15 7K 7L 7D P 37 4B 4C DT4 K2
16 7B 7C COL3 DT7 38 4K 4L 4D TEMP
17 8H 8F 8E 8N 39 4A 4J 4G 4M
18 8A 8J 8G 8M 40 4H 4F 4E 4N
19 8K 8L 8D CONTRAST 41 3B 3C DT3 K1
20 8B 8C DT8 MODE 42 3K 3L 3D K
21 9H 9F 9E 9N 43 3A 3J 3G 3M
22 9A 9J 9G 9M 44 3H 3F 3E 3N

Interfacing the LCD MCU to an LCD Glass
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 11
3.2 Mapping LCD Glass Segments to the MCU LCD RAM Registers
After the relationship between the individual segments and the LCD pins is understood, the relationship
between the LCD pins and the MCU pins and MCU LCD RAM registers needs to be established. The
MCU and LCD pins are wired together, making sure that the respective backplane and frontplane pins are
matched. Figure 7 shows connections between the GP3980P and the MC9S08LC60 for the
DEMO9S08LC60.
Figure 7. MCU-to-LCD pin connections
With the MCU pins connected to the LCD glass pins, a simple relationship between the LCD display
segments and the MCU LCD RAM registers can be established. The mapping is determined by both the
MCU-to-LCD pin connections (Figure 7) and the LCD pin out specification (Table 3). Each bit in the
MCU RAM registers is mapped to an individual segment on the LCD glass.
Table 4 shows the MCU LCD RAM registers, where the individual bits are labelled FPxBPy. Figure 7
shows both the “BPy” and the “FPx” relationships between the MCU pinout and LCD panel pins. For
example:
• BP3 is connected to the LCD pin 4. (It is important to note this is COM4.)
• FP15 is connected to LCD pin 37.
BP0
BP1
BP2
BP3
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP24
FP25
FP26
FP27
FP28
FP29
FP30
FP31
FP32
FP33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
FP8
FP9
FP10
FP11
FP12
FP13
FP14
FP15
FP16
FP17
FP18
FP19
FP20
FP21
FP22
FP23
FP39
FP38
FP37
FP36
FP35
FP34
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

Interfacing an LCD to the MC9S08LC60, Rev. 0
Interfacing the LCD MCU to an LCD Glass
Freescale Semiconductor12
Using this information and Table 3 (for COM4 and LCD pin 37), one finds that FP15BP3 is connected to
the label “K2.” Using Figure 6, the label “K2” is associated with the snowflake icon segment. Using this
approach, all the relationships between the LCD display segments and the MCU LCD RAM registers can
be established. Powering individual segments on and off is a matter of toggling the correct bit associated
with the segment. For example, when the FP15BP3 bit is set to 1, the corresponding segment (the snow
flake icon) will become visible on the LCD glass. When the FP15BP3 bit is set to 0, the segment is not
displayed.
3.3 Mapping the MCU LCD RAM to Alphanumeric Segment Groups
Using the procedure above, turning individual segments on and off is very straightforward. For the
alphanumeric displays (the DEMO9S08LC60 contains 13-segment displays), the procedure is basically
the same except that individual segments are grouped and modified together depending on the
alphanumeric character that is specified to be activated in the display.
Table 4. MCU LCD RAM
0x1848 LCDRAM0 FP1BP3FP1BP2FP1BP1FP1BP0FP0BP3FP0BP2FP0BP1FP0BP0
0x1849 LCDRAM1 FP3BP3FP3BP2FP3BP1FP3BP0FP2BP3FP2BP2FP2BP1FP2BP0
0x184A LCDRAM2 FP5BP3FP5BP2FP5BP1FP5BP0FP4BP3FP4BP2FP4BP1FP4BP0
0x184B LCDRAM3 FP7BP3FP7BP2FP7BP1FP7BP0FP6BP3FP6BP2FP6BP1FP6BP0
0x184C LCDRAM4 FP9BP3FP9BP2FP9BP1FP9BP0FP8BP3FP8BP2FP8BP1FP8BP0
0x184D LCDRAM5 FP11BP3FP11BP2FP11BP1FP11BP0FP10BP3FP10BP2FP10BP1FP10BP0
0x184E LCDRAM6 FP13BP3FP13BP2FP13BP1FP13BP0FP12BP3FP12BP2FP12BP1FP12BP0
0x184F LCDRAM7 FP15BP3FP15BP2FP15BP1FP15BP0FP14BP3FP14BP2FP14BP1FP14BP0
0x1850 LCDRAM8 FP17BP3FP17BP2FP17BP1FP17BP0FP16BP3FP16BP2FP16BP1FP16BP0
0x1851 LCDRAM9 FP19BP3FP19BP2FP19BP1FP19BP0FP18BP3FP18BP2FP18BP1FP18BP0
0x1852 LCDRAM10 FP21BP3FP21BP2FP21BP1FP21BP0FP20BP3FP20BP2FP20BP1FP20BP0
0x1853 LCDRAM11 FP23BP3FP23BP2FP23BP1FP23BP0FP22BP3FP22BP2FP22BP1FP22BP0
0x1854 LCDRAM12 FP25BP3FP25BP2FP25BP1FP25BP0FP24BP3FP24BP2FP24BP1FP24BP0
0x1855 LCDRAM13 FP27BP3FP27BP2FP27BP1FP27BP0FP26BP3FP26BP2FP26BP1FP26BP0
0x1856 LCDRAM14 FP29BP3FP29BP2FP29BP1FP29BP0FP28BP3FP28BP2FP28BP1FP28BP0
0x1857 LCDRAM15 FP31BP3FP31BP2FP31BP1FP31BP0FP30BP3FP30BP2FP30BP1FP30BP0
0x1858 LCDRAM16 FP33BP3FP33BP2FP33BP1FP33BP0FP32BP3FP32BP2FP32BP1FP32BP0
0x1859 LCDRAM17 FP35BP3FP35BP2FP35BP1FP35BP0FP34BP3FP34BP2FP34BP1FP34BP0
0x185A LCDRAM18 FP37BP3FP37BP2FP37BP1FP37BP0FP36BP3FP36BP2FP36BP1FP36BP0
0x185B LCDRAM19 FP39BP3FP39BP2FP39BP1FP39BP0FP38BP3FP38BP2FP38BP1FP38BP0
0x185C LCDRAM20 0000FP40BP3FP40BP2FP40BP1FP40BP0

Interfacing the LCD MCU to an LCD Glass
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 13
3.3.1 GP3890P Alphanumeric Segment Groups
The alphanumeric segment group for the DEMO9S08LC60 is a modified version of a standard 14-segment
display group. This custom segment group for alphanumeric displays in the GP3890P LCD glass, shown
in Figure 8, uses only 13 segments. The difference between this group and a standard 14-segment group
is the single segment “G”, which normally consists of two segments of equal size. The GP3890P has a total
of nine 13-segment displays. Referencing Figure 6, the leftmost 13-segment display group is the first
position. With a 13-segment display layout, each alphanumeric character will require 13 bits of MCU LCD
RAM.
Figure 8. GP3980P Custom 13-Segment Display Layout Pattern
3.3.2 Alphanumeric Segment Group MCU LCD RAM Mapping
This section gives an example of the mapping of an alphanumeric segment group for the leftmost
13-segment display (position 1) on the GP3890P to display the letter “M”. Figure 9 shows the layout of
the 13-segment display, an excerpt from the LCD pinout specification table, and the pinout connections
between the MCU and the LCD glass. Table 5 shows the corresponding MCU LCD RAM registers. Note
that two adjacent MCD LCD RAM registers, LCDRAM1 and LCDRAM0, are used for the 13-segment
alpha numeric segment group.
BF
A
HJK
G
ENMLC
D

Interfacing an LCD to the MC9S08LC60, Rev. 0
Interfacing the LCD MCU to an LCD Glass
Freescale Semiconductor14
Figure 9. Example Mapping MCU LCD RAM to LCD Glass Alphanumeric Segment Groups
In Table 5, the MCU LCD RAM registers are shown with both the bit names and the corresponding labels
from Figure 6. The register bits values in Table 5 are provided for the display of the alphanumeric
character “M” in the LCD display. A value of “X” in the table is provided for the bit locations where the
value is not associated with the 13-segment display. For these locations, the bit value is irrelevant. In this
case (for alphanumeric characters in character position 1), these are the bits for the labels “TIME”, “DT”,
and “DT1”. Table 6 provides a more detailed tabular form of the decoding from MCU pins to LCD
segments.
Table 5. LCD RAM Values for the Leftmost GD3890P Alphanumeric Character to Display an “M”
LCDRAM0 FP1BP3
“1M”
FP1BP2
“1G”
FP1BP1
“1J”
FP1BP0
“1A”
FP0BP3
“1N”
FP0BP2
“1E”
FP0BP1
“1F”
FP0BP0
“1H”
10110110
LCDRAM1
FP3BP3
“DT”
FP3BP2
“DT1”
FP3BP1
“1C”
FP3BP0
“1B”
FP2BP3
“TIME”
FP2BP2
“1D”
FP2BP1
“1L”
FP2BP0
“1K”
XX1 1X000
BF
A
HJK
G
EN
MLC
D
PIN
COM1
COM2
COM3
COM4
5678
1H 1A 1K 1B
1F 1J 1L 1C
1E 1G 1D DT1
1N 1M TIME DT
5
6
7
8
FP0
FP1
FP2
FP3
LCD401

Interfacing the LCD MCU to an LCD Glass
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 15
The same mapping approach can be used for the remaining alphanumeric character positions. An
important observation is that the other character positions follow the MCU LCD RAM mapping
organization and layout pattern (see Figure 8) using two adjacent registers. The shaded bit locations in
Table 6 are used arbitrarily for all other segments not used in an alphanumeric group. Table 7 lists the
MCU LCD RAM registers used for alphanumeric groups 1–9 (LCDRAM[0:17], respectively). The
LCDRAM[18:19] registers are not used for alphanumeric groups. LCDRAM20 is not used at all because
FP40 is not used in 1/4 duty mode. In 1/4 duty mode, the multiplexed BP3/FP40 pin is configured as BP3.
Table 6. Detailed Alphanumeric Segment Mapping
MCU Pin
Function
MCU Pin #
in 80 Pin
Package
MCU Pin #
in 64 Pin
Package
LCD Pin
LCD Segment / MCU LCD RAM Bit
COM1/BP0 COM2/BP1 COM3/BP2 COM4/BP3
FP0 7 6 5 1H/FP0BP0 1F/FP0BP1 1E/FP0BP2 1N/FP0BP3
FP1 6 5 6 1A/FP1BP0 1J/FP1BP1 1G/FP1BP2 1M/FP1BP3
FP2 5 4 7 1K/FP2BP0 1L/FP2BP1 1D/FP2BP2 TIME/FP2BP3
FP3 4 3 8 1B/FP3BP0 1C/FP3BP1 DT1/FP3BP2 DT/FP3BP3
Table 7. MCU LCD RAM Registers for Alphanumeric Groups
Alphanumeric
Segment Group MCU LCD RAM
1 LCDRAM0
LCDRAM1
2 LCDRAM2
LCDRAM3
3 LCDRAM4
LCDRAM5
4 LCDRAM6
LCDRAM7
5 LCDRAM8
LCDRAM9
6 LCDRAM10
LCDRAM11
7 LCDRAM12
LCDRAM13
8 LCDRAM14
LCDRAM15
9 LCDRAM16
LCDRAM17

Interfacing an LCD to the MC9S08LC60, Rev. 0
Example Application Using the DEMO9S08LC60
Freescale Semiconductor16
4 Example Application Using the DEMO9S08LC60
This section provides a brief description of a basic software demo using the DEMO9S08LC60
demonstration board which uses the MC9S08LC60. Figure 10 shows the a photo of the DEMO9S08LC60
Example Application.
Figure 10. DEMO9S08LC60 Example Application
The demo captures alphanumeric data from SCI0 and then displays the data on the LCD display.
Alphanumeric data can be transmitted to MC9S08LC60’s SCI0 using a PC and a COM terminal program
(such as Hyperterminal or Tera Term). Other features of the demo are:
• Demonstrates the usage of an MC9S08LC60 with a 32.768 kHz external crystal clock source
— Demonstrates configuration of the ICG
• Demonstrates the reception of data via SCI0
— Demonstrates configuration of the SCI0 baud rate
• Demonstrates the usage of the LCD modules
— Demonstrates the LCD module power configuration to drive the GP3890P (3 volts LCD glass)
— Demonstrates the LCD module clock configuration
— Demonstrates the LCD module segment blinking
— Demonstrates the LCD module driving of alphanumeric characters
• Demonstrates the reception of data via SCI0
• Demonstrates the use of GPIO
— LEDs toggle when user presses buttons

Example Application Using the DEMO9S08LC60
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 17
All the software for the basic demo is provided as a companion to this application note and can be
downloaded from the Freescale web site. The file name is AN3280SW1.zip. Use the software at your own
risk. The software is provided “as-is,” with no warranties, guarantees, or support.
NOTE
Out of box, the DEMO9S08LC60 comes preprogrammed with an LCD
demo. This preprogrammed demo application is provided by SofTech
Microsystems and it is operational when the DEMO9S08LC60 is powered.
The SofTech Microsystems demo and the demo described in this
application note, though having similar functions, have slightly different
source code implementations. The SofTech Microsystems demo source
code is provided on a CD in the DEMO9S08LC60 kit.
4.1 DEMO9S08LCD60 Overview and Configuration
The DEMO9S08LC60 (see Figure 4) is a full-featured customer evaluation PCB with a built-in
USB-to-BDM programmer. Besides providing a programming interface, the USB cable can also be used
to power the device.
The DEMO9S08LC60 has the following user interface elements:
• LEDs
• Buttons
• Potentiometer
• Serial port
• Photo cell
• Temp sensor
•Speaker
• 3-Axis accelerometer
For this demo, the DEMO9S08LC60 must be configured with the jumper positions given in Table 8.
Table 8. DEMO9S08LC60 Configuration for Example Application
Jumper(s) Setting
LED EN all ON
IO1 ENA all ON
IO2 ENA all ON
PTA7 SEL LED
CLK ENA all ON
POWER SEL USB
g-Sel1 don’t care
g-Sel1 don’t care
g-Sleep Mode don’t care

Interfacing an LCD to the MC9S08LC60, Rev. 0
Example Application Using the DEMO9S08LC60
Freescale Semiconductor18
4.2 Example Application Software Overview
This section provides an overview of the configuration of the example application demo. The overview
reviews settings for:
•ICG
•SCI
•LCD
These LCD drivers are a subset of the application. The application could be an energy meter or a toy.
The goal of this section is not to describe every function in detail. Instead, only select functions will be
described. For example, a description will be provided for the implementation of a procedure for the
mapping of the MCU LCD RAM to alphanumeric segment groups as described in the previous section.
4.2.1 ICG Configuration
The ICG has four possible configurations, including the following three modes:
• FLL bypassed, external clock (FBE) mode
• FLL engaged, internal clock (FEI) mode
• FLL engaged, external clock (FEE) mode
Both FBE and FEE use the on-board 32.768 kHz crystal on the DEMO9S08LC60. For these modes, the
DEMO9S08LC60 CLK ENA jumper must be installed. For the lowest power mode, the FBE mode is
recommended. If the use of the LCD in stop3 is desired, FBE mode is also recommended. If lower
system/BOM (bill of materials) cost is the priority, the FEI mode should be used. Cpu.h defines variables
to select the desired ICG clock mode.
While the demo software is pre-configured to use the ICG FBE mode, the demo project can be modified
so that the user can also operate the demo in FEI and FEE ICG modes. When using either FEI and FEE
ICG modes, the demo uses a faster SCI baud setting (9600 bps). The code excerpt below from Cpu.h shows
the ICG options built-in to the project.
//=======================================================
//Select a clock mode
//=======================================================
//FBE = FLL ByPassed External Clock
#define FBE_32KHZ 1 /* 32 kHz crystal and 16 kHz fbus */
//FEE = FLL Enabled using External Clock
#define FEE_32K8BUS 0 /* 32 kHz crystal and 8.39 MHz fbus */
#define FEE_32K16BUS 0 /* 32 kHz crystal and 16.775 MHz fbus */
//FEI = FLL Enabled Internal Clock
#define FEI_8MBUS 0 /* fbus 17.77/2 MHz; untrimmed */

Example Application Using the DEMO9S08LC60
Interfacing an LCD to the MC9S08LC60, Rev. 0
Freescale Semiconductor 19
4.2.2 SCI Configuration
The SCI configuration requires:
• The enabling of the SCI receiver and transmitter
• The configuration of the SCI baud registers
• Configuration of other SCI parameters
The code excerpt below provides a typical scheme for SCI configuration.
SCIC1 = 0;
/* SCI1C3: R8=0,T8=0,TXDIR=0,??=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
SCIC3 = 0;
SCIBD = SCIDIVIDER; //Set in sci.h file
SCIC2_TE = 1; /* Enable transmitter */
SCIC2_RE = 1; /* Enable receiver */
Depending on the ICG configuration, the SCIDIVIDER variable may need to be modified to obtain a
particular baud rate. The SCI is clocked by the bus clock. With a 32.768 kHz crystal and FBE mode, a
9600 baud rate cannot be achieved. (The value of SCIDIVIDER is approximately equal to the bus
clock / 16 / desired baud rate). In the demo application, SCIDIVIDER can be configured in sci.h. In the
case of a 32.768 kHz crystal in FBE mode, SCIDIVIDER is selected (in sci.h) such that the baud rate is
110 bps.
4.2.3 LCD Configuration
An LCD driver can be developed using a variety of approaches. LCD drivers provide the ability to
initialize the LCD module and write to the display. Because of this, LCD driver should provide the
following functionality:
• LCD initialization
— Initialization of the LCD clock
— Initialization of the LCD frame frequency and blink rate
— Initialization of the LCD power supply
— Setup of the waveform type
— Setup of the charge pump frequency
— Setup of the LCD buffer
— Setup of the LCD buffer driver capability
— Enabling of the frontplanes and the LCD
• LCD methods
— Write to the display (for alphanumerics and non-alphanumerics)
— Clear the display (for alphanumerics and non-alphanumerics)
— Configure, start, and end blinking
•LCDevents
— LCD interrupt enable
— LCD interrupt handler

Interfacing an LCD to the MC9S08LC60, Rev. 0
Example Application Using the DEMO9S08LC60
Freescale Semiconductor20
LCD drivers to write to the display are simple to implement after the relationship of the LCD segments to
the LCD RAM is determined. For this example application, the method to determine the LCD segment to
LCD RAM relationship was described in Section 3. Section 3 also discussed an approach to display
alphanumeric characters. This approach will be implemented in software.
4.2.3.1 LCD Initialization Drivers LCD_init()
In the example application, the initialization is accomplished via the LCD_init() function. The source code
for LCD_init() is provided below. LCD_init() calls functions that configure the power, clocks, and other
parameters for the LCD. Many of these parameters are compile time decisions. Each of the functions called
by LCD_init() can be found in lcddrv.c.
void LCD_init() {
//Configure clock source
CONFIG_CLKSOURCE();
//power supply configuration
SET_CONFIG_VSUPPLY();
//Configure operation in stop/wait
SET_LCDCR1_REG();
//Configure frame frequncy
SET_LCD_FRAME_FREQU();
//Configure blink rate
CONFIG_BLINKING( 2 /* Hz*/, OFF);
//Enable Frontplanes
ENABLE_FP();
//Enable LCD
ENABLE_LCD(ON);
//Map RAM to ARRAY
MAP_LCDDRIVER_TO_LCDGLASS();
}
The example application uses lcddrv.h to set up the LCD module power, clock, and other initialization
options using several define directives. Some of these directive-defined variables are also tied to variables
defined in cpu.h because LCD clock configuration parameters are dependent on the ICG configuration. An
excerpt of variables defined in lcddrv.h is provided below, and shows the options for LCD power
configuration and LCD duty cycle.
//===========================
//LCD power configuration
//===========================
#define LCDPWR_VDD 1
#define LCDPWR_VLCD 0
#define LCDPWR_VLLLN 0
.
.
.