NXP Semiconductors UJA1169A User manual

UM11758
UJA1169A evaluation boards
Rev. 1 — 19 April 2022 User manual
Rev Date Description
v.1 20220419 Initial version
Revision history
IMPORTANT NOTICE
For engineering development or evaluation purposes only
NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-
soldered to a printed-circuit board to make it easier to access inputs,
outputs and supply terminals. This evaluation board may be used with any
development system or other source of I/O signals by connecting it to the
host MCU computer board via off-the-shelf cables. This evaluation board
is not a Reference Design and is not intended to represent a final design
recommendation for any particular application. Final device in an application
heavily depends on proper printed-circuit board layout and heat sinking
design as well as attention to supply filtering, transient suppression, and I/O
signal quality.
The product provided may not be complete in terms of required design,
marketing, and or manufacturing related protective considerations, including
product safety measures typically found in the end device incorporating the
product. Due to the open construction of the product, it is the responsibility of
the user to take all appropriate precautions for electric discharge. In order to
minimize risks associated with the customers’ applications, adequate design
and operating safeguards must be provided by the customer to minimize
inherent or procedural hazards. For any safety concerns, contact NXP sales
and technical support services.

NXP Semiconductors UM11758
UJA1169A evaluation boards
1 Introduction
This document is the user guide for the UJA1169A evaluation boards. It is intended
for engineers involved in the evaluation, design, implementation and validation of the
UJA1169A product family. This guide discusses power supply requirements and the MCU
and CAN bus interfaces, and describes how to connect the boards into an ECU/CAN
network.
The UJA1169A evaluation boards are designed to facilitate the testing and evaluation of
UJA1169A product features in a variety of microcontroller IO interface environments. All
MCU interface signals can be accessed in two ways: at a header row on the top side and
also at header rows on the bottom side that can be plugged directly into many NXP MCU
evaluation boards. The UJA1169A evaluation boards are designed to be compatible
with the S32K1xx evaluation board series from NXP and to support the use of standard
software development tools and drivers.
The UJA1169A evaluation board family consists of three variant boards as detailed
in Table 1. The entire UJA1169A product family can be evaluated using these three
boards, and not just the onboard devices. For example, the UJA1169AF-EVB board
(with a UJA1169ATK/F device) can be used to evaluate the UJA1169ATK by setting
bit CPNC = 0 in the CAN control register. In the same way, the UJA1169ATK/X and
UJA1169ATK/3 devices can be evaluated using the the UJA1169AXF-EVB and
UJA1169AF3-EVB boards, respectively.
Modes Supplies
Host
interface Additional features Package
Evaluation board On-board device
Normal + Standby modes Sleep mode Reset mode V1: 5 V, μC only V1: 5 V, μC and CAN V1: 3.3 V, µC only V2: 5 V, CAN + onboard loads VEXT: 5 V, external loads SPI: for control and diagnosis RSTN: reset pin Watchdog Local WAKE pin Limp pin Non-volatile memory CAN partial networking CAN FD passive HVSON20
UJA1169AF-EVB UJA1169ATK/F ● ● ● ● ● ● ● ● ● ● ● ● ● ●
UJA1169AXF-EVB UJA11692ATK/X/F ● ● ● ● ● ● ● ● ● ● ● ● ● ●
UJA1169AF3-EVB UJA1169ATK/F/3 ● ● ● ● ● ● ● ● ● ● ● ● ● ●
Table 1. UJA1169A evaluation boards and device overview
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2 Overview of boards
Top and bottom views of the UJA1169AXF-EVB board are illustrated in Figure 1. Unless
otherwise stated, the information in this section applies to all UJA1169A evaluation
boards.
Board dimensions are 58.5 mm × 81.1 mm. Only components needed to support basic
UJA1169A functionality are included. All boards contain circuitry for reverse polarity-
protected battery supply, status LEDs for BAT, V1, V2/VEXT and LIMP signals, external
PNP transistor for thermal management, local wake-up and CAN bus termination. The
boards also provide several header rows (2.54 mm pitch) for connecting MCU interface
and application signals. The headers on the bottom are compatible with the Arduino
Uno pinout order, allowing the board to be connected directly to a variety of NXP MCU
evaluation boards.
Figure 1. UJA1169AXF-EVB top and bottom views
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2.1 Ground connections
All ground pins are connected to the ground plane.
Ground connections
J2-02
J3-07/12
J4-13
J5-11/13
J6-02/03
J9-02
Table 2. Ground connections
2.2 Power supply connections
2.2.1 Battery connections
An external power supply must be connected to either power jack J6 or 2-pin header J2,
as illustrated in Figure 2.
UJA1169A UJA1169Ax-EVB
BAT (pin 14) J2-01 or J6-01: connect to 12 V battery supply; pin BAT on the device is
connected via Schottky diode D1.
J5-01 and J5-15: pin VIN on the UJA1169Ax-EVB board is connected,
by default, to the battery supply via jumper J8; remove jumper J8 to
disconnect VIN on J5 from the battery supply.
Table 3. BAT/VIN connections
Both supply circuits are routed via polarity protection Schottky diode D1 in order to block
reverse currents. Decoupling capacitors C1 and C2 are provided to stabilize the input
voltage and remove noise on the battery connection.
Green LED D2 lights up once the 12 V power supply has been connected.
By default, the UJA1169Ax-EVB evaluation board battery supply is routed to the MCU
board via pin VIN on the Arduino connector, allowing the supply to the entire module to
be managed via the UJA1169Ax-EVB board. This feature can be disabled by removing
jumper J8, disconnecting the battery supply from pin VIN.
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UJA1169A evaluation boards
J2
J5
J8
aaa-045442
UJA1169A
BAT (p14)
GND
(p1,4,16,19)
12 V
GND
J6
C2
0.1 µF
C1
100 µF
R1
1 kΩ
D2
LED
D1
Schottky
diode
VIN
Figure 2. 12 V power supply connection options
2.2.2 V1/PNP connections
The V1 supply voltage is generated by the internal 5 V or 3.3 V regulator, depending
on the UJA1169A variant, and is intended to supply the external microcontroller. It also
determines the IO reference level.
The V1 output voltage can be accessed at pin 8 on connector J3. Decoupling capacitor
C8 is provided to stabilize the output voltage and remove noise. LED D5, connected
via resistor R9, indicates the status of V1 (on when V1 active). Jumper J7 can be used
to connect V1 to J5-03 if needed as an MCU IO reference voltage. PNP pins can be
accessed at connector J9 (see Figure 7).
UJA1169A UJA1169Ax-EVB
V1 (pin 5) J3-08 provides 3.3 V (UJA1169AF3-EVB only) or 5 V for MCU
supply
J5-03: pin V1 is connected to the IOREF signal on header J5 via
jumper J7, e.g. for the MCU IO supply
VEXCTRL (pin 15) TP4
VEXCC (pin 6) J9-01: connected to the collector of the onboard PNP transistor
PNP UJA1169Ax-EVB
B (pin 4) J9-03: connected to the base of the onboard PNP transistor
C (pin 5) J9-01: connected to the collector of the onboard PNP transistor
E (pin 1,2,3) J9-04: connected indirectly via R4, 0 Ω to emitter of the onboard
PNP transistor
Table 4. V1/PNP connections
The internal V1 voltage regulator on the UJA1169A can deliver up to 250 mA without
the need for an external PNP transistor. However, if critical thermal requirements need
to be satisfied, it is possible to connect one or more external PNP transistors to share
the total V1 load current, and therefore also share the thermal dissipation. The PNP
transistor switches on when the load current exceeds the selected PNP activation
threshold, Ith(act)PNP, while the battery supply voltage is above the PNP activation
threshold, Vth(act)PNP. The main regulation loop inside the UJA1169A continues to handle
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all dynamic load changes within the package while the external PNP delivers additional
supply current to the application.
Detailed information on the functionality and operation of the UJA1169A can be found in
the data sheet and application hints (see Section 7).
2.2.2.1 UJA1169A with one PNP
By default, all UJA1169Ax-EVB boards are delivered with an onboard PNP (e.g.
PHPT61003PY from Nexperia). A simplified circuit diagram is shown in Figure 3.
Shunt resistor R13 is used to limit the current delivered by the external PNP transistor
and to protect the PNP transistor against a V1 short-circuit to GND.
Pull-up resistor R15 is used to pull up the PNP base voltage to prevent it floating (e.g. if
R10 has been removed) and therefore ensure that the PNP is turned OFF.
Filter capacitor C9 is needed to protect V1 against an overvoltage during RF-injection on
the battery line. For EMI optimization, C9 is placed close to the PNP emitter.
R4 and R10 are provided to allow the PNP to be easily disconnected.
aaa-045443
D5
LED
R9
1 k
GND
V1
J3
UJA1169A
J9
J5
V1 (p5)
VEXCC (p6)
VEXCTRL (p15)
GND
(p1, 4, 16, 19)
VDD
PNP_C
PNP_B
GND
BAT
BAT
GND
R13
1.6 Ω J7
R15
100 k
R10
0 Ω
PNP
R4
0 Ω
C8
6.8 F
C9
10 nF
Figure 3. Simplified schematic of UJA1169Ax-EVB with one PNP.
Figure 4. UJA1169Ax-EVB PCB configured to operate with one PNP.
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2.2.2.2 UJA1169A without an external PNP
As already discussed, the UJA1169Ax-EVB can operate using only the V1 regulator in
applications where thermal considerations are not critical. For this option, resistors R4
and R10 must be removed, as illustrated in Figure 5 and Figure 6.
aaa-045490
D5
LED
R9
1 k
GND
V1
J3
UJA1169A
J9
J5
V1 (p5)
VEXCC (p6)
VEXCTRL (p15)
GND
(p1, 4, 16, 19)
VDD
PNP_C
PNP_B
GND
BAT
BAT
GND
R13
1.6 Ω J7
R15
100 k
R10
0 Ω
PNP
R4
0 Ω
C8
6.8 F
C9
10 nF
Figure 5. UJA1169Ax-EVB PCB configured to operate without a PNP.
Figure 6. UJA1169Ax-EVB PCB configured to operate without a PNP.
2.2.2.3 UJA1169Ax-EVB with multiple external PNPs
If thermal dissipation is so high that it needs to be distributed over a number of
components, multiple PNPs can be connected in parallel. A single onboard PNP is
included. Additional PNPs can be connected via header J9, as illustrated in Figure 7.
An emitter resistor is needed for each PNP to balance the current between the devices
(e.g. 10 Ω). Make sure the resistor selected can handle the expected power dissipation.
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aaa-045491
D5
LED
R9
1 k
GND
V1
J3
UJA1169A
J9
J5
V1 (p5)
VEXCC (p6)
VEXCTRL (p15)
GND
(p1, 4, 16, 19)
VDD
PNP_C
PNP_B
GND
BAT
BAT
additional PNP(s)
GND
R13
1.6 Ω J7
R15
100 k
R10
0 Ω
PNP
C8
6.8 F
C9
10 nF
R15
100 k
PNP
R4
10 Ω
R4
10 Ω
C9
10 nF
R15
100 k
PNP
R4
10 Ω
C9
10 nF
Figure 7. Simplified schematic of UJA1169Ax-EVB with multiple PNPs.
Figure 8. UJA1169Ax-EVB PCB configured to operate with multiple PNPs.
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2.2.3 V2/VEXT connection
UJA1169A devices contain a second on-chip 5 V regulator. On the UJA1169ATK,
UJA1169ATK/F, UJA1169ATK/3 and UJA1169ATK/F/3 variants, this regulator (V2)
supplies the internal CAN transceiver and/or additional onboard hardware. On the
UJA1169ATK/X and UJA1169ATK/X/F variants, the second regulator (VEXT) is intended
to supply off-board components such as sensors.
Both V2 and VEXT can deliver up to 100 mA. A decoupling capacitor (C10) is connected
between the pin and ground on the board. LED D6 lights up when the V2/VEXT output is
active.
The V2 (UJA1169AF-EVB and UJA1169AF3-EVB) or VEXT (UJA1169AXF-EVB) output
voltage is accessible on connector J3 (pin 10).
UJA1169A UJA1169Ax-EVB
V2/VEXT (pin 13) J3-10: provides 5 V supply for internal ECU/external loads
Table 5. VEXT connection
aaa-045535
UJA1169A
V2/VEXT(p13)
GND(p1,4,16,19)
V2/VEXT
GND
J3
R8
1 kΩ
D6
LED
C10
6.8 µF
Figure 9. V2/VEXT supply connections
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2.3 CAN communication circuitry
The UJA1169Ax-EVB evaluation boards contain typical CAN communication circuitry.
The CANH and CANL bus signals are output on connector J1.
UJA1169A UJA1169Ax-EVB
CANH (pin 18) J1-01: connect to HIGH-level CAN bus line
CANL (pin 17) J1-02: connect to LOW-level CAN bus line
Table 6. CAN bus line connections
Equipped with termination resistors R2 and R3, the UJA1169Ax-EVB evaluation boards
are configured to be used as termination nodes in a CAN network. If the CAN network
is already terminated at both ends, it is recommended to remove R2 and R3 or replace
them with higher value resistors to ensure that the impedance on the bus meets the CAN
bus load specification, typically 60 Ω.
aaa-045540
UJA1169A
CANH(p18)
CANL(p17)
L1
100 µH
R3
62 Ω
C4
4.7 nF
D3
PESD1CAN
CANH
CANL
J1
split
termination
common-mode
choke ESD protection diodes
R2
62 Ω
Figure 10. CAN bus interface circuitry (relevant for the entire UJA1169A-EVB family)
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2.4 Wake-up options
All UJA1169A variants support a Sleep mode for use in energy-sensitive applications.
Once in Sleep mode, the device will remain in this low-power mode until a wake-up
request is received. A wake-up event can be triggered remotely via a standard pattern or
dedicated wake-up frame on the CAN bus, or locally via the WAKE pin (details of wake-
up functionality can be found in the data sheet and application hints; see Section 7).
UJA1169A UJA1169Ax-EVB
WAKE (pin 12) J3-11: connect to wake-up signal
Table 7. WAKE connections
All three UJA1169A evaluation boards feature local wake-up test circuitry. The WAKE pin
is pulled HIGH by default via 10 kΩ resistors R6 and R7. When switch SW1 is pressed,
the WAKE pin is pulled LOW. To test local wake-up functionality, local wake-up must first
be enabled via the UJA1169A register map (as described in the UJA1169A data sheet
[1]).
Regulator V1 on the UJA1169A is intended to supply the MCU. V1 is off in Sleep mode
and switches on automatically when a wake-up event is detected.
The WAKE pin can be accessed via header J3 on the top of the board.
aaa-045551
UJA1169A
WAKE(p12)
GND
(p1,4,16,19)
WAKE
GND
J3
R7, 10 kΩ R6, 10 kΩ
C7
10 nF
SW1
BAT
Figure 11. Local wake-up circuitry
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2.5 LIMP output
The LIMP pin can be accessed on top-side connector J3. It is targeted at applications
that need a ‘limp home’ feature in the event of serious ECU failure. LIMP is an open-drain
low-side output. It can be biased to an application-specific voltage level, such as via a
pull-up resistor to BAT in the evaluation setup.
Red LED D4, connected in series with resistor R5, turns on when LIMP is triggered.
UJA1169A UJA1169Ax-EVB
LIMP (pin 11) J3-14: connect to limp home signal
Table 8. VEXT connection
aaa-045552
UJA1169A
J3
LIMP(p11) LIMP
R5
1 kΩ
D4
LED
BAT
Figure 12. LIMP circuitry
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2.6 MCU interface
The digital interface pins are located on the top side connector J3, as well as on the
bottom side connector J4. Two of these pins, TXD and RXD, are used for CAN data
communication with the MCU. The remaining four pins are used for SPI communication
with the MCU.
A bidirectional reset signal (connected to the RSTN pin on the UJA1169A) is also
accessible on J3 and J5.
UJA1169A UJA1169Ax-EVB
TXD (pin 2) J3-01 or J4-18
RXD (pin 7) J3-02 or J4-20
SDO (pin 9) J3-03 or J4-09
SDI (pin 3) J3-04 or J4-07
SCK (pin 10) J3-05 or J4-11
SCSN (pin 20) J3-06 or J4-05
Table 9. TXD, RXD and SPI connections
J4
aaa-045565
UJA1169A
SCSN(p20) SCSN
J3
SCK(p10) SCK
SDI(p3) SDI
SDO(p9) SDO
RXD(p7) RXD
TXD(p2) TXD
Figure 13. MCU interface
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2.7 Reset connection
The reset connection is a bidirectional signal between the RSTN pin on the SBC and the
MCU. It is used to initiate a system reset.
A 10 kΩ pull-up resistor is connected between RSTN and V1 on the evaluation boards.
A reset event is triggered by a LOW level on RSTN. Details of reset functionality can be
found in the UJA1169A data sheet [1] and application hints [2].
UJA1169A UJA1169Ax-EVB
RSTN (pin 8) J3-09 or J5-05: connect MCU reset signal
Table 10. RSTN connection
aaa-045566
UJA1169A
J5
RSTN(p8) RSTN
R14
10 kΩ
V1(p5)
J3
Figure 14. Reset connection
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3 Connecting the UJA1169Ax-EVB into a CAN network
The following conditions must be met before powering up the system with a 12 V supply.
•Connect all boards in the ECU to a common GND
•Connect SPI pins to the MCU SPI master:
–SDO (J3-03, J4-09) → MISO
–SDI (J3-04, J4-07) → MOSI
–SCK (J3-05, J4-11) → SCK
–SCSN (J3-06, J4-05) → CS
•Connect TXD/RXD (J3-01/J3-02, J4-18/J4-20) pins to the MCU CAN controller TXD/
RXD pins
•Connect RSTN (J3-09/J5-05) to the MCU CAN controller reset pin
•Connect CANH and CANL (J1-01/J1-02) to the CAN bus twisted-pair cables
•Connect V1(J3-08, J5-03) to the MCU supply unit
•For the UJA1169AXF-EVB, connect VEXT (J3-10) to the peripheral loads that need a
5 V supply (optional)
Once the above steps have been completed, the ECU/EVB can be powered up using an
external battery supply. The UJA1169A starts up in Forced Normal mode (if MTP is not
configured) or Standby mode (if MTP configured), awaiting commands from the MCU via
the SPI interface.
An example showing how to connect the UJA1169AXF-EVB between an MCU and the
CAN bus is shown in Figure 15.
aaa-045590
ECU A
TXD/RXD
V1
CANH
GND 12 V
CANL
LIMP
GND
ECU X
ECU B
ECU N
WAKE
RST
VEXCTRL/VEXCC
VEXT
SPI
PNP
MCU
UJA1169AXF-EVB
Figure 15. Connecting the UJA1169AXF-EVB into an ECU/CAN bus network
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4 Schematic diagrams
R1
1 k
R7
10 k
R6
10 k
D4
D2
LED_GRN
SILK=BAT
HDR_1X2
CON PWR 3
12 V
BAT
V1
B
AT
_
L
E
D
A
C
LED RED
SILK=BAT
A C
A C
SILK=GND
SILK=12 V
SILK=PNP_C
SILK=GND
SILK=PNP_B
SILK=BAT
2
1
1
2
3
PNP_C
GND
PNP_B
4
J2
RHDR_1X4(1)
J9
3
1
2
S
H
1
S
H2
J6
2119
6
U1
17
12
11
18
UJA1169ATK/F
EP
D1
PMEG3020EH
C1
100 µF
C2
0.1 µF
C7
0.01 µF SW1
SW SPST TH
SILK = WAKE
PB_WAKE
R8
1 k D6
LED_GRN
SILK=V2
V2_LED CA
C10
6.8 µF
R9
1 k D5
LED_GRN
SILK=V1
V1_LED CA
C8
6.8 µF
aaa-045591
12
HDR_1X14
USER INTERFACE ARDUINO INTERFACE
HDR_2X10
SILK=GND
SILK=BAT
SILK=LIMP
11
14
13
10
9
WAKE
LIMP
V2
RSTN
SCSN
SCSN
SDI
SDO
TXD
RXD
SCK
V1
SCK
SDI
SDO
RX D
TXD
SILK=RSTN
8
SILK=V1
SILK=WAKE
SILK=V2
BAT
7
SILK=GND
6
SILK=SCSN
5
SILK=TXD
SILK=RXD
SILK=SCSN
SILK=SDO
SILK=SDI
SILK=SCK
SILK=GND
4
3
SILK=SDO
2
SILK=RXD
SILK=SCK
SILK=SDI
1
J3
SILK=TXD
HDR_1X2
JUMPER (DEFAULT) = ON
2 1
J8
2 1
J7
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
2
4
6
8
10
12
14
16
J4
HDR_2X8
1
3
5
7
9
RSTN
IOREF SILK=IOREF
SILK=GND
SILK=RST
SILK=VIN
SILK=12 V
SILK=V1
SILK=VIN
11
13
15
J5
12 V
V1
HDR 1X2
JUMPER (DEFAULT) = ON
VIN
BAT
TP1 TP2
TP4
3
2
1 5
4
PNP_E
GND4 V
E
X
CC
15
V
E
X
C
T
R
L
VEXCTRL
16
GND3
4
GND2
1
GND1
RST
RSTN
V2 V2
8
R14
10 k
R13
1.6
R10
C9
0.01 µF
R15
PHPT61003PY
Q1
LAYOUT NOTE: PLACE C9 CLOSE TO Q1
LAYOUT NOTE: PLACE R10, R13 CLOSE TO J9
100 k
R4
V1
5
SCK
10
SDI
SCK
SDI
3
SDO SDO
9
SCS SCSN
20
TXD
2
13
RXD
TXD
RXD
R5
10 k
WAKE
LIMP
LIMP_LED
14
BAT
7
HDR_1X2
SILK=CAN
PORT_CANL
PORT_CANH
SILK=L
SILK=H 1
2
J1
CANL
CANH
R2
62
R3
62
L1
100 µH
C5(1)
51 pF
C6(1)
51 pF C4
4700 pF
1
3
D3
PESD1CAN
2
34
CAN_T
1
24
13
2CANL
CANH
(1) Component not populated.
Figure 16. UJA1169AF-EVB schematic diagram
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NXP Semiconductors UM11758
UJA1169A evaluation boards
R1
1 k
R7
10 k
R6
10 k
D4
D2
LED_GRN
SILK=BAT
HDR_1X2
CON PWR 3
12 V
BAT
V1
B
AT
_
L
E
D
A
C
LED RED
SILK=BAT
A C
A C
SILK=GND
SILK=12 V 2
1
1
2
3
PNP_C
GND
PNP_B
4
J2
3
1
2
S
H
1
S
H2
J6
2119
6
U1
17
12
11
18
UJA1169ATK/F/3
EP
D1
PMEG3020EH
C1
100 µF
C2
0.1 µF
C7
0.01 µF SW1
SW SPST TH
SILK = WAKE
PB_WAKE
R8
1 k D6
LED_GRN
SILK=V2
V2_LED CA
C10
6.8 µF
R9
1 k D5
LED_GRN
SILK=V1
V1_LED CA
C8
6.8 µF
aaa- 045593
12
HDR_1X14
USER INTERFACE ARDUINO INTERFACE
HDR_2X10
SILK=GND
SILK=BAT
SILK=LIMP
11
14
13
10
9
WAKE
LIMP
V2
RSTN
SCSN
SCSN
SDI
SDO
TXD
RXD
SCK
V1
SCK
SDI
SDO
RX D
TXD
SILK=RSTN
8
SILK=V1
SILK=WAKE
SILK=V2
BAT
7
SILK=GND
6
SILK=SCSN
5
SILK=TXD
SILK=RXD
SILK=SCSN
SILK=SDO
SILK=SDI
SILK=SCK
SILK=GND
4
3
SILK=SDO
2
SILK=RXD
SILK=SCK
SILK=SDI
1
J3
SILK=TXD
HDR_1X2
JUMPER (DEFAULT) = ON
2 1
J8
2 1
J7
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
2
4
6
8
10
12
14
16
J4
HDR_2X8
1
3
5
7
9
RSTN
IOREF SILK=IOREF
SILK=GND
SILK=RST
SILK=VIN
SILK=12 V
SILK=V1
SILK=VIN
11
13
15
J5
12 V
V1
HDR 1X2
JUMPER (DEFAULT) = ON
VIN
BAT
TP1 TP2
TP4
3
2
1 5
4
PNP_E
GND4 V
E
X
CC
15
V
E
X
C
T
R
L
VEXCTRL
16
GND3
4
GND2
1
GND1
RST
RSTN
V2 V2
8
R14
10 k
R13
1.6
R10
C9
0.01 µF
R15
PHPT61003PY
Q1
LAYOUT NOTE: PLACE C9 CLOSE TO Q1
LAYOUT NOTE: PLACE R10, R13 CLOSE TO J9
100 k
R4
V1
5
SCK
10
SDI
SCK
SDI
3
SDO SDO
9
SCS SCSN
20
TXD
2
13
RXD
TXD
RXD
R5
10 k
WAKE
LIMP
LIMP_LED
14
BAT
7
HDR_1X2
SILK=CAN
PORT_CANL
PORT_CANH
SILK=L
SILK=H 1
2
J1
CANL
CANH
R2
62
R3
62
L1
100 µH
C4
4700 pF
1
3
D3
PESD1CAN
2
34
CAN_T
1
24
13
2CANL
CANH
C5(1)
51 pF
C6(1)
51 pF
SILK=PNP_C
SILK=GND
SILK=PNP_B
SILK=BAT
RHDR_1X4(1)
J9
(1) Component not populated.
Figure 17. UJA1169AF3-EVB schematic diagram
UM11758 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved.
User manual Rev. 1 — 19 April 2022
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NXP Semiconductors UM11758
UJA1169A evaluation boards
R1
1 k
R7
10 k
R6
10 k
D4
D2
LED_GRN
SILK=BAT
HDR_1X2
CON PWR 3
12 V
BAT
V1
B
AT
_
L
E
D
A
C
LED RED
SILK=BAT
A C
A C
SILK=GND
SILK=12 V 2
1
1
2
3
PNP_C
GND
PNP_B
4
J2
3
1
2
S
H
1
S
H2
J6
2119
6
U1
17
12
11
18
UJA1169ATK/X/F
EP
D1
PMEG3020EH
C1
100 µF
C2
0.1 µF
C7
0.01 µF SW1
SW SPST TH
SILK = WAKE
PB_WAKE
R8
1 k D6
LED_GRN
SILK=VEXT
VEXT_LED CA
C10
6.8 µF
R9
1 k D5
LED_GRN
SILK=V1
V1_LED CA
C8
6.8 µF
aaa- 045594
12
HDR_1X14
USER INTERFACE ARDUINO INTERFACE
HDR_2X10
SILK=GND
SILK=BAT
SILK=LIMP
11
14
13
10
9
WAKE
LIMP
VEXT
RSTN
SCSN
SCSN
SDI
SDO
TXD
RXD
SCK
V1
SCK
SDI
SDO
RX D
TXD
SILK=RSTN
8
SILK=V1
SILK=WAKE
SILK=VEXT
BAT
7
SILK=GND
6
SILK=SCSN
5
SILK=TXD
SILK=RXD
SILK=SCSN
SILK=SDO
SILK=SDI
SILK=SCK
SILK=GND
4
3
SILK=SDO
2
SILK=RXD
SILK=SCK
SILK=SDI
1
J3
SILK=TXD
HDR_1X2
JUMPER (DEFAULT) = ON
2 1
J8
2 1
J7
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
2
4
6
8
10
12
14
16
J4
HDR_2X8
1
3
5
7
9
RSTN
IOREF SILK=IOREF
SILK=GND
SILK=RST
SILK=VIN
SILK=12 V
SILK=V1
SILK=VIN
11
13
15
J5
12 V
V1
HDR 1X2
JUMPER (DEFAULT) = ON
VIN
BAT
TP1 TP2
TP4
3
2
1 5
4
PNP_E
GND4 V
E
X
CC
15
V
E
X
C
T
R
L
VEXCTRL
16
GND3
4
GND2
1
GND1
RST
RSTN
VEXT VEXT
8
R14
10 k
R13
1.6
R10
C9
0.01 µF
R15
PHPT61003PY
Q1
LAYOUT NOTE: PLACE C9 CLOSE TO Q1
LAYOUT NOTE: PLACE R10, R13 CLOSE TO J9
100 k
R4
V1
5
SCK
10
SDI
SCK
SDI
3
SDO SDO
9
SCS SCSN
20
TXD
2
13
RXD
TXD
RXD
R5
10 k
WAKE
LIMP
LIMP_LED
14
BAT
7
HDR_1X2
SILK=CAN
PORT_CANL
PORT_CANH
SILK=L
SILK=H 1
2
J1
CANL
CANH
R2
62
R3
62
L1
100 µH
C4
4700 pF
1
3
D3
PESD1CAN
2
34
CAN_T
1
24
13
2CANL
CANH
SILK=PNP_C
SILK=GND
SILK=PNP_B
SILK=BAT
RHDR_1X4(1)
J9
C5(1)
51 pF
C6(1)
51 pF
(1) Component not populated.
Figure 18. UJA1169AXF-EVB schematic diagram
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User manual Rev. 1 — 19 April 2022
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NXP Semiconductors UM11758
UJA1169A evaluation boards
5 Bills of Materials
NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP offers component recommendations in this configuration, it is the responsibility
of the customer to validate their application.
For critical components, it is vital to use the manufacturer listed.
Item
number
Quantity Schematic
label
Value Description Part number Manufacturer name
Active components
1 1 U1 UJA1169ATK/F IC SBC XCVR CAN 5 V AEC-Q100 HVSON20 UJA1169ATK/X NXP SEMICONDUCTORS
Capacitors
2 1 C1 100 µF CAP ALEL 100 µF 25 V 20 % -- SMT UWX1E101MCL1GB NICHICON
3 1 C2 0.1 µF CAP CER 0.1 µF 25 V 10 % X7R AEC-Q200 0603 CGA3E2X7R1E104K080AA TDK
4 1 C4 4700 pF CAP CER 4700 pF 50 V 5 % C0G AEC-Q200 0603 CGA3E2C0G1H472J080AA TDK
5 2 C5, C6 51 pF not populated
6 1 C7, C9 0.01 µF CAP CER 0.01 µF 50 V 10 % X7R AEC-Q200 0603 CGA3E2X7R1H103K080AA TDK
7 1 C8, C10 6.8 µF CAP CER 6.8 µF 16 V 10 % X7S AEC-Q200 0805 CGA4J1X7S1C685K125AC TDK
Diodes
8 1 D1 SCH/30 V DIODE SCH PWR RECT 2A 30 V AEC-Q101 SOD123F PMEG3020EH,115 NEXPERIA
9 1 D2, D5, D6 LED/GRN LED BRIGHT GRN SGL 30 mA 0603 150060VS75000 WURTH ELEKTRONIK EISOS GMBH & CO. KG
10 1 D3 ESD Prot./24 V DIODE BIDIR CAN BUS ESD PROTECTION 200 W 24 V AEC-Q
101 SOT23
PESD1CAN,215 NEXPERIA
11 1 D4 LED/RED LED BRIGHT RED CLEAR SGL 2 V 20 mA SMT 0603 150060RS75000 WURTH ELEKTRONIK EISOS GMBH & CO. KG
Inductors
12 1 L1 100 µH IND CHK 100 µH 150 mA -30/+50 % AEC-Q200 1812 B82789C0104N002 EPCOS
Resistors
CRCW06031K00JNEA VISHAY INTERTECHNOLOGY (preferred)
ERJ-3GEYJ103V PANASONIC (alternative)
13 2 R1, R8, R9 1 kΩ RES MF 1 kΩ 1/10 W 5 % AEC-Q200 0603
RK73B1JTTD102J KOA SPEER (alternative)
14 2 R2, R3 62 Ω RES MF 62 Ω 1/4W 5 % AEC-Q200 1206 CRCW120662R0JNEA VISHAY INTERTECHNOLOGY
ERJ-8GEY0R00V PANASONIC (preferred)
CR1206J/000ELF BOURNS (alternative)
CR12064W000T VENKEL COMPANY (alternative)
15 1 R4 0 Ω RES MF ZERO Ω 1/4 W 1206
WR12X000 PTL WALSIN TECHNOLOGY CORP (alternative)
ERJ-3GEYJ103V PANASONIC (preferred)16 3 R5, R6, R7, R14 10 kΩ RES MF 10 kΩ 1/10 W 5 % AEC-Q200 0603
RK73B1JTTD103J KOA SPEER (alternative)
ERJ-3GEY0R00V PANASONIC (preferred)17 1 R10 0 Ω RES MF ZERO Ω 1/10 W AEC-Q200 0603
CRCW06030000Z0EA VISHAY INTERTECHNOLOGY (alternative)
18 1 R13 1.6 Ω RES MF 1.6 Ω 3/4 W 1 % AEC-Q200 1206 CRCW12061R60FKEAHP VISHAY INTERTECHNOLOGY
CR0603-JW-104ELF BOURNS (preferred)
RK73B1JTTD104J KOA SPEER (alternative)
0603104J LIKET CORPORATION (alternative)
ERJ3GEYJ104V PANASONIC (alternative)
RC-0603-104JT SKYMOS
CR0603-10W-104JSNT VENKEL COMPANY (alternative)
CR0603-10W-104JT VENKEL COMPANY (alternative)
CRCW0603100KJNEC VISHAY INTERTECHNOLOGY (alternative)
19 1 R15 100 kΩ RES MF 100K 1/10 W 5 % 0603
WR06X104JTL WALSIN TECHNOLOGY CORP (alternative)
Switches, Connectors, Jumpers, and Test Points
20 1 J1 HDR_1X2 HDR 1X2 TH 200 MIL SP 338H SN 100L TSW-202-07-T-S SAMTEC
21 2 J2, J7, J8 HDR_1X2 HDR 1X2 TH 100 MIL SP 338H SN 100L TSW-102-07-T-S SAMTEC
22 1 J3 HDR_1x14 HDR 1X14 TH 100 MIL SP 350H AU 118L 61301411121 WURTH ELEKTRONIK EISOS GMBH & CO. KG
23 1 J4 HDR_2X10 HDR 2X10 TH 100 MIL CTR 428H AU 110L TSW-110-14-G-D SAMTEC
24 1 J5 HDR_2X8 HDR 2X8 TH 100 MIL CTR 433H AU 110L TSW-108-14-G-D SAMTEC
25 1 J6 CON 3 CON 3 PWR JACK RA TH 295H -- NI 98L PJ-051A CUI INC
26 1 J9 HDR_1X4 not populated
27 1 SW1 SPST_SWITCH SW SPST PB TACT 50MA 12 V TH 430186070716 WURTH ELEKTRONIK EISOS GMBH & CO. KG
5001 KEYSTONE ELECTRONICS (preferred)
TP-105-01-00 COMPONENTS CORPORATION (alternative)
28 2 TP1, TP2 TEST_040 TEST POINT BLACK 40 MIL DRILL 180 MIL TH 109L
151-203-RC KOBICONN (alternative)
29 13 TP4 TPAD_059 TEST POINT PAD 59 MIL DIA SMT, NO PART TO ORDER - -
Table 11. Bill of Materials - UJA1169AF-EVB
UM11758 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved.
User manual Rev. 1 — 19 April 2022
19 / 39

NXP Semiconductors UM11758
UJA1169A evaluation boards
NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP offers component recommendations in this configuration, it is the responsibility
of the customer to validate their application.
For critical components, it is vital to use the manufacturer listed.
Item
number
Quantity Schematic
label
Value Description Part number Manufacturer name
Active components
1 1 U1 UJA1169ATK/F/3 IC SBC XCVR CAN 3.3 V AEC-Q100 HVSON20 UJA1169ATK/X NXP SEMICONDUCTORS
Capacitors
2 1 C1 100 µF CAP ALEL 100 µF 25 V 20 % -- SMT UWX1E101MCL1GB NICHICON
3 1 C2 0.1 µF CAP CER 0.1 µF 25 V 10 % X7R AEC-Q200 0603 CGA3E2X7R1E104K080AA TDK
4 1 C4 4700 pF CAP CER 4700 pF 50 V 5 % C0G AEC-Q200 0603 CGA3E2C0G1H472J080AA TDK
5 2 C5, C6 51 pF not populated
6 1 C7, C9 0.01 µF CAP CER 0.01 µF 50 V 10 % X7R AEC-Q200 0603 CGA3E2X7R1H103K080AA TDK
7 1 C8, C10 6.8 µF CAP CER 6.8 µF 16 V 10 % X7S AEC-Q200 0805 CGA4J1X7S1C685K125AC TDK
Diodes
8 1 D1 SCH/30 V DIODE SCH PWR RECT 2A 30 V AEC-Q101 SOD123F PMEG3020EH,115 NEXPERIA
9 1 D2, D5, D6 LED/GRN LED BRIGHT GRN SGL 30 mA 0603 150060VS75000 WURTH ELEKTRONIK EISOS GMBH & CO. KG
10 1 D3 ESD Prot./24 V DIODE BIDIR CAN BUS ESD PROTECTION 200 W 24 V AEC-Q
101 SOT23
PESD1CAN,215 NEXPERIA
11 1 D4 LED/RED LED BRIGHT RED CLEAR SGL 2 V 20 mA SMT 0603 150060RS75000 WURTH ELEKTRONIK EISOS GMBH & CO. KG
Inductors
12 1 L1 100 µH IND CHK 100 µH 150 mA -30/+50 % AEC-Q200 1812 B82789C0104N002 EPCOS
Resistors
CRCW06031K00JNEA VISHAY INTERTECHNOLOGY (preferred)
ERJ-3GEYJ103V PANASONIC (alternative)
13 2 R1, R8, R9 1 kΩ RES MF 1 kΩ 1/10 W 5 % AEC-Q200 0603
RK73B1JTTD102J KOA SPEER (alternative)
14 2 R2, R3 62 Ω RES MF 62 Ω 1/4W 5 % AEC-Q200 1206 CRCW120662R0JNEA VISHAY INTERTECHNOLOGY
ERJ-8GEY0R00V PANASONIC (preferred)
CR1206J/000ELF BOURNS (alternative)
CR12064W000T VENKEL COMPANY (alternative)
15 1 R4 0 Ω RES MF ZERO Ω 1/4 W 1206
WR12X000 PTL WALSIN TECHNOLOGY CORP (alternative)
ERJ-3GEYJ103V PANASONIC (preferred)16 3 R5, R6, R7, R14 10 kΩ RES MF 10 kΩ 1/10 W 5 % AEC-Q200 0603
RK73B1JTTD103J KOA SPEER (alternative)
ERJ-3GEY0R00V PANASONIC (preferred)17 1 R10 0 Ω RES MF ZERO Ω 1/10 W AEC-Q200 0603
CRCW06030000Z0EA VISHAY INTERTECHNOLOGY (alternative)
18 1 R13 1.6 Ω RES MF 1.6 Ω 3/4 W 1 % AEC-Q200 1206 CRCW12061R60FKEAHP VISHAY INTERTECHNOLOGY
CR0603-JW-104ELF BOURNS (preferred)
RK73B1JTTD104J KOA SPEER (alternative)
0603104J LIKET CORPORATION (alternative)
ERJ3GEYJ104V PANASONIC (alternative)
RC-0603-104JT SKYMOS
CR0603-10W-104JSNT VENKEL COMPANY (alternative)
CR0603-10W-104JT VENKEL COMPANY (alternative)
CRCW0603100KJNEC VISHAY INTERTECHNOLOGY (alternative)
19 1 R15 100 kΩ RES MF 100K 1/10 W 5 % 0603
WR06X104JTL WALSIN TECHNOLOGY CORP (alternative)
Switches, Connectors, Jumpers, and Test Points
20 1 J1 HDR_1X2 HDR 1X2 TH 200 MIL SP 338H SN 100L TSW-202-07-T-S SAMTEC
21 2 J2, J7, J8 HDR_1X2 HDR 1X2 TH 100 MIL SP 338H SN 100L TSW-102-07-T-S SAMTEC
22 1 J3 HDR_1x14 HDR 1X14 TH 100 MIL SP 350H AU 118L 61301411121 WURTH ELEKTRONIK EISOS GMBH & CO. KG
23 1 J4 HDR_2X10 HDR 2X10 TH 100 MIL CTR 428H AU 110L TSW-110-14-G-D SAMTEC
24 1 J5 HDR_2X8 HDR 2X8 TH 100 MIL CTR 433H AU 110L TSW-108-14-G-D SAMTEC
25 1 J6 CON 3 CON 3 PWR JACK RA TH 295H -- NI 98L PJ-051A CUI INC
26 1 J9 HDR_1X4 not populated
27 1 SW1 SPST_SWITCH SW SPST PB TACT 50MA 12 V TH 430186070716 WURTH ELEKTRONIK EISOS GMBH & CO. KG
5001 KEYSTONE ELECTRONICS (preferred)
TP-105-01-00 COMPONENTS CORPORATION (alternative)
28 2 TP1, TP2 TEST_040 TEST POINT BLACK 40 MIL DRILL 180 MIL TH 109L
151-203-RC KOBICONN (alternative)
29 13 TP4 TPAD_059 TEST POINT PAD 59 MIL DIA SMT, NO PART TO ORDER - -
Table 12. Bill of Materials - UJA1169AF3-EVB
UM11758 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved.
User manual Rev. 1 — 19 April 2022
20 / 39