NXP Semiconductors UJA1169A User manual

UM11758
UJA1169A evaluation boards
Rev. 1 — 19 April 2022 User manual
Rev Date Description
v.1 20220419 Initial version
Revision history
IMPORTANT NOTICE
For engineering development or evaluation purposes only
NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-
soldered to a printed-circuit board to make it easier to access inputs,
outputs and supply terminals. This evaluation board may be used with any
development system or other source of I/O signals by connecting it to the
host MCU computer board via off-the-shelf cables. This evaluation board
is not a Reference Design and is not intended to represent a final design
recommendation for any particular application. Final device in an application
heavily depends on proper printed-circuit board layout and heat sinking
design as well as attention to supply filtering, transient suppression, and I/O
signal quality.
The product provided may not be complete in terms of required design,
marketing, and or manufacturing related protective considerations, including
product safety measures typically found in the end device incorporating the
product. Due to the open construction of the product, it is the responsibility of
the user to take all appropriate precautions for electric discharge. In order to
minimize risks associated with the customers’ applications, adequate design
and operating safeguards must be provided by the customer to minimize
inherent or procedural hazards. For any safety concerns, contact NXP sales
and technical support services.

NXP Semiconductors UM11758
UJA1169A evaluation boards
1 Introduction
This document is the user guide for the UJA1169A evaluation boards. It is intended
for engineers involved in the evaluation, design, implementation and validation of the
UJA1169A product family. This guide discusses power supply requirements and the MCU
and CAN bus interfaces, and describes how to connect the boards into an ECU/CAN
network.
The UJA1169A evaluation boards are designed to facilitate the testing and evaluation of
UJA1169A product features in a variety of microcontroller IO interface environments. All
MCU interface signals can be accessed in two ways: at a header row on the top side and
also at header rows on the bottom side that can be plugged directly into many NXP MCU
evaluation boards. The UJA1169A evaluation boards are designed to be compatible
with the S32K1xx evaluation board series from NXP and to support the use of standard
software development tools and drivers.
The UJA1169A evaluation board family consists of three variant boards as detailed
in Table 1. The entire UJA1169A product family can be evaluated using these three
boards, and not just the onboard devices. For example, the UJA1169AF-EVB board
(with a UJA1169ATK/F device) can be used to evaluate the UJA1169ATK by setting
bit CPNC = 0 in the CAN control register. In the same way, the UJA1169ATK/X and
UJA1169ATK/3 devices can be evaluated using the the UJA1169AXF-EVB and
UJA1169AF3-EVB boards, respectively.
Modes Supplies
Host
interface Additional features Package
Evaluation board On-board device
Normal + Standby modes Sleep mode Reset mode V1: 5 V, μC only V1: 5 V, μC and CAN V1: 3.3 V, µC only V2: 5 V, CAN + onboard loads VEXT: 5 V, external loads SPI: for control and diagnosis RSTN: reset pin Watchdog Local WAKE pin Limp pin Non-volatile memory CAN partial networking CAN FD passive HVSON20
UJA1169AF-EVB UJA1169ATK/F ● ● ● ● ● ● ● ● ● ● ● ● ● ●
UJA1169AXF-EVB UJA11692ATK/X/F ● ● ● ● ● ● ● ● ● ● ● ● ● ●
UJA1169AF3-EVB UJA1169ATK/F/3 ● ● ● ● ● ● ● ● ● ● ● ● ● ●
Table 1. UJA1169A evaluation boards and device overview
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NXP Semiconductors UM11758
UJA1169A evaluation boards
2 Overview of boards
Top and bottom views of the UJA1169AXF-EVB board are illustrated in Figure 1. Unless
otherwise stated, the information in this section applies to all UJA1169A evaluation
boards.
Board dimensions are 58.5 mm × 81.1 mm. Only components needed to support basic
UJA1169A functionality are included. All boards contain circuitry for reverse polarity-
protected battery supply, status LEDs for BAT, V1, V2/VEXT and LIMP signals, external
PNP transistor for thermal management, local wake-up and CAN bus termination. The
boards also provide several header rows (2.54 mm pitch) for connecting MCU interface
and application signals. The headers on the bottom are compatible with the Arduino
Uno pinout order, allowing the board to be connected directly to a variety of NXP MCU
evaluation boards.
Figure 1. UJA1169AXF-EVB top and bottom views
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NXP Semiconductors UM11758
UJA1169A evaluation boards
2.1 Ground connections
All ground pins are connected to the ground plane.
Ground connections
J2-02
J3-07/12
J4-13
J5-11/13
J6-02/03
J9-02
Table 2. Ground connections
2.2 Power supply connections
2.2.1 Battery connections
An external power supply must be connected to either power jack J6 or 2-pin header J2,
as illustrated in Figure 2.
UJA1169A UJA1169Ax-EVB
BAT (pin 14) J2-01 or J6-01: connect to 12 V battery supply; pin BAT on the device is
connected via Schottky diode D1.
J5-01 and J5-15: pin VIN on the UJA1169Ax-EVB board is connected,
by default, to the battery supply via jumper J8; remove jumper J8 to
disconnect VIN on J5 from the battery supply.
Table 3. BAT/VIN connections
Both supply circuits are routed via polarity protection Schottky diode D1 in order to block
reverse currents. Decoupling capacitors C1 and C2 are provided to stabilize the input
voltage and remove noise on the battery connection.
Green LED D2 lights up once the 12 V power supply has been connected.
By default, the UJA1169Ax-EVB evaluation board battery supply is routed to the MCU
board via pin VIN on the Arduino connector, allowing the supply to the entire module to
be managed via the UJA1169Ax-EVB board. This feature can be disabled by removing
jumper J8, disconnecting the battery supply from pin VIN.
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NXP Semiconductors UM11758
UJA1169A evaluation boards
J2
J5
J8
aaa-045442
UJA1169A
BAT (p14)
GND
(p1,4,16,19)
12 V
GND
J6
C2
0.1 µF
C1
100 µF
R1
1 kΩ
D2
LED
D1
Schottky
diode
VIN
Figure 2. 12 V power supply connection options
2.2.2 V1/PNP connections
The V1 supply voltage is generated by the internal 5 V or 3.3 V regulator, depending
on the UJA1169A variant, and is intended to supply the external microcontroller. It also
determines the IO reference level.
The V1 output voltage can be accessed at pin 8 on connector J3. Decoupling capacitor
C8 is provided to stabilize the output voltage and remove noise. LED D5, connected
via resistor R9, indicates the status of V1 (on when V1 active). Jumper J7 can be used
to connect V1 to J5-03 if needed as an MCU IO reference voltage. PNP pins can be
accessed at connector J9 (see Figure 7).
UJA1169A UJA1169Ax-EVB
V1 (pin 5) J3-08 provides 3.3 V (UJA1169AF3-EVB only) or 5 V for MCU
supply
J5-03: pin V1 is connected to the IOREF signal on header J5 via
jumper J7, e.g. for the MCU IO supply
VEXCTRL (pin 15) TP4
VEXCC (pin 6) J9-01: connected to the collector of the onboard PNP transistor
PNP UJA1169Ax-EVB
B (pin 4) J9-03: connected to the base of the onboard PNP transistor
C (pin 5) J9-01: connected to the collector of the onboard PNP transistor
E (pin 1,2,3) J9-04: connected indirectly via R4, 0 Ω to emitter of the onboard
PNP transistor
Table 4. V1/PNP connections
The internal V1 voltage regulator on the UJA1169A can deliver up to 250 mA without
the need for an external PNP transistor. However, if critical thermal requirements need
to be satisfied, it is possible to connect one or more external PNP transistors to share
the total V1 load current, and therefore also share the thermal dissipation. The PNP
transistor switches on when the load current exceeds the selected PNP activation
threshold, Ith(act)PNP, while the battery supply voltage is above the PNP activation
threshold, Vth(act)PNP. The main regulation loop inside the UJA1169A continues to handle
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NXP Semiconductors UM11758
UJA1169A evaluation boards
all dynamic load changes within the package while the external PNP delivers additional
supply current to the application.
Detailed information on the functionality and operation of the UJA1169A can be found in
the data sheet and application hints (see Section 7).
2.2.2.1 UJA1169A with one PNP
By default, all UJA1169Ax-EVB boards are delivered with an onboard PNP (e.g.
PHPT61003PY from Nexperia). A simplified circuit diagram is shown in Figure 3.
Shunt resistor R13 is used to limit the current delivered by the external PNP transistor
and to protect the PNP transistor against a V1 short-circuit to GND.
Pull-up resistor R15 is used to pull up the PNP base voltage to prevent it floating (e.g. if
R10 has been removed) and therefore ensure that the PNP is turned OFF.
Filter capacitor C9 is needed to protect V1 against an overvoltage during RF-injection on
the battery line. For EMI optimization, C9 is placed close to the PNP emitter.
R4 and R10 are provided to allow the PNP to be easily disconnected.
aaa-045443
D5
LED
R9
1 k
GND
V1
J3
UJA1169A
J9
J5
V1 (p5)
VEXCC (p6)
VEXCTRL (p15)
GND
(p1, 4, 16, 19)
VDD
PNP_C
PNP_B
GND
BAT
BAT
GND
R13
1.6 Ω J7
R15
100 k
R10
0 Ω
PNP
R4
0 Ω
C8
6.8 F
C9
10 nF
Figure 3. Simplified schematic of UJA1169Ax-EVB with one PNP.
Figure 4. UJA1169Ax-EVB PCB configured to operate with one PNP.
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NXP Semiconductors UM11758
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2.2.2.2 UJA1169A without an external PNP
As already discussed, the UJA1169Ax-EVB can operate using only the V1 regulator in
applications where thermal considerations are not critical. For this option, resistors R4
and R10 must be removed, as illustrated in Figure 5 and Figure 6.
aaa-045490
D5
LED
R9
1 k
GND
V1
J3
UJA1169A
J9
J5
V1 (p5)
VEXCC (p6)
VEXCTRL (p15)
GND
(p1, 4, 16, 19)
VDD
PNP_C
PNP_B
GND
BAT
BAT
GND
R13
1.6 Ω J7
R15
100 k
R10
0 Ω
PNP
R4
0 Ω
C8
6.8 F
C9
10 nF
Figure 5. UJA1169Ax-EVB PCB configured to operate without a PNP.
Figure 6. UJA1169Ax-EVB PCB configured to operate without a PNP.
2.2.2.3 UJA1169Ax-EVB with multiple external PNPs
If thermal dissipation is so high that it needs to be distributed over a number of
components, multiple PNPs can be connected in parallel. A single onboard PNP is
included. Additional PNPs can be connected via header J9, as illustrated in Figure 7.
An emitter resistor is needed for each PNP to balance the current between the devices
(e.g. 10 Ω). Make sure the resistor selected can handle the expected power dissipation.
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NXP Semiconductors UM11758
UJA1169A evaluation boards
aaa-045491
D5
LED
R9
1 k
GND
V1
J3
UJA1169A
J9
J5
V1 (p5)
VEXCC (p6)
VEXCTRL (p15)
GND
(p1, 4, 16, 19)
VDD
PNP_C
PNP_B
GND
BAT
BAT
additional PNP(s)
GND
R13
1.6 Ω J7
R15
100 k
R10
0 Ω
PNP
C8
6.8 F
C9
10 nF
R15
100 k
PNP
R4
10 Ω
R4
10 Ω
C9
10 nF
R15
100 k
PNP
R4
10 Ω
C9
10 nF
Figure 7. Simplified schematic of UJA1169Ax-EVB with multiple PNPs.
Figure 8. UJA1169Ax-EVB PCB configured to operate with multiple PNPs.
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NXP Semiconductors UM11758
UJA1169A evaluation boards
2.2.3 V2/VEXT connection
UJA1169A devices contain a second on-chip 5 V regulator. On the UJA1169ATK,
UJA1169ATK/F, UJA1169ATK/3 and UJA1169ATK/F/3 variants, this regulator (V2)
supplies the internal CAN transceiver and/or additional onboard hardware. On the
UJA1169ATK/X and UJA1169ATK/X/F variants, the second regulator (VEXT) is intended
to supply off-board components such as sensors.
Both V2 and VEXT can deliver up to 100 mA. A decoupling capacitor (C10) is connected
between the pin and ground on the board. LED D6 lights up when the V2/VEXT output is
active.
The V2 (UJA1169AF-EVB and UJA1169AF3-EVB) or VEXT (UJA1169AXF-EVB) output
voltage is accessible on connector J3 (pin 10).
UJA1169A UJA1169Ax-EVB
V2/VEXT (pin 13) J3-10: provides 5 V supply for internal ECU/external loads
Table 5. VEXT connection
aaa-045535
UJA1169A
V2/VEXT(p13)
GND(p1,4,16,19)
V2/VEXT
GND
J3
R8
1 kΩ
D6
LED
C10
6.8 µF
Figure 9. V2/VEXT supply connections
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2.3 CAN communication circuitry
The UJA1169Ax-EVB evaluation boards contain typical CAN communication circuitry.
The CANH and CANL bus signals are output on connector J1.
UJA1169A UJA1169Ax-EVB
CANH (pin 18) J1-01: connect to HIGH-level CAN bus line
CANL (pin 17) J1-02: connect to LOW-level CAN bus line
Table 6. CAN bus line connections
Equipped with termination resistors R2 and R3, the UJA1169Ax-EVB evaluation boards
are configured to be used as termination nodes in a CAN network. If the CAN network
is already terminated at both ends, it is recommended to remove R2 and R3 or replace
them with higher value resistors to ensure that the impedance on the bus meets the CAN
bus load specification, typically 60 Ω.
aaa-045540
UJA1169A
CANH(p18)
CANL(p17)
L1
100 µH
R3
62 Ω
C4
4.7 nF
D3
PESD1CAN
CANH
CANL
J1
split
termination
common-mode
choke ESD protection diodes
R2
62 Ω
Figure 10. CAN bus interface circuitry (relevant for the entire UJA1169A-EVB family)
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