NXP Semiconductors AN13125 Installation and operating instructions

AN13125
IW416 Design Guide
Rev. 1 — 26 May 2021 Application note
Document information
Information Content
Keywords Power supply, clock source, reset, host interface, RF interface, PCB layout,
PCB stackup
Abstract Provides design guidelines for IW416 device.

NXP Semiconductors AN13125
IW416 Design Guide
Rev Date Description
v.1 20210526 Initial version
Revision history
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NXP Semiconductors AN13125
IW416 Design Guide
1 Overview
This document provides design guidelines for NXP IW416 device. The IW416 is a highly
integrated Wi-Fi® 4 (2.4 GHz/5 GHz) and Bluetooth® 5.1 single-chip solution.
The IW416 is available in two package options – QFN and WLCSP.
NXP releases reference designs to provide examples on how to design a PCB using the
device. We strongly recommend follow these design guidelines closely. Please contact
your NXP representative to schedule a design review and discuss design options.
Note: In the following sections, the IW416 may be referred to as “Wireless SoC”
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NXP Semiconductors AN13125
IW416 Design Guide
2 Power supply
2.1 Power supply overview
Table 1 lists the power supplies.
Supply Description Typical value
VCORE Core power supply 1.05 V
AVDD18 Analog power supply 1.8 V
VPA Wi-Fi PA power supply 2.2 V
VIO Digital I/O power supply 1.8 V or 3.3 V
VIO_SD SDIO power supply 1.8 V or 3.3 V
VIO_RF RF power supply 1.8 V or 3.3 V
Table 1. Power supplies
A “2-wire” power management interface is used to lower the core voltage to reduce
power consumption in sleep mode. The power management interface uses two control
signals, DVSC1 and DVSC0, to dynamically adjust the voltage level from the power
management IC (PMIC). Under normal operation, the core voltage level is 1.05 V. In
sleep mode, the core voltage is dropped to 0.8 V.
The following sections describe PMIC solutions from MPS, NXP, and Marvell
manufacturers:
•MPS: MP2182, MP2162A, MP8904
•Marvell 88PG823
•NXP PM823
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NXP Semiconductors AN13125
IW416 Design Guide
2.2 Power supply using MPS PMICs
Figure 1 shows a simplified block diagram using the MPS MP2182, MP2162A and
MP8904. Two control signals, DVSC1 and DVSC0, are used to control the core voltage
level. Table 2 shows the part numbers.
Figure 1. Power supply by MPS PMICs
Manufacturer Part number
MPS BUCK: MP2162AGQH-C867-Z
MPS BUCK: MP2182GTL-C867-Z
MPS BUCK: MP8904DD-C867-LF-Z
Table 2. MPS PMICs part numbers
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NXP Semiconductors AN13125
IW416 Design Guide
2.3 Power supply using NXP PM823 or Marvell 88PG823
Figure 2 shows a simplified block diagram using the NXP PM823 or Marvell 88PG823
(QFN). Two control signals, DVSC1 and DVSC0, are used to control the core voltage
level. Table 3 shows the part numbers.
Figure 2. Power supply by 88PG823 (QFN)
Manufacturer Part number
Marvell QFN package option: 88PG823-xx-NPD2C000
Marvell WLCSP package option: 88PG823-xx-CBK2-T
NXP QFN package option: PM823HN/A0CHP
NXP WLCSP package option: PM823UK/A0CZ
Table 3. Marvell and NXP PMICs part numbers
2.4 Power-up sequence requirements
All the power rails must meet correct power-up sequence. Refer to IW416 data sheet.
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NXP Semiconductors AN13125
IW416 Design Guide
2.5 PCB layout guidelines
Refer to the following PCB layout guidelines for power supply.
•Follow the PMIC schematic/layout exactly. Any deviation must be reviewed with PMIC
vendor Applications Engineer.
•Use power planes (layer) and polygons to lower the power impedance.
•Use decoupling capacitors with low ESR
•Place the power vias and ground vias as close as possible to the decoupling
capacitors, as shown in Figure 3.
Figure 3. Power vias and ground vias
•Ensure each power pin has its own decoupling capacitor. Place the decoupling
capacitors as close as possible to the power pin.
•The power from source to the power pin should go through the decoupling network
before connecting to the power pin. As shown in Figure 4
Figure 4. Example of power trace outing to power pin
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NXP Semiconductors AN13125
IW416 Design Guide
•There is a decoupling capacitor for each power pin and a bulk capacitor for each rail.
Place the decoupling capacitor as close as possible to the power pin, then place the
bulk capacitor. Figure 5 shows an example where C9 is the decoupling capacitor for K5
pin. In this example, place C9 as close as possible to K5 pin, and place C58 close to
C9.
Figure 5. Decoupling capacitor and bulk capacitor placements
•Do not place any analog power plane (trace) as ring and loop in the layout. Figure 6
shows the correct top layer (left hand side of the figure) and the incorrect top layer
(right hand side). In the correct top layer, there is no loop on the AVDD18 net.
Figure 6. Power plane without loop
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NXP Semiconductors AN13125
IW416 Design Guide
3 Clock source
Two main clock sources are available: a crystal, and an external oscillator. An optional
sleep clock is also available for low power mode.
3.1 Crystal
In a typical application, a 26 MHz or 40 MHz crystal is used as a reference clock source.
We recommend to select a crystal with ±10 ppm at 25°C and ±10 ppm over the operating
temperature range. For detailed crystal specifications, refer to IW416 data sheet.
Figure 7 shows the crystal connections. The internal capacitor in the Wireless SoC is
used to tune the crystal frequency. External loading capacitors are typically not needed.
Figure 7. Typical crystal circuit
PCB layout guidelines for the crystal
Refer to the following guidelines for the crystal:
•Place the crystal close to the device and keep it as far away as possible from the RF
side of the device and high frequency signal traces such as SDIO, PCIe, or USB.
•Keep XTAL_IN and XTAL_OUT traces far from any noisy or switching signal, at a
distance of at least ten times the substrate height.
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NXP Semiconductors AN13125
IW416 Design Guide
•Keep XTAL_IN and XTAL_OUT traces as short as possible, as shown in Figure 8.
Figure 8. Crystal PCB layout
•Make sure XTAL_IN and XTAL_OUT traces are referenced to the solid ground plane in
the second layer.
•Place the ground guard with ground stitching vias around the XTAL_IN and XTAL_OUT
traces, as shown in Figure 8.
•To minimize the reference clock signals, cut out all internal metal planes under the
crystal and keep the last ground plane as the reference plane.
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