ON Semiconductor ECLTSSOP20EVB User manual

©Semiconductor Components Industries, LLC, 2012
January, 2012 −Rev. 2
1Publication Order Number:
EVBUM2057/D
ECLTSSOP20EVB
Evaluation Board User's
Manual for High Frequency
TSSOP20
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 20−lead TSSOP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 20−lead TSSOP device
samples. The board provides a high bandwidth 50 W
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
•Information on 20−lead TSSOP Evaluation Board
•Assembly Instructions
•Appropriate Lab Setup
•Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−Up
The 20−lead TSSOP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay−Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the 50
Winternal impedance in the oscilloscope as a termination for
ECL devices. The first layer or primary trace layer is 0.008″
thick Rogers RO4003 material, which is designed to have
equal electrical length on all signal traces from the device
under the test (DUT) to the sense output. The second layer
is the 1.0 oz copper ground. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is the power plane (VCC & VEE)
and a portion of this layer is a ground plane. The fourth layer
is the secondary trace layer.
Figure 1. Top View of the 20−lead TSSOP Evaluation Board
http://onsemi.com
EVAL BOARD USER’S MANUAL

ECLTSSOP20EVB
http://onsemi.com
2
Figure 2. Bottom View of the 20−lead TSSOP Evaluation Board
Bottom View
Expanded Bottom View
Figure 3. Evaluation Board Lay−up
LAY−UP DETAIL
4 LAYER
LAYER 1 (TOP SIDE) 1 OZ
ROGERS 4003 0.008 in
LAYER 2 (GROUND PLANE P1) 1 OZ
FR−4 0.020 in
LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ
FR−4 0.025 in
LAYER 4 (BOTTOM SIDE) 1 OZ
SILKSCREEN (TOP SIDE)
0.062 $0.007
Board Layout
The 20−lead TSSOP evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least eight possible configurable options. Table 1, list the
devices and the relevant configuration that utilizes this PCB
board. Lists of components and simple schematics are
located in Figures 6 through 12. Place SMA connectors on
J1 through J20, 50 Wchip resistors between ground pad and
Pin 1 pad through Pin 20 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01
mF and C1, C2, and C3 are 0.1ĂmF); (See Figure 5).

ECLTSSOP20EVB
http://onsemi.com
3
Figure 4. Evaluation Board Layout
Top View
Bottom View

ECLTSSOP20EVB
http://onsemi.com
4
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Ground
C5
C4
VEE
VCC
Pin 20
Pin 19
Pin 18
Pin 17
Pin 16
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Figure 5. Enlarged Bottom View of the Evaluation Board
Table 1. Configuration List
Configuration Comments Device
1See Figure 6 EP14, LVEP14
2See Figure 7 EP17, LVEP17
3See Figure 8 EP29
4See Figure 9 EP40
5See Figure 10 EP56, LVEP56
6See Figure 11 EP57
7See Figure 12 EP139

ECLTSSOP20EVB
http://onsemi.com
5
Evaluation Board Assembly Instructions
The 20−lead TSSOP evaluation board is designed for
characterizing devices in a 50 Wlaboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of placing a termination
resistor depending on the input/output configuration (see
Table 1, Configuration List). Table 11 contains the Bill of
Materials for this evaluation board.
Solder the Device on the Evaluation Board
The soldering can be accomplished by hand soldering or
soldering re−flow techniques. Make sure pin 1 of the device
is located next to the white dotted mark and all the pins are
aligned to the footprint pads. Solder the 20−lead TSSOP
device to the evaluation board.
Connecting Power and Ground Planes
For standard ECL lab setup and test, a split (dual) power
supply is required enabling the 50 Winternal impedance in
the oscilloscope to be used as a termination of the ECL
signals (VTT = VCC – 2.0 V, in split power supply setup, VTT
is the system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 2, Power Supply Levels).
Table 2. Power Supply Levels
Power Supply VCC VEE GND
5.0 V 2.0 V −3.0 V 0.0 V
3.3 V 2.0 V −1.3 V 0.0 V
2.5 V 2.0 V −0.5 V 0.0 V
Connect three banana jack sockets to VCC, VEE, and GND
labeled holes. Wire bond the appropriate device pin pad on
the bottom side of the board to VCC and VEE power stripes.
(Device specific, please see configuration for each desired
device. See Figure 5)
It is recommended to solder 0.01 mF capacitors to C4 and
C5 to reduce the unwanted noise from the power supplies.
C1, C2, and C3 pads are provided for 0.1 mF capacitor to
further diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.
Termination
All ECL outputs need to be terminated to VTT (VTT = VCC
–2.0 V = GND) via a 50 Wresistor. 0402 chip resistor pads
are provided on the bottom side of the evaluation board to
terminate the ECL driver (More information on termination
is provided in AN8020). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads. For ease of assembly,
it is advised to place and solder termination resistors on its
vertical (side) position, instead of its original or flat position.
Installing the SMA Connectors
Each configuration indicates the number of SMA
connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board on J1
through J20. Please note that alignment of the signal
connector pin of the SMA can influence the lab results. The
reflection and launch of the signals are largely influenced by
imperfect alignment and soldering of the SMA connector.
Validating the Assembled Board
After assembling the evaluation board, it is recommended
to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.

ECLTSSOP20EVB
http://onsemi.com
6
CONFIGURATIONS
Figure 6. Configuration 1
J1
J10
J9
J7
J6
J5
J4
J2 J19
J13
J12
J14
J16
J17
SMA
CONNECTORS
BANANA JACK
PLUG
NORMAL TOP VIEW
EP14 / LVEP14
J3
J8
PIN 1
EXPANDED BOTTOM VIEW
EP14 / LVEP14
WIRE
VCC
VEE
0603 CHIP
CAPACITOR
0.1 mF
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
Table 3. Configuration 1 (Device EP14 and LVEP14)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes No Yes No
Resistor No No No No No No No No No No No Ye s Ye s Yes No Yes Yes No Yes No
Power No No No No No No No No No No VEE No No No No No No VCC No VCC

ECLTSSOP20EVB
http://onsemi.com
7
Figure 7. Configuration 2
NORMAL TOP VIEW
EP17 / LVEP17
PIN 1
EXPANDED BOTTOM VIEW
EP17 / LVEP17
WIRE
J9
J7
J6
J5
J4
J2 J19
J13
J12
J14
J16
J17
SMA
CONNECTORS
BANANA JACK
PLUG
J3
J8
0603 CHIP
CAPACITOR
0.1 mF
J15
J18
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
Table 4. Configuration 2 (Device EP17 and LVEP17)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Ye s No
Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No
Power VCC No No No No No No No No No VEE No No No No No No No No VCC

ECLTSSOP20EVB
http://onsemi.com
8
Figure 8. Configuration 3
NORMAL TOP VIEW
EP29
PIN 1
EXPANDED BOTTOM VIEW
EP29
WIRE
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
J9
J7
J6
J5
J4
J2 J19
J13
J12
J14
J16
J17
SMA
CONNECTORS
BANANA JACK
PLUG
J3
J8
0603 CHIP
CAPACITOR
0.1 mF
J15
J18
J1
Table 5. Configuration 3 (Device EP29)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Ye s Ye s Yes Yes Yes Yes No
Resistor Yes No Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No No No No Yes Yes No
Power No No No No No No No No No VCC VEE No No No No No No No No VCC

ECLTSSOP20EVB
http://onsemi.com
9
Figure 9. Configuration 4
NORMAL TOP VIEW
EP40
PIN 1
EXPANDED BOTTOM VIEW
EP40
WIRE
J9
J7
J6
J5
J4
J2 J19
J14
J16
J17
SMA
CONNECTORS
BANANA JACK
PLUG
J3
J8
0603 CHIP
CAPACITOR
0.1 mF
J15
J10
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
(Option 1 Internal Termination Resistor)
PIN 1
EXPANDED BOTTOM VIEW
EP40
WIRE
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
(Option 2 External Termination Resistor)
Table 6. Configuration 4 (Device EP40) (Options 1 & 2)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Option 1 Internal Termination Resistor Configuration
Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes No Yes No
Resistor No No No No No No No No No No No No No No No No No No No No
Power VEE Gnd Gnd No No No No Gnd Gnd No VEE No VCC No No No No VCC No VCC
Option 2 External Termination Resistor Configuration
Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes No Yes No
Resistor No No No Yes Yes Yes Yes No No No No No No No No No No No No No
Power VEE No No No No No No No No No VEE No VCC No No No No VCC No VCC

ECLTSSOP20EVB
http://onsemi.com
10
Figure 10. Configuration 5
NORMAL TOP VIEW
EP56 / LVEP56
PIN 1
EXPANDED BOTTOM VIEW
EP56 / LVEP56
WIRE
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
J9
J7
J6
J5
J4
J2 J19
J13
J12
J16
J17
SMA
CONNECTORS
BANANA JACK
PLUG
0603 CHIP
CAPACITOR
0.1 mF
J15
J18
J1
J10
Table 7. Configuration 5 (Device EP56 and LVEP56)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Ye s Ye s Yes No
Resistor Yes Yes No Yes Yes Yes Yes No Yes Yes No No No No Yes Yes Yes No No No
Power No No No No No No No No No No VEE No No VCC No No No No No VCC

ECLTSSOP20EVB
http://onsemi.com
11
Figure 11. Configuration 6
NORMAL TOP VIEW
EP57
PIN 1
EXPANDED BOTTOM VIEW
EP57
WIRE
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
J9
J7
J6
J5
J4
J2 J19
J13
J12
J16
SMA
CONNECTORS
BANANA JACK
PLUG
J3
J8
0603 CHIP
CAPACITOR
0.1 mF
J15
J18
Table 8. Configuration 6 (Device EP57)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector No Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No Yes Yes No Ye s Ye s No
Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Ye s Ye s No
Power VCC No No No No No No No No VEE VEE No No VCC No No VCC No No VCC

ECLTSSOP20EVB
http://onsemi.com
12
Figure 12. Configuration 7
NORMAL TOP VIEW
EP139
PIN 1
EXPANDED BOTTOM VIEW
EP139
WIRE
VCC
VEE
0603 CHIP
CAPACITOR
0.01 mF
0805 CHIP
CAPACITOR
0.01 mF
0402 CHIP
RESISTOR
50 W
J9
J7
J6
J5
J4
J2 J19
J13
J12
J14
J16
J17
SMA
CONNECTORS
BANANA JACK
PLUG
J3
0603 CHIP
CAPACITOR
0.1 mF
J15
J18
J10
Table 9. Configuration 7 (Device EP139)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector No Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No
Resistor No Yes Yes Yes Yes No Ye s No Ye s Ye s No No No No No No No No No No
Power VCC No No No No No No VCC No No VEE No No No No No No No No VCC

ECLTSSOP20EVB
http://onsemi.com
13
LAB SETUP
Figure 13. Example of Standard Lab Setup (Configuration 1)
Power Supply
Trigger
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Trigger
J1
J2
J3
J4
J5
J6
J7
J8
J13
J12
D
U
T
Test
Measuring
Equipment Differential
Signal
Generator
VCC GND VEE
Out1
Out1
1. Connect appropriate power supplies to VCC, VEE,
and GND.
For standard ECL lab setup and test, a split (dual)
power supply is required enabling the 50 W
internal impedance in the oscilloscope to be used
as a termination of the ECL signals (VTT = VCC
– 2.0 V, in split power supply setup, VTT is the
system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 10).
2. Connect a signal generator to the input SMA
connectors. Setup input signal according to the
device data sheet.
3. Connect a test measurement device on the device
output SMA connectors.
NOTE: The test measurement device must contain 50 W
termination.
Table 10. Power Supply Levels
Power Supply VCC VEE GND
5.0 V 2.0 V −3.0 V 0.0 V
3.3 V 2.0 V −1.3 V 0.0 V
2.5 V 2.0 V −0.5 V 0.0 V

ECLTSSOP20EVB
http://onsemi.com
14
Table 11. Bill of Materials
Components Manufacturer Description Part Number Web Site
SMA Connector Johnson
Components*
SMA Connector, Side
Launch, Gold Plated
142−0701−851 http://www.johnsoncomponents.com
Banana Jack Keystone* Standard Jack 6096 http://www.keyelco.com
Miniature Jack 6090
Chip Capacitor Johanson
Dielectric*
0603 0.01 mF500R14Z100MV4E http://www.johansondielectrics.com
0805 0.01 mF500R15Z100MV4E
0603 0.1 mF250R14Z101MV4E
Chip Resistor Panasonic* 0402 50 W±1% Precision
Think Film Chip Resistor
ERJ−2RKF49R9X http://www.panasonic.com
Evaluation Board ON Semiconductor TSSOP 20 Evaluation Board ECLTSSOP20EVB http://www.onsemi.com
Device Samples ON Semiconductor TSSOP 20 Package Device Various http://www.onsemi.com
*Components are available through most distributors, i.e. www.newark.com, www.digikey.com.

ECLTSSOP20EVB
http://onsemi.com
15
Figure 14. Gerber Files
Top View
Second Layer (Ground Plane)

ECLTSSOP20EVB
http://onsemi.com
16
Figure 15. Gerber Files
Third Layer (Power and Ground Plane)
(Left side −VCC, Right side −VEE, Middle Box −Ground)
Bottom Layer

www.onsemi.com
1
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or
other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is
subject to all applicable copyright laws and is not for resale in any manner.
The evaluation board/kit (research and development board/kit) (hereinafter the “board”) is not a finished product and is as such not available for sale to consumers. The board is only intended
for research, development, demonstration and evaluation purposes and should as such only be used in laboratory/development areas by persons with an engineering/technical training
and familiar with the risks associated with handling electrical/mechanical components, systems and subsystems. This person assumes full responsibility/liability for proper and safe handling.
Any other use, resale or redistribution for any other purpose is strictly prohibited.
The board is delivered “AS IS” and without warranty of any kind including, but not limited to, that the board is production−worthy, that the functions contained in the board will meet your
requirements, or that the operation of the board will be uninterrupted or error free. ON Semiconductor expressly disclaims all warranties, express, implied or otherwise, including without
limitation, warranties of fitness for a particular purpose and non−infringement of intellectual property rights.
ON Semiconductor reserves the right to make changes without further notice to any board.
You are responsible for determining whether the board will be suitable for your intended use or application or will achieve your intended results. Prior to using or distributing any systems
that have been evaluated, designed or tested using the board, you agree to test and validate your design to confirm the functionality for your application. Any technical, applications or design
information or advice, quality characterization, reliability data or other services provided by ON Semiconductor shall not constitute any representation or warranty by ON Semiconductor,
and no additional obligations or liabilities shall arise from ON Semiconductor having provided such information or services.
The boards are not designed, intended, or authorized for use in life support systems, or any FDA Class 3 medical devices or medical devices with a similar or equivalent classification in
a foreign jurisdiction, or any devices intended for implantation in the human body. Should you purchase or use the board for any such unintended or unauthorized application, you shall
indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor
was negligent regarding the design or manufacture of the board.
This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC,
CE or UL, and may not meet the technical requirements of these or other related directives.
FCC WARNING – This evaluation board/kit is intended for use for engineering development, demonstration, or evaluation purposes only and is not considered by ON Semiconductor to
be a finished end product fit for general consumer use. It may generate, use, or radiate radio frequency energy and has not been tested for compliance with the limits of computing devices
pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment may cause interference with radio
communications, in which case the user shall be responsible, at its expense, to take whatever measures may be required to correct this interference.
ON Semiconductor does not convey any license under its patent rights nor the rights of others.
LIMITATIONS OF LIABILITY: ON Semiconductor shall not be liable for any special, consequential, incidental, indirect or punitive damages, including, but not limited to the costs of
requalification, delay, loss of profits or goodwill, arising out of or in connection with the board, even if ON Semiconductor is advised of the possibility of such damages. In no event shall
ON Semiconductor’s aggregate liability from any obligation arising out of or in connection with the board, under any theory of liability, exceed the purchase price paid for the board, if any.
For more information and documentation, please visit www.onsemi.com.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: [phone]
LITERATURE FULFILLMENT:
Email Requests to: [email protected]
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: [phone]
For additional information, please contact your local Sales Representative
◊