Pickering 41-320 User manual

Page 1
pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
USER MANUAL
DUAL 70MSPS PXI WAVEFORM DIGITIZER MODULE
(MODEL No. 41-320)
www.pickeringtest.com
pickering
ISO 9002
Reg No. FM38792
Issue 3.2 January 2013

Page ii
pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
© COPYRIGHT (2013) PICKERING INTERFACES. ALL RIGHTS RESERVED.
No part of this publication may be reproduced, transmitted, transcribed, translated or stored in any form, or
by any means without the written permission of Pickering Interfaces.
Technical details contained within this publication are subject to change without notice.

Page iii
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
TECHNICAL SUPPORT
For Technical Support please contact Pickering Interfaces either by phone, fax, the website or via e-mail.
WARRANTY
All products manufactured by Pickering Interfaces are warranted against defective materials and workmanship for a period of two
years, excluding PXI chassis, from the date of delivery to the original purchaser. Any product found to be defective within this period
will, at the discretion of Pickering Interfaces be repaired or replaced.
Products serviced and repaired outside of the warranty period are warranted for ninety days.
Extended warranty and service are available. Please contact Pickering Interfaces by phone, fax, the website or via e-mail.
ENVIRONMENTAL POLICY
Pickering Interfaces operates under an environmental management system similar to ISO 14001.
environment. Pickering Interfaces aims to design and operate products in a way that protects the environment and the health and
safety of its employees, customers and the public. Pickering Interfaces endeavours to develop and manufacture products that can
be produced, distributed, used and recycled, or disposed of, in a safe and environmentally friendly manner.
Worldwide Technical Support and Product Information
http://www.pickeringtest.com
Pickering Interfaces Headquarters
Stephenson Road Clacton-on-Sea CO15 4NL United Kingdom
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Observe the Electrical Hazard Warning detailed in Section 8.
Observe the Electrostatic Sensitive Device Caution detailed in Section 8.
Pickering Interfaces GmbH
Johann-Karg-Straße 30
D-85540
Haar-Salmdorf
Germany
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces AB
Karl Nordströmsväg 31
432 53
Varberg
Sweden
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ˇ
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email [email protected]
Pickering Interfaces Inc.
(East Coast Regional Office)
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Pickering Interfaces strives to fulfil all relevant environmental laws and regulations and reduce wastes and releases to the

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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
Copyright Statement .......................................................... ii
Technical Support and Warranty....................................... iii
Contents (this page)........................................................... v
Section 1
Technical Specication...................................................... 1.1
Section 2
Technical Description ........................................................ 2.1
Introduction................................................................... 2.1
Analogue Circuit........................................................... 2.2
Triggering ...................................................................... 2.3
Clocking ........................................................................ 2.6
Memory.......................................................................... 2.7
Calibration..................................................................... 2.7
Register Asignment...................................................... 2.8
Section 3
Installation........................................................................... 3.1
Software Installation .................................................... 3.1
Hardware Installation ................................................... 3.21
Section 4
Programming Guide........................................................... 4.1
Programming Options For Pickering PXI Cards........ 4.1
Software Utility ............................................................. 4.3
Adjusting the Instrument ............................................. 4.4
Analysing the Data ....................................................... 4.5
Section 5
Connector Information....................................................... 5.1
Section 6
Trouble Shooting ................................................................ 6.1
Section 7
Maintenance Information................................................... 7.1
Software Update ........................................................... 7.1
Component Layout....................................................... 7.1
Section 8
Warnings and Cautions ..................................................... 8.1
CONTENTS

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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
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Section 1 - tecHnicAL SPeciFicAtion
Page 1.1
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
SECTION 1 - TECHNICAL SPECIFICATION
PXI Switch & Instrumentation
Pickering Interfaces www.pickeringtest.com
41-320
Dual PXI Waveform Digitizer Module
●14-Bit Dual Channel Digitizer
●Flexible Differential or Single Ended Input
●Internal, Selectable 50MHz and 70MHz
Clocks
●Selectable Filters to Reduce Out Of Band
Signals
●AC or DC Coupled Termination With
Adjustable DC Pedestal
●PXI Trigger Support for Synchronizing
Measurements
●512K Word Signal Capture Memory
●Excellent Dynamic Range
●LabView and LabWindows Libraries
The 41-320 Dual PXI Waveform Digitizer Module is a
high performance dual-channel 14-bit digitizer capable
of operating at sample rates of 70MHz. It has been
optimized for high performance and excellent SFDR.
This makes it an ideal tool for capturing analog signals
for digital analysis.
DUAL PXI WAVEFORM DIGITIZER
41-320
The digitizer has fully differential input terminals to
reduce the effects of external noise and common mode
signals found in typical test systems. The inputs can
also be set to single ended mode for operation in more
electrically quiet environments. The input impedance
can be set to 10kΩor 50Ωwith DC coupling. The 50Ω
setting can also be AC coupled to allow capture of
signals on a DC pedestal without an excessive input
current. Full scale input voltage can be switched in
ranges between 1 Volt and 25 Volt peak to peak.
For applications requiring the capture of a DC coupled
signal on a voltage pedestal the 41-320 can be
adjusted to have a DC offset applied to the input.
This ensures that the full resolution of the converter is
maintained.
The input to each digitizer can be filtered with a
30MHz, 15MHz or 6MHz low pass filter. This is to
restrict the impact of broad-band spurious signals
when capturing input signals containing lower
frequencies.
The module supports external trigger sources, star
triggering and PXI triggering. This allows synchronized
measurements to be performed in a PXI test system.
The 41-320 is supplied with easy to use soft front
panels and VISA kernel drivers
Supplied Soft Front Panel For the 41-320 PXI
Waveform Digitizer Module
ISSUE 5.3 APR 2012
This Product Is No
Longer Available From
Pickering Interfaces.
Please Refer To The
Third Party PXI Product
Guide For An Equivalent
Module.

Page 1.2
Section 1 - tecHnicAL SPeciFicAtion
DuAL 70MSPS PXi WAveForM Digitizer MoDuLe 41-320
pickering
Pickering Interfaces are sponsor members of the PXI Systems Alliance www.pxisa.org
www.pickeringtest.com E-Mail [e-mail]
PCB Layout for the 41-320 Waveform Digitizer Module
Block Diagram for the 41-320 Waveform Digitizer Module
The Soft Front Panel For the 41-320 PXI
Waveform Digitizer Module Shown Capturing
an Amplitude Modulated Signal

Section 1 - tecHnicAL SPeciFicAtion
Page 1.3
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
PXI Switch & Instrumentation
Pickering Interfaces www.pickeringtest.com
Dynamic Performance
of the 41-320
Waveform Digitizer
Module With a 1MHz
2Vp-p Input Signal
(Input Set to 50ΩDC).
The Horizontal Scale
is 0 to 25MHz, The
Vertical Scale is Zero
to -120dB.
Dynamic Performance
of the 41-320
Waveform Digitizer
Module With a 10MHz
2Vp-p Input Signal
(Input Set to 50ΩDC).
The Horizontal Scale
is 0 to 25MHz, The
Vertical Scale is Zero
to -120dB.
Typical Frequency
Responses For The
Three Selectable Low-
Pass Filters. These
Can be Switched Into
The Input Circuit to
Reject Out of Band
Signals And Reduce
Aliasing.

Page 1.4
Section 1 - tecHnicAL SPeciFicAtion
DuAL 70MSPS PXi WAveForM Digitizer MoDuLe 41-320
pickering
Pickering Interfaces are sponsor members of the PXI Systems Alliance www.pxisa.org
www.pickeringtest.com E-Mail [e-mail]
© Copyright (2011) Pickering Interfaces. All Rights Reserved Pickering Interfaces maintains a commitment to continuous product development, consequently we reserve the right to vary from the description given in this data sheet.
Digitizer Specification
Number of channels: 2
Resolution: 14-bits
Sampling Rate: 500ks/s to 70Ms/s
Clock Source: External or Internal
Internal Clock Rate: 70Ms/s, 50Ms/s or 10Ms/s
Internal Clock Accuracy: 100ppm
External Clock Frequency: 500kHz to 70MHz
External Clock Input: 50Ω, TTL levels
Clock Division Ratio: 1 to 256
Memory: 512k samples per channel
Digitizer Input Specification
Input: Differential or single-ended
Input Impedance: 10KΩDC, 50ΩDC, or 50ΩAC
Input Range: 1Vp-p, 2Vp-p or 4Vp-p (normal)
5Vp-p 10Vp-p or 20Vp-p (with
attenuator)
Maximum Input Range: -5V to +5V (normal, with common
mode voltage)
-25 to +25 (with attenuator, with
common mode voltage)
Input Filters: None, 30MHz, 15MHz or 6MHz.
(3-pole Butterworth low pass)
Frequency Response: ±0.5dB DC to 20MHz
±2dB 20MHz to 50MHz
DC Offset: ±5V normal, 16-bit resolution
±25V with attenuator on
Dynamic Performance
Absolute accuracy: ±500µV ±0.1% of range (normal)
±2.5mV ±0.2% of range (with
attenuator)
Relative Accuracy: ±0.025% of range
SFDR (50Ms/s 2Vp-p): 80dB at 1MHz input
72dB at 10MHz input
SINAD (50Ms/s 2Vp-p): 68dB at 1MHz input
64dB at 10MHz input
Channel Crosstalk: <70dB at 1MHz
Trigger Specification
Source: Internal or external
(channels are independent)
External Input: 10kΩ, TTL levels
Internal: PXI STAR, PXI TRIG 0 to 5
or software trigger
Polarity: Selectable positive or negative
Response: Edge or Level
Programming
The 41-320 is supplied with soft front panels and a
comprehensive set of VISA drivers.
Power Requirements
+3.3V +5V +12V -12V
0.2A 0.7A 0.3A 0.3A
Width and Dimensions
Size: Single width 3U PXI/CompactPCI
instrument module
Connectors
PXI bus: 32-bit P1/J1 backplane connector
Front panel connectors: A+ input (SMB)
A- input (SMB)
B+ input (SMB)
B- input (SMB)
Clock input (SMB)
Trigger input (SMB)
PXI & CompactPCI Compliance
All Pickering Interfaces PXI modules comply with the PXI
Specification 2.2.
Safety & CE Compliance
All modules are fully CE compliant and meet applicable EU
directives: Low-voltage safety EN61010-1:2001,
EMC Immunity EN61000-6-1:2001, Emissions EN55011:1998.
Operating/Storage Conditions
Operating Conditions
Operating Temperature:
Humidity:
Altitude:
0°C to +55°C
Up to 90% non-condensing
5000m
Storage and Transport Conditions
Storage Temperature:
Humidity:
Altitude:
-20°C to +75°C
Up to 90% non-condensing
15000m
Product Order Codes
Dual PXI Waveform Digitizer Module 41-320-001
Latest Details
Please refer to our Web Site for Latest Product Details.
www.pickeringtest.com
Mating Connectors & Cabling
For connection accessories for the 41-320 module please refer
to the 90-011D RF Connector Accessories data sheet where a
complete list and documentation can be found for accessories.
Alternatively, refer to the
Pickering Interfaces “Connection
Solutions” catalog for the full
list of connector/cabling options,
including drawings, photos and
specifications. This is available in
either print or as a download.
Alternatively our web site has
dynamically linked connector/cabling
options, including pricing, for all
Pickering PXI modules.

Section 2 - tecHnicAL DeScRiPtion
Page 2.1
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
SECTION 2 - TECHNICAL DESCRIPTION
INTRODUCTION
The 41-320 is a dual channel high speed waveform digitizer card in a compact 3U PXI module. The two channels
are independant and each has its own 14 bit, 70 MSPS Analog to digital converter. The design ensures low crosstalk
and no phase error between the channels. Fig. 2.1 shows the functional block diagram from the 41-320
On the left of the diagram are the differential analog inputs, the external clock in- /output and the trigger input.
The analog input is a differential input. By switching one input to ground or to the programmable DC Offset source
it becomes a single ended input with programmable DC Offset level. The input has six range steps.
The analog signal can be ltered to remove out of band noise using the built in low pass lters.
The External Clock connection can be used as a clock input or as the internal clock output. The two channels can
sample simultaneously or at a different speed by using the clock divider.
The Trigger input allows the user to control the start of data capturing.
The output from the 14 bit analog to digital converter is captured by a 512k RAM data capture memory system.
When the 41-320 is triggered, the capture memory starts running from a user specied start address.
During the measurement an internal or external clock increments the memory counter. When the counter reaches
the value of the stop address it jumps back to the start address, or stops if the loop mode is programmed off.
The interface is on the right side of the diagram.
endaddress
endaddress
address counter
address counter
CH-B capture memory CH-A capture memory
DAC
DAC
- input - input
+input +input
DATA BUFFER
DATA BUFFER
DC-OFFSET
DAC CH-B (16 bit)
DC-OFFSET
DAC CH-A (16 bit)
14 bit ADC
14 bit ADC
TRIGGER
IN B(+)
IN A(+)
Input term.
- 10k Ohm
- 50 Ohm DC
- 50 Ohm AC
Input term.
- 10k Ohm
- 50 Ohm DC
- 50 Ohm AC
IN B(-)
IN A(-)
Data Bus
Data Bus
EXTERNAL CLOCK (in/out)
c
c
c
c
c
c
c
c
c
c
Differential to
single ended
rangable amplifier
Differential to
single ended
rangable amplifier
6MHz LPF
6MHz LPF
30MHz LPF
30MHz LPF
15MHz LPF
15MHz LPF
c
c
PXI CLK 10
CLOCK
LOGIC
TRIGGER
LOGIC
PXI STAR
PXI TRIG 0
PXI TRIG 5
70MHz
INTERNAL
CLOCK
50MHz
INTERNAL
CLOCK
PXI BUS INTERFACE
Fig. 2.1 - 41-320 Functional block diagram

Page 2.2
Section 2 - tecHnicAL DeScRiPtion pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
ANALOG CIRCUIT
The SMB connectors marked A+, A- ,B+ and B-, on the front of the 41-320, are the analog differential inputs for
channel A and channel B. If a channel is set in the single input mode the input signal must be connected to the +
input. The negative input is connected to ground by the software.
Input coupling
Fig. 2.2 shows the analog input circuit from one input. The analog input impedance is selectable, 50Ω AC, 50Ω DC
and 10kΩ DC. If the analog input is disconnected, the internal circuit is disconnected from the input by a mechanical
switch. The settings for the input mode are separate for each channel, so Channel A can be 50Ω AC differential
input, while channel B is 10kΩ DC single input.
Fig. 2.2 Analog Input Circuit
Input Ranges:
The 41-320 offers six ranges to optimize the ADC resolution to the input signal.
Table 2.1 - Input Ranges: 41-320
Range Input Offset
1Vpp +5V…-5V
2Vpp +5V…-5V
4Vpp +5V…-5V
5Vpp +25V…-25V
10Vpp +25V…-25V
20Vpp +25V…-25V
Input Offset
At the input of the 41-320 there is a 16 bit offset DAC. The input offset facility allows a signal to be captured that
is biased on a DC pedestal, without having to use a less sensitive input range setting than is required for optimum
operation. Depending on the range, the input offset span is +5Volt to –5Volt or +25Volt to – 25Volt ( Table 2.1). When
the input offset is used the negative connector from the differential input is disabled.
Example: To examine a signal (1Vpp) on a 1 Volt DC offset, see Fig. 2.3. The top of the input signal is 1Volt offset +
0.5V signal = 1.5Vpeak input voltage. Without using input offset, you would need to specify a range of 4V (2Vpeak)
to capture the waveform. In this case a large range from the ADC will not be used because of the DC voltage on the
signal. However, with the input offset set to 1Volt, the signal center around 0V and a range of 1V is enough to capture
the signal. This improves the accuracy of the measurement and the dynamic range of any captured information.
50
10k
SMB input
AC / DC
50 / 10k
connect
GND

Section 2 - tecHnicAL DeScRiPtion
Page 2.3
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
Fig. 2.3 - Using the DC offset facility to improve measurement resolution and accuracy
Filters
Each channel has three selectable 3-pole low pass lters. The lters limit the bandwidth of the signal path and are
useful for rejecting out of band noise and signals that may generate alias responses. The selectable lters have
cutoff frequencies of: 6 MHz, 15 MHz, and 30 MHz. The lters can also be bypassed for wideband signals. Fig. 2.4
shows the typical frequency response from the 41-320.
Fig. 2.4 - Typical frequency response
TRIGGERING
The 41-320 starts capturing on receiving a trigger signal. The separate trigger circuits for Channel-A and Channel-B
allows each channel to start on different trigger sources and on different trigger edges or levels. The 41-320 can
trigger on three trigger sources: Digital input trigger, Software trigger and Analog trigger. Fig. 2.5 shows the trigger
capabilities. To prevent triggering during connection or initializing there is a “lock” bit. The 41-320 can be triggered
once the lock bit is set.
Digital Input Triggering
The digital trigger accepts triggers from the front panel trigger and the PXI back plane trigger sources, including PXI
TRIGGER 0 to 5 and the PXI STAR TRIGGER. The front panel trigger input uses normal TTL logic levels, with a
0.5V nominal threshold for a low level and a 2V nominal threshold for a high level.
t
Input signal Captured signal
t
1V
Input offset 1V
0.5V
0
-0.5V
0
1.5V
0.5V
-50
-40
-30
-20
-10
0
10
1 10 100
Frequency (MHz)
)Bd( edutilpmA
No Filter
6MHz Filter
15MHz Filter
30MHZ Filter

Page 2.4
Section 2 - tecHnicAL DeScRiPtion pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
All the trigger inputs, except the software trigger, can handle different trigger signal types. The triggers can be set
for positive or negative levels or positive and negative edges.
For settings see the PD1472_SetTriggerInput command in Section 3.
The level trigger mode the capturing starts when trigger goes active and stops when trigger goes inactive. The
Edge trigger mode has two options, normal or continuous. In normal mode data capture starts at a trigger edge
and stops on the next trigger edge. In continuous mode the measurement runs until stopped by the software. Every
measurement can be stopped with the software by forcing the channel out of “lock mode”. When the module is out
of lock mode the trigger register will be cleared.
Software Triggering
If trigger timing is not a issue, there is a software initiated trigger. By writing the trigger register the signal capture
can be started or stopped.
Fig. 2.5 - 41-320 trigger capabilities
Analog Triggering
In the analog trigger mode the analog input signal starts and stops the signal capture. The trigger signal is extracted
from the zero crossing from the input signal. (ADC code 4000 Hex).
If the analog input voltage is higher than 0 volt the trigger signal is high and if the analog input voltage is lower than
0 the trigger signal is low. The trigger level can be offset by adding an offset voltage with the input offset DAC. With
the level and edge trigger settings it is possible to capture different parts from the analog input signal. In the positive
or negative level trigger mode the signal capture starts when the when the analog input signal higher or lower than
0 volt.
In this mode only the upper parts or the lower parts from the analog signal will be captured. (Fig. 2.6).
In edge trigger mode the capturing starts at a trigger edge and stops on the next trigger edge. This edge can be
negative or positive according to the setting. (Fig. 2.7).
In continuous trigger mode the signal capture starts on a positive or negative edge and runs till the memory stop
address is reached (not in loop mode) or stopped by the user in loop mode. (Fig. 2.8).
Fig. 2.6 - Analog Positive Level Triggering
Trigger
Multiplexer Edge/Level
select
Trigger
PXI trigger 0..5
PXI star trigger
Front trigger
Software trigger
Input level trigger
Digital Triggers
Analog Trigger
t
UU
t
Input signal Captured signal
Trigger start stop start Trigger error
13
2
3
15

Section 2 - tecHnicAL DeScRiPtion
Page 2.5
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
Fig. 2.7 - Analog Positive Edge Triggering
Fig. 2.8 - Analog positive Continuous Edge trigger
Trigger Timing
The external trigger can come from the front panel trigger input or the PXI back plane trigger sources. The external
trigger input uses normal TTL logic levels, with a 0.5V nominal threshold for a low level and a 2V nominal threshold
for a high level. The trigger signal has to be re-timed to the sample clock and needs one sample clock to enter into
the trigger register. The trigger must be high 6ns before the rising edge from the sample clock to start or stop the
measurement (see Fig. 2.9 and Fig. 2.10 ). Since the ADC has a latency of 8 sample clock pulses, the rst sample
that will be saved after triggering is the sample taken 8 sample clocks before triggering. When the measurement is
stopped with the trigger signal or by reaching the stop-address the last sample that will be saved is a sample taken
eight sample clocks before the stop condition (see Fig. 2.9 and Fig. 2.10).
Fig. 2.9 - External Trigger Timing Start
t
UU
Input signal Captured signal
Trigger
t
Trigger error
start stop
Trigger error
1
2
3 1 5
2
t
UU
Input signal Captured signal
Trigger
t
Trigger error
start
1
2
31
2
3
Lock mode
Trigger
Sample Clock
Capture start
Input signal
Captured Data
n
n+1 n+2
n+3
n+4 n+5
n+6
n+7
n+9
n+8
n-1n-2
n-3
n-4
n-5
n-6
n-8 n-7 n
n-1
n-2
1.5ns
6ns

Page 2.6
Section 2 - tecHnicAL DeScRiPtion pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
Fig. 2.10 - External Trigger Timing Stop
CLOCKING
The 41-320 can sample on different clock signals. The module has two internal clock sources, 70MHz and 50MHz
and an external clock source input. To sample on lower clock frequencies it is possible to divide the clock source
to a lower frequency with the clock divider. Each channel has its own clock divider so they can capture at different
frequencies.
If an application require sampling at specic intervals that cannot be achieved by using the internal 70MHz or
50 MHz clock, an external sample clock can be used.
The external clock can be connected to the SMB input or output.
When the front clock connector output is enabled, the sample clock from channel-A is present on this connector.
This clock can be used to synchronize other devices in a measurement system to the 41-320. The front panel clock
in and- output has a 50-Ohm termination.
Fig. 2.11 - Clock Circuit
Lock mode
Trigger
Sample Clock
Capture
Input signal
Captured Data
n+2
n+3 n+4
n+5
n+6 n+7
n+8
n+9
n-1n-2
n-3
n-4
n-5
n-6
n-8 n-7 n
n+1
n
6ns
n-9
Clock
Multiplexer
Clock
Divider
Clock ADC channel A
Front clock in
Internal clock 50MHz
Internal clock 70MHz
Front clock out
Clock ADC channel B
Clock
Divider

Section 2 - tecHnicAL DeScRiPtion
Page 2.7
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Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
Memory
512K
00000 Hex
7FFFF Hex
Start address
End address
Memory
512K
00000 Hex
7FFFF Hex
Start address
End address
Loop mode enableLoop mode disable
30000 Hex 30000 Hex
CALIBRATION
Calibration is a test that compares the values indicated by the 41-320 with a external reference source. The result of
a calibration is used to determine the gain and offset error so the 41-320 can correct the error with the trim DAC’s.
For optimum performance use self-calibration when the digitizer is placed in a new system or if the temperature
changes more than 5°C from the previous calibration.
The maximum recommended amount of time between two calibrations is six months.
The calibration can be done with the software tool 41-320 calibration or with the DLL function PD1472_AutoCalibrate.
The input offset DAC is used as reference voltage source. Before the auto calibration is started the input offset DAC
must be calibrated rst, using a calibrated high-precision voltmeter connected to the negative input.
The 41-320 uses trim DAC’s to calibrate the offset and gain errors of the analog input channels. Once the calibration
process is done, the calibration constant will be stored in EEPROM. These values can be loaded by the software,
and used as needed by the board.
The software tool leads you step for step through the calibration process. For details of the DLL function refer to
Section 4.
Fig. 2.12 - Function of the Loopmode-Bit
ONBOARD MEMORY
The onboard memory is for the storage of the captured data before transfer to the computer. This capture memory
has the size of 512k words, available for each channel. The capture memory of the 41-320 is addressed through
a counter. This counter is active during signal capture and during reading or writing to the memory from the PXI
backplane.
In capture mode the counter starts counting from the start and increments on each sample clock until it reaches
the end address from the memory ( 7FFFF Hex ). At the end of the memory the counter stops, or jumps to address
00000 Hex and counts up again. This selection is made with the DLL function PD1472_SetLoopMode. Setting to “0”
disables the loop mode and setting to “1” enables, see Section 3.
To see if the the channel has reached the end address there is a function called PD1472_GetLoopMode This
function returns a logic “1” if the channel has reached the end address.
The start address should be written the DLL PD1472_SetAddressCounter before the pattern starts. Writing the start
address, loads this value into the counter.
In bus access mode the same mechanism is active except that the clock is now the read or write signal. To write
a memory section the start address should be set rst. The counter is now pointing to the start address and the
content of this address can be read or written. After each read or write the counter increments to the next address
allowing burst read or write actions. Note that the counter will stop or jump to address 00000 Hex when it reaches
the end address, depending PD1472_SetLoopMode setting.
Since the memory may not be read or written to during signal capture, there is a lock bit that should be set to allow
signal capture. The memory is then locked for reading or writing. After setting the lock bit to unlock the memory is
accessible again. If a measurement was running when the memory becomes locked the the signal capture will be
aborted.

Page 2.8
Section 2 - tecHnicAL DeScRiPtion pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
REGISTER ASSIGNMENT
TABLE 2.1 - Register Assignment: Channel A
ADDRESS Operation DATA Description
01 Hex R and W 00000 : 3FFFF Hex Read or write address counter
02 Hex R and W 0000 : FFFF (auto increment) Read or write to memory
04 Hex W 00 : FF Hex Write clock source divider (ADC)
05 Hex R 00 Hex No channel has looped
01 Hex Channel A has looped
02 Hex Channel B has looped
03 Hex Channel A and B looped
Read loop status. Displays if the memory
counter has looped one time.
06 Hex R and W 00 Hex No trigger
01 Hex Trigger channel A
02 Hex Trigger channel B
03 Hex Trigger channel A and B
Write software trigger start
Read current trigger status
07 Hex W 00 Hex Front clock input
01 Hex Internal clock 70MHz
02 Hex Internal clock 50MHz
10 Hex Front clock out enable
Select Clock source. and Clock output
function
08 Hex R and W 01 Hex No lter
02 Hex 6MHz lter
04 Hex 15MHz lter
08 Hex 30MHz lter
Select Filter (Combine with Analog output
select code)
08 Hex R and W 10 Hex range 1 input = 1Vpp (x0.2 = 5Vpp)
20 Hex range 2 input = 2Vpp (x0.2 = 10Vpp)
40 Hex range 3 input = 4Vpp (x0.2 = 20Vpp)
Select Attenuator (Combine code with Filter
select and input offset)
08 Hex R and W 80 Hex Input offset on Input offset on / off (combine with ATT)
09 Hex R and W 01 Hex Connect input A+
02 Hex Connect input A-
04 Hex Input A+ 50 Ohm
08 Hex Input A- 50 Ohm
10 Hex Input A+ to GND
20 Hex Input A- to GND
40 Hex input attenuation x 0.2
80 Hex Both inputs AC coupling
Analog output select
0A Hex W 00 Hex Front trigger
01 Hex PXI trigger 0
02 Hex PXI trigger 1
03 Hex PXI trigger 2
04 Hex PXI trigger 3
05 Hex PXI trigger 4
06 Hex PXI trigger 5
07 Hex PXI STAR trigger
08 Hex Software triggering
09 Hex Analog level Triggering
Select Trigger source
(Combine with select Edge code)
0A Hex W 00 Hex positive level triggering
10 Hex negative level triggering
20 Hex positive edge triggering
30 Hex negative edge triggering
60 Hex positive edge, continuous triggering
70 Hex negative edge, continuous triggering
Select trigger edge
0A Hex W 80 Loop counter Counter loop (0x) or one time (8x)
0B Hex R and W (bit0=Do/Di bit1=CLK bit3=CS) Read Write EEPROM
0C Hex W (bit0=DO bit1=CLK bit3=CS) Write Input offset DAC (16bit)
0D Hex W (bit0=DO bit1=CLK bit3=CS)
07 Hex cal offset channel A
08 Hex cal. gain channel A
Write Callibration offset and gain DAC
(10bit)
0F Hex W 00 Hex Lock off
01 Hex ready for trigger
Lock on or off

Section 2 - tecHnicAL DeScRiPtion
Page 2.9
pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
TABLE 2.2 - Register Assignment: Channel B
ADDRESS Operation DATA Description
81 Hex R and W 00000 : 3FFFF Hex Read or write address counter
82 Hex R and W 0000 : FFFF (auto increment) Read or write to memory
84 Hex W 00 : FF Hex Write clock source divider (ADC)
85 Hex R 00 Hex No channel has looped
01 Hex Channel A has looped
02 Hex Channel B has looped
03 Hex Channel A and B looped
Read loop status. Displays if the memory counter
has looped one time.
86 Hex R and W 00 Hex No trigger
01 Hex Trigger channel A
02 Hex Trigger channel B
03 Hex Trigger channel A and B
Write software trigger start.
Read current trigger status
87 Hex W 00 Hex Front clock input
01 Hex Internal clock 70MHz
02 Hex Internal clock 50MHz
10 Hex Front clock out enable
Select Clock source. and Clock output function.
88 Hex R and W 01 Hex No lter
02 Hex 6MHz lter
04 Hex 15MHz lter
08 Hex 30MHz lter
Select Filter
(Combine with Analog output select code)
88 Hex R and W 10 Hex range 1 input = 1Vpp (x0.2 = 5Vpp)
20 Hex range 2 input = 2Vpp (x0.2 = 10Vpp)
40 Hex range 3 input = 4Vpp (x0.2 = 20Vpp)
Select Attenuator
(Combine code with Filter select and input offset)
88 Hex R and W 80 Hex Input offset on Input offset on / off (combine with ATT)
89 Hex R and W 01 Hex Connect input A+
02 Hex Connect input A-
04 Hex Input A+ 50 Ohm
08 Hex Input A- 50 Ohm
10 Hex Input A+ to GND
20 Hex Input A- to GND
40 Hex input attenuation x 0.2
80 Hex Both inputs AC coupling
Analog output select
8A Hex W 00 Hex Front trigger
01 Hex PXI trigger 0
02 Hex PXI trigger 1
03 Hex PXI trigger 2
04 Hex PXI trigger 3
05 Hex PXI trigger 4
06 Hex PXI trigger 5
07 Hex PXI STAR trigger
08 Hex Software triggering
09 Hex Analog level Triggering
Select Trigger source
(Combine with select Edge code)
8A Hex W 00 Hex positive level triggering
10 Hex negative level triggering
20 Hex positive edge triggering
30 Hex negative edge triggering
60 Hex positive edge, continuous triggering
70 Hex negative edge, continuous triggering
Select trigger edge
8A Hex W 80 Loop counter Counter loop (0x) or one time (8x)
8B Hex R and W (bit0=Do/Di bit1=CLK bit3=CS) Read Write EEPROM
8C Hex W (bit0=DO bit1=CLK bit3=CS) Write Input offset DAC (16bit)
8D Hex W (bit0=DO bit1=CLK bit3=CS)
07 Hex cal offset channel A
08 Hex cal. gain channel A
Write Callibration offset and gain DAC (10bit)
8F Hex W 00 Hex Lock off
01 Hex ready for trigger
Lock on or off

Page 2.10
Section 2 - tecHnicAL DeScRiPtion pickering
Dual 70MSPS PXI WaveforM DIgItIzer MoDule 41-320
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