Pickering PXI 41-610 User manual

pickering
USER MANUAL
DUAL 100 MS/s Arbitrary Waveform Generator
(MODEL No. 41-610)
WWW.PICKERINGTEST.COM
Pickering Interfaces Ltd.
Stephenson Road
Clacton-on-Sea
CO15 4NL
United Kingdom
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces Inc.
2900 Northwest Vine Street
Grants Pass
Oregon 97526
USA
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces GmbH
Buchenstrasse 15
D-77880
Sasbach
Germany
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces AB
Karl Nordströmsväg 31
432 53
Varberg
Sweden
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces, Inc.
Eastern Regional Office
12 Alfred Street Suite 300-3
Woburn, MA 01801
USA
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Issue 1.1 August 2009

© COPYRIGHT (2003) PICKERING INTERFACES. ALL RIGHTS RESERVED.
No part of this publication may be reproduced, transmitted, transcribed, translated or stored in any form, or
by any means without the written permission of Pickering Interfaces.
Technical details contained within this publication are subject to change without notice.
Page ii

TECHNICAL SUPPORT
For Technical Support please contact Pickering Interfaces either by phone, fax, the website or via e-mail.
WARRANTY
All products manufactured by Pickering Interfaces are warranted against defective materials and workmanship for
a period of two years from the date of delivery to the original purchaser. Any product found to be defective within
this period will, at the discretion of Pickering Interfaces be repaired or replaced.
Warranty is on a return to factory basis, however, for most systems, the module may be replaced on a module
exchange basis. A module will be delivered to the user and the faulty part returned to Pickering Interfaces on
receipt.
Products serviced and repaired outside of the warranty period are warranted for ninety days.
Extended warranty and service are available. Please contact Pickering Interfaces by phone, fax, the website or via
e-mail.
ENVIRONMENTAL POLICY
Pickering Interfaces operates under an environmental management system similar to ISO 14001.
Pickering Interfaces strives to fulfill all relevant environmental laws and regulations and reduce wastes and releases
to the environment. Pickering Interfaces aims to design and operate products in a way that protects the environment
and the health and safety of its employees, customers and the public. Pickering Interfaces endeavours to develop
and manufacture products that can be produced, distributed, used and recycled, or disposed of, in a safe and
environmentally friendly manner.
Observe the Electrical Hazard Warning detailed in Section 7.
Observe the Electrostatic Sensitive Device Caution detailed in Section 7.
Page iii

Page iv
REVISION HISTORY
Rev Date Section Description
- 28 Jul 2003 preliminary release
1.1 17 Nov 2003 All Updated hardware (1.2) & software (1.0) sections
1.2 4-Mar-2004 1 & 6 Updated SW installation in section (1)
Added Alignment instructions in section (6)
1.3 26-May-2004 Updated specifications adding new output version 41-610-002

Copyright Statement ......................................................... ii
Technical Support and Warranty ...................................... iii
Revision History ................................................................. vi
Section 1
Introduction & Installation ................................................ 1.1
Description .................................................................... 1.1
General ........................................................................... 1.2
Digital .............................................................................. 1.2
Analog ............................................................................ 1.2
PXI/cPCI Interface ......................................................... 1.3
Front Panel .................................................................... 1.4
SW Installation Procedure ........................................... 1.5
41-610 Driver Package ................................................. 1.5
Contact Information ..................................................... 1.7
Product Order Codes .................................................... 1.7
Section 2
Device Operation ............................................................... 2.1
Memory ........................................................................... 2.1
Trigger Processing ....................................................... 2.2
Clock Select ................................................................... 2.3
Filter Selection ............................................................... 2.3
Output Stage .................................................................. 2.4
Bias DAC ....................................................................... 2.5
Attenuator ...................................................................... 2.5
Offset DAC .................................................................... 2.6
Memory Segmentation .................................................. 2.6
Serial EEPROM ............................................................. 2.7
Register Summary Channel A ...................................... 2.8
Register Summary Channel B ...................................... 2.10
Section 3
PXI Interface & Programming ........................................... 3.1
PXI Hardware Interface ................................................. 3.1
DLL functions ................................................................ 3.1
Close( ci ) ....................................................................... 3.1
CONTENTS
Page v

Section 3 continued
PXI Interface & Programming ........................................... 3.1
Close(ci) ........................................................................ 3.1
ConnectCard( ci , cc ) ................................................... 3.2
GetActiveChannel( ci , channel ) ................................. 3.2
GetAddressCounter( ci ,addresscounter)................... 3.2
GetAttenuator( ci , attenuation ) .................................. 3.2
GetCardAddress( ci , address ) ................................... 3.3
GetCardConnection( ci , cc ) ........................................ 3.3
GetCardList( count, buslist, devicelist ) ..................... 3.3
GetCardNumber( ci , card ) .......................................... 3.3
GetDCOffsetVoltage( ci , voltage ) ............................... 3.4
GetErrorMessage( code, message ) ............................ 3.4
GetNumberOfCards( cards ) ........................................ 3.4
GetOffsetCalDacCode( ci , code ) ................................ 3.4
GetOutputOffsetCalDacCode( ci, dac,code ) .............. 3.4
GetRevision( revision ) ................................................. 3.5
GetTriggerStatus( ci , triggerstatus ) ........................... 3.5
GetStartAddress( ci , startaddress ) ........................... 3.5
GetStopAddress( ci , stopaddress) ............................. 3.5
Init( bus , device , ci ) .................................................... 3.6
InitCard( card , ci ) ......................................................... 3.6
LoadArbitraryWaveform
( ci, startaddress, length, waveform ) ......................... 3.6
Read( ci , offset , data ) ................................................. 3.7
ReadEeprom( ci , eeaddress , data ) ........................... 3.7
ReadId( ci , id ) ............................................................... 3.7
ReadRam( ci, data ) ....................................................... 3.7
ReadRamBuffer( ci , length , buf32 ) ........................... 3.8
ResetToStartAddress( ci ) ............................................ 3.8
SetActiveChannel( ci , channel ) ................................. 3.8
SetAttenuator( ci , attenuation ) ................................... 3.8
SetClockDivider( ci , clockdivider ) ............................. 3.9
SetClockSource( ci , clocksource ) ............................. 3.9
SetDacCode( ci , code ) ................................................ 3.9
SetDCOffsetDacCode( ci , code ) ................................. 3.9
SetDCOffsetVoltage( ci , voltage ) ............................... 3.10
SetDCOffsetLimitVoltages( ci , posvolt , negvolt ) ..... 3.10
SetFilter( ci , filter ) ........................................................ 3.10
SetLockMode( ci , lock ) ............................................... 3.11
CONTENTS
Page vi

Section 3 continued
PXI Interface & Programming ........................................... 3.1
SetOffsetCalDacCode( ci, code ) ................................. 3.11
SetOutputOffsetCalDaqCode( ci, dac,code ) .............. 3.11
SetRangeDacCode( ci , code ) ..................................... 3.11
SetRangeLimitVoltages( ci , maxvolt , minvolt ) ........ 3.12
SetSoftwareTriggerStatus( ci , triggerstatus ) ............ 3.12
SetStartAddress( ci , startaddress ) ............................ 3.12
SetStopAddress( ci , stopaddress ) ............................ 3.13
SetTriggerMode( ci , triggersource , triggermode ) ... 3.13
SignalAdd
( ci , type , amplitude , periods , phase ,symmetry ) .. 3.14
SignalClear( ci ) ............................................................. 3.14
SignalToRam( ci ) .......................................................... 3.14
StoreCalibrationData( ci ) ............................................. 3.15
Write( ci , offset , data ) ................................................. 3.15
WriteEeprom( ci , eeaddress , data ) ........................... 3.16
WriteId( ci , id ) .............................................................. 3.16
WriteRam( ci , data ) ..................................................... 3.16
WriteRamBuffer( ci , length , buffer ) .......................... 3.16
Status codes .................................................................. 3.17
VISA Error Codes .......................................................... 3.17
Section 4
Applications ....................................................................... 4.1
Programming example ................................................. 4.1
Section 5
Demo Software Guide ....................................................... 5.1
AWG Demo Description ............................................... 5.1
AWG Demo Controls and Displays ............................. 5.1
AWG Demo Files and Utilities ..................................... 5.3
Function Generator Demo ........................................... 5.3
Fuction Generator Controls and Displays ................. 5.4
CONTENTS
Page vii

Page viii
Section 6
Alignment Procedure ......................................................... 6.1
Start the Alignment Utility ............................................ 6.1
Select the card .............................................................. 6.1
Select channel(s) .......................................................... 6.1
Connect Voltmeter ........................................................ 6.2
Offset balance calibration ............................................ 6.2
Offset Calibration at Positive Output .......................... 6.3
DC Offset min. and max. voltages ............................... 6.3
Gain min. and max. voltages ....................................... 6.3
Offset Calibration at Negative Output ......................... 6.3
Finish .............................................................................. 6.3
Section 7
Warnings and Cautions .................................................... 7.1
CONTENTS

SECTION 1 - INTRODUCTION & INSTALLATION
Page 1.1
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
SECTION 1 - INTRODUCTION & INSTALLATION
Introduction
The 41-610 is a dual-channel PXI-based Arbitrary Waveform Generator.(AWG or ARB) using a 14-bit high speed
digital to analog converter. Figure 1-1 shows the functional block diagram from the 41-610.
Channel-B is an exact copy of channel-A except for the addition in the signal path to Channel-A that permits the
two channels to be combined (B channel inverted) and routed to the Channel A output connector.
On the left of the diagram is the PXI interface from the chassis backplane.
The core of the ARB contains an address counter and a 14bit x 512k RAM memory, the memory output being
supplied to a 14 bit DAC system.
When the 41-610 is triggered, the memory contents are read out, starting from a user defined start address.
While the ARB is running an internal or external clock increments the memory counter. When the counter reaches
the value of the stop address it jumps back to the start address to allow the generation of continues analog pat-
terns.
If desired the generated analog signal can be filtered to remove broadband signals when operated at lower fre-
quencies.
The output level is adjusted by two controls, an attenuator and Dc reference voltage. The attenuator has 7 steps
of 3dB each. Fine control is managed by the DAC programmable reference voltage that allows a proportional
output level variation of 3 dB. The reference voltage to the DAC can be adjusted over a larger range, but may
impact the performance of the converter. The 7 of 3 dB steps and and the 3 dB adjustment of the reference volt-
age provides a total voltage range of 24 dB. The output voltage range can be reduced further using the reference
voltage.
A DC-offset voltage can be added to the signal. The outputs for both channels use differential 50 Ohm amplifiers,
the differential signals appearing on two outputs for each channel.
Figure 1-1 41-610 Functional Block Diagram

Page 1.2
SECTION 1 - INTRODUCTION & INSTALLATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
ARB Characteristics
Resolution 14 bits on both channels
Internal clock sample rate 100 Ms/s, 70 Ms/s, 10 Ms/s
(PXI CLK10) When set to
internal clock the clock is
provided on the front panel
at TTL levels
Internal clock accuracy 100 ppm
External clock sample rate DC to 100 Ms/s
Clock division ratio Settable from 1 to 256
Memory Depth 512 k per for each output
ARB Trigger
Supported trigger sources Front panel source (TTL)
PXI Trigger 0 to 5.
Star Trigger
Software trigger
ARB Output
Output Differential output for both
channels
Output Impedance 50 ohms
Output Voltage
41-610-001 315 mV to 5 Vpp into an
open circuit
41-610-002 126mV to 2 Vpp into an
open circuit
Output level can be further
reduced with reduced
SFDR
DC Output Offset ±2.5 V
Combined output A channel – B channel on a
differential output
(A connectors used)
Output filters Selectable as none, 6 MHz,
15 MHz or 30 MHz
(3 pole Butterworth)
Output range control Range of 24 dB in 3 dB
steps (7 off) with fine level
control between steps.
Range can be extended
use fine level control
(performance not specified)
Output accuracy (DC) 0.1% of range ±0.5 mV
(at DC)
Frequency response
envelope is less than
±0.5 dB relative to 30MHz
from DC to 50MHz
Output Spectral Purity For 100 Ms/s sample rate,
2 V pp output into 50 ohms
SFDR (with harmonics)
1MHz sine wave -78 dB
10MHz sine wave -64dB, typically -70 dB
Channel crosstalk: better than >80 dB @ 10MHz
Waveform Generation
Internal Sine, pulsed
(adjustable duty cycle),
triangle
(adjustable symmetry)
External Files created using external
tools can be imported
Connectors SMB front panel connectors
Physical Parameters
Physical Characteristics One slot, 3UPXI
PCI Interface 33 MHz
32-bit Address
16-bit Data
PXI Power Supply
+5 V +3.3 V +12 V -12 V
0.3 A 0.38 A 0.24 A 0.24 A
Deviation from a sinx/x
with no filter selected

SECTION 1 - INTRODUCTION & INSTALLATION
Page 1.3
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
PXI Support
Supplied with the 41-610 is a PC software package that consists of a windows driver, Labview driver and a demo
program.
Details on how to use this software are given in Section 5 - Demo Software Guide.
Front Panel
A diagram of the 41-610 front panel is shown in Figure 1-2. On the front panel, there are six SMB coaxial connec-
tors . Four connectors are used for the differential output from channel A and B. The two other connectors are for
the trigger input and the clock. The function of these connectors is described below.
OUT A+ and OUT A-
This is the output from channel A. In single ended mode the connector A+ is used,
in differential mode the output signal is present between A+ and A-. The output impedance is always 50Ω.
OUT B+ and OUT B-
This is the output from channel B. In single ended mode the connector B+ is used,
in differential mode the output signal is present between B+ and B-. The output impedance is always 50Ω.
CLK in/out
This connector is bi-directional. If the clock source selector is set to FRONT this
connector is an input for the sample clock, in all other clock source modes this connector is an output for the
sample clock. This signal can be used to clock or synchronize other modules. The input impedance of this input is
50Ω.
TRIG in
If the trigger selector is set to FRONT this input accepts signals that starts generation of output waveforms
The trigger input can be set to level- or negative level trigger and edge- or negative edge trigger.
Trigger level for this input is TTL.
Figure 1-2

Page 1.4
SECTION 1 - INTRODUCTION & INSTALLATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
INSTALLATION PROCEDURE
The 41-610 is a 100MHz dual channel Arbitrary Waveform Generator. For software development and integration in
a PXI system, the card is provided with a software driver (DLL) and a LabVIEW® demo program.
The main part of the 41-610 driver consist of a Windows dynamic link library, the pg14102.DLL
For Labview users the package includes a Labview library with all the driver function viʼs.
Installation
The software should be installed before the 41-610 is placed in the system. Place the installation CD in the CD-
ROM. If the installation program does not start automatically, run the program install.exe (placed in the root of the
CD-ROM).
Highlight the perfered language then click <Next>
The installation wizard will guide you through the installation process, click <Next>

SECTION 1 - INTRODUCTION & INSTALLATION
Page 1.5
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
Please read the license agreement and if you agree to the terms and conditions tic the Yes box, then click <Next>
Additional software may be required to use the 41-610 hardware, please read the requirements carefully and
install the necessary software as required. Click <Next>

Page 1.6
SECTION 1 - INTRODUCTION & INSTALLATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
Please select a destination folder, then click <Next>
The minimal installation will install the 41-610 utility software and alignment software. The Full installation adds the
following components:
• LabView Demo program;
• LabView library (driver);
• Places files in the VXIpnp\[OS] directory (default C:\VXIpnp\[OS]). [OS] indicates the operating system.

SECTION 1 - INTRODUCTION & INSTALLATION
Page 1.7
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
Select a location for the installation wizard to place the program shortcuts. Click <Next>
Click <Next> to proceed with the installation. The PXI Kernel Driver cannot be installed on Windows95 or Win-
dows NT. This selection will be disabled if one of these operating systems is detected.

Page 1.8
SECTION 1 - INTRODUCTION & INSTALLATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
After installation shutdown the computer and place the 41-610 in the system. After turning on the computer the
operating system should automatically detect the new hardware and install the low level driver.
PICKERING INTERFACES CONTACT INFORMATION
Pickering Interfaces can provide detailed technical information and assistance for the 41-610. For your nearest
Pickering Interfaces point of contact consult our web site at http://www.pickeringtest.com.
PRODUCT ORDER CODES
41-610-001 Dual 100 MS/s 14 bit 50Ω Impedance Standard O/P ARB
41-610-002 Dual 100 MS/s 14-bit 50Ω Impedance Reduced O/P ARB

SECTION 2 - DEVICE OPERATION
Page 2.1
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
SECTION 2 - DEVICE OPERATION
Memory operation
The ARB memory of the 41-610 is addressed through a counter system. This counter system is used during pat-
tern generation and during reading or writing to the memory via the PXI bus.
In Pattern generation mode the counter starts counting from the start (see table below) and increments on each
sample clock until it reaches the stop address. Then it jumps back to the start address and repeats the same
memory segment. The start address and stop address values should be written to the appropriate registers before
the pattern generation starts. When writing the start address, this value is also loaded into the counter.
In Bus Access mode the same methodilogy is used except that the clock is now the read or write signal.
To write to memory the start address and stop address should be set first. The counter initially points to the start
address and the content of this address can be read or written via register 04 Hex (84 Hex).
After each read or write the counter increments to the next address allowing read or write actions. Note that the
counter will jump back to the start address when it reaches the stop address.
Since the memory may not be read or written during pattern generation, there is a Lock bit that should be set to
allow pattern generation. The memory is then prevented from being read or written to over the PXI bus. To enable
reading or writing again the lock bit should be set to unlock. Any pattern that was still running at that moment will
be aborted.
Figure 2-1
Register assignment:
ADDRESS
Channel A (B)
Operation
(R/W ) Data Description
01 (81) Hex W 00000 : 3FFFF Hex Write stop address
02 (82) Hex W 00000 : 3FFFF Hex Write start address
04 (84) Hex R and W 0000 : FFFF Hex (auto incre-
ment) Read or write to memory
05 (85) Hex R 00000 : 3FFFF Hex Read counter

Page 2.2
SECTION 2 - DEVICE OPERATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
0F (8F) Hex W 00 Hex Unlock
01 Hex Lock, ready for trigger
Lock / Unlock (Measurement
mode /
Memory access mode)
Trigger processing
The 41-610 starts generating a signal after being triggered.
The separate trigger circuits for Channel-A and Channel-B allows each channel to be started by different sources
and on different edges.
The 41-610 accepts triggers from the PXI back plane trigger sources including PXI_TRG[0:5] and PXI_STAR. In
addition, the 41-610 allows selection of the front panel trigger input or a software initiated trigger.
The front panel trigger input uses normal TTL logic levels, with a 0.5V nominal threshold for a low level and a 2V
nominal threshold for a high level. The 41-610 can handle positive, negative, edge and level trigger signals, see
the (SELECT TRIGGER EDGE) command.
In Level trigger mode the pattern generator starts when Trigger goes active and stops when trigger goes inactive.
In edge trigger mode the pattern generator starts at a trigger edge and either stops on the next trigger edge or
runs continuously until stopped by the software. Figure 2-2 shows a diagram of the 41-610 trigger processing.
Figure 2-2
Register assignment:
ADDRESS
Channel A (B)
Opera-
tion
(R/W )
Data Description
0C (8C) HEX W
x0 Hex FRONT PANEL TRIG
x1 Hex PXI TRIG 0
x2 Hex PXI TRIG 1
x3 Hex PXI TRIG 2
x4 Hex PXI TRIG 3
x5 Hex PXI TRIG 4
x6 Hex PXI TRIG 5
x7 Hex PXI STAR
x8 Hex SOFTWARE TRIG
Select Trigger source
0C (8C) HEX W
0x Hex positive level
1x Hex negative level
2x Hex positive edge, toggle on/off
3x Hex negative edge, toggle on/
off
6x Hex positive edge, continuous
7x Hex negative edge, continuous
Select Edge

SECTION 2 - DEVICE OPERATION
Page 2.3
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
ADDRESS
Channel A (B)
Opera-
tion
(R/W )
Data Description
07 (87) Hex R and W
00 Hex No trigger
01 Hex Software trigger channel A
02 Hex Software trigger channel B
03 Hex Software trigger channel
A & B
Write = software trigger
start.
Read = hardware and soft-
ware trigger status.
Clock select
After triggering the memory counter runs on an internal or external clock signal. The external clock can be the
front panel clock or the 10 MHz PXI clock. The two internal clock sources have frequencies of 100MHz and
70MHz derived by from crystal oscillators.
To allow operation at lower clock frequencies, clock source frequency can be divided by an onboard divider. The
division ratio is set by an 8 bit number to provide division by factors of 1 to 256.
Each channel can be set to a different clock source and a different divider ratio.
If the front panel clock input is not used by one of the two channels, the sample clock from Channel-A is provided
on this connector.
The front panel clock input has an input impedance of 50 Ohm.
Figure 2-4
Register assignment:
ADDRESS
Channel A (B)
Operation
(R/W ) Data Description
08 (88) HEX W
00 Hex FRONT PANEL CLK
01 Hex INT CLK 1 (100MHz)
02 Hex INT CLK 2 (70MHz)
03 Hex PXI 10MHz CLK
Select Clock source
06 (86) HEX W 00 : FF HEX Write clock divider
Filter select
The 41-610 has a bank of selectable 3-pole low pass filters for each channel. The filters improve the reconstruc-
tion of the analog output signal when lower output frequencies are required by restricting the bandwidth of any
quantisation noise or spurious signal levels.
The cutoff frequencies of the filters are 6 MHz, 15 MHz, and 30 MHz. The filters can also be bypassed for repro-
duction of wider band signals. The filters can be independently set for each channel.

Page 2.4
SECTION 2 - DEVICE OPERATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
Figure 2-5
Register assignment:
ADDRESS
Channel A (B)
Opera-
tion
(R/W )
Data Description
0A (8A) HEX R and W
01 Hex No filter
02 Hex 6MHz filter
04 Hex 15MHz filter
08 Hex 30MHz filter
Select Filter DAC A
Output stage
Both channels have two different connect modes, single ended and differential outputs.
If the analog output is turned off, the internal circuit is disconnected from the output by a mechanical switch.
The output includes a series 50Ω 0.1% tolerance resistor to define the source impedance.
It is also possible to add both channels together. In this mode the B channel is inverted.
If the signal from DAC B is added to Channel A, the signal from DAC B is still present on channel B.
Figure 2-6
Register assignment:
ADDRESS
Channel A (B)
Operation
(R/W ) Data (*) Description