Pickering PXI 41-610 User manual

pickering
USER MANUAL
DUAL 100 MS/s Arbitrary Waveform Generator
(MODEL No. 41-610)
WWW.PICKERINGTEST.COM
Pickering Interfaces Ltd.
Stephenson Road
Clacton-on-Sea
CO15 4NL
United Kingdom
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces Inc.
2900 Northwest Vine Street
Grants Pass
Oregon 97526
USA
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces GmbH
Buchenstrasse 15
D-77880
Sasbach
Germany
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces AB
Karl Nordströmsväg 31
432 53
Varberg
Sweden
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Pickering Interfaces, Inc.
Eastern Regional Office
12 Alfred Street Suite 300-3
Woburn, MA 01801
USA
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Issue 1.1 August 2009

© COPYRIGHT (2003) PICKERING INTERFACES. ALL RIGHTS RESERVED.
No part of this publication may be reproduced, transmitted, transcribed, translated or stored in any form, or
by any means without the written permission of Pickering Interfaces.
Technical details contained within this publication are subject to change without notice.
Page ii

TECHNICAL SUPPORT
For Technical Support please contact Pickering Interfaces either by phone, fax, the website or via e-mail.
WARRANTY
All products manufactured by Pickering Interfaces are warranted against defective materials and workmanship for
a period of two years from the date of delivery to the original purchaser. Any product found to be defective within
this period will, at the discretion of Pickering Interfaces be repaired or replaced.
Warranty is on a return to factory basis, however, for most systems, the module may be replaced on a module
exchange basis. A module will be delivered to the user and the faulty part returned to Pickering Interfaces on
receipt.
Products serviced and repaired outside of the warranty period are warranted for ninety days.
Extended warranty and service are available. Please contact Pickering Interfaces by phone, fax, the website or via
e-mail.
ENVIRONMENTAL POLICY
Pickering Interfaces operates under an environmental management system similar to ISO 14001.
Pickering Interfaces strives to fulfill all relevant environmental laws and regulations and reduce wastes and releases
to the environment. Pickering Interfaces aims to design and operate products in a way that protects the environment
and the health and safety of its employees, customers and the public. Pickering Interfaces endeavours to develop
and manufacture products that can be produced, distributed, used and recycled, or disposed of, in a safe and
environmentally friendly manner.
Observe the Electrical Hazard Warning detailed in Section 7.
Observe the Electrostatic Sensitive Device Caution detailed in Section 7.
Page iii

Page iv
REVISION HISTORY
Rev Date Section Description
- 28 Jul 2003 preliminary release
1.1 17 Nov 2003 All Updated hardware (1.2) & software (1.0) sections
1.2 4-Mar-2004 1 & 6 Updated SW installation in section (1)
Added Alignment instructions in section (6)
1.3 26-May-2004 Updated specifications adding new output version 41-610-002

Copyright Statement ......................................................... ii
Technical Support and Warranty ...................................... iii
Revision History ................................................................. vi
Section 1
Introduction & Installation ................................................ 1.1
Description .................................................................... 1.1
General ........................................................................... 1.2
Digital .............................................................................. 1.2
Analog ............................................................................ 1.2
PXI/cPCI Interface ......................................................... 1.3
Front Panel .................................................................... 1.4
SW Installation Procedure ........................................... 1.5
41-610 Driver Package ................................................. 1.5
Contact Information ..................................................... 1.7
Product Order Codes .................................................... 1.7
Section 2
Device Operation ............................................................... 2.1
Memory ........................................................................... 2.1
Trigger Processing ....................................................... 2.2
Clock Select ................................................................... 2.3
Filter Selection ............................................................... 2.3
Output Stage .................................................................. 2.4
Bias DAC ....................................................................... 2.5
Attenuator ...................................................................... 2.5
Offset DAC .................................................................... 2.6
Memory Segmentation .................................................. 2.6
Serial EEPROM ............................................................. 2.7
Register Summary Channel A ...................................... 2.8
Register Summary Channel B ...................................... 2.10
Section 3
PXI Interface & Programming ........................................... 3.1
PXI Hardware Interface ................................................. 3.1
DLL functions ................................................................ 3.1
Close( ci ) ....................................................................... 3.1
CONTENTS
Page v

Section 3 continued
PXI Interface & Programming ........................................... 3.1
Close(ci) ........................................................................ 3.1
ConnectCard( ci , cc ) ................................................... 3.2
GetActiveChannel( ci , channel ) ................................. 3.2
GetAddressCounter( ci ,addresscounter)................... 3.2
GetAttenuator( ci , attenuation ) .................................. 3.2
GetCardAddress( ci , address ) ................................... 3.3
GetCardConnection( ci , cc ) ........................................ 3.3
GetCardList( count, buslist, devicelist ) ..................... 3.3
GetCardNumber( ci , card ) .......................................... 3.3
GetDCOffsetVoltage( ci , voltage ) ............................... 3.4
GetErrorMessage( code, message ) ............................ 3.4
GetNumberOfCards( cards ) ........................................ 3.4
GetOffsetCalDacCode( ci , code ) ................................ 3.4
GetOutputOffsetCalDacCode( ci, dac,code ) .............. 3.4
GetRevision( revision ) ................................................. 3.5
GetTriggerStatus( ci , triggerstatus ) ........................... 3.5
GetStartAddress( ci , startaddress ) ........................... 3.5
GetStopAddress( ci , stopaddress) ............................. 3.5
Init( bus , device , ci ) .................................................... 3.6
InitCard( card , ci ) ......................................................... 3.6
LoadArbitraryWaveform
( ci, startaddress, length, waveform ) ......................... 3.6
Read( ci , offset , data ) ................................................. 3.7
ReadEeprom( ci , eeaddress , data ) ........................... 3.7
ReadId( ci , id ) ............................................................... 3.7
ReadRam( ci, data ) ....................................................... 3.7
ReadRamBuffer( ci , length , buf32 ) ........................... 3.8
ResetToStartAddress( ci ) ............................................ 3.8
SetActiveChannel( ci , channel ) ................................. 3.8
SetAttenuator( ci , attenuation ) ................................... 3.8
SetClockDivider( ci , clockdivider ) ............................. 3.9
SetClockSource( ci , clocksource ) ............................. 3.9
SetDacCode( ci , code ) ................................................ 3.9
SetDCOffsetDacCode( ci , code ) ................................. 3.9
SetDCOffsetVoltage( ci , voltage ) ............................... 3.10
SetDCOffsetLimitVoltages( ci , posvolt , negvolt ) ..... 3.10
SetFilter( ci , filter ) ........................................................ 3.10
SetLockMode( ci , lock ) ............................................... 3.11
CONTENTS
Page vi

Section 3 continued
PXI Interface & Programming ........................................... 3.1
SetOffsetCalDacCode( ci, code ) ................................. 3.11
SetOutputOffsetCalDaqCode( ci, dac,code ) .............. 3.11
SetRangeDacCode( ci , code ) ..................................... 3.11
SetRangeLimitVoltages( ci , maxvolt , minvolt ) ........ 3.12
SetSoftwareTriggerStatus( ci , triggerstatus ) ............ 3.12
SetStartAddress( ci , startaddress ) ............................ 3.12
SetStopAddress( ci , stopaddress ) ............................ 3.13
SetTriggerMode( ci , triggersource , triggermode ) ... 3.13
SignalAdd
( ci , type , amplitude , periods , phase ,symmetry ) .. 3.14
SignalClear( ci ) ............................................................. 3.14
SignalToRam( ci ) .......................................................... 3.14
StoreCalibrationData( ci ) ............................................. 3.15
Write( ci , offset , data ) ................................................. 3.15
WriteEeprom( ci , eeaddress , data ) ........................... 3.16
WriteId( ci , id ) .............................................................. 3.16
WriteRam( ci , data ) ..................................................... 3.16
WriteRamBuffer( ci , length , buffer ) .......................... 3.16
Status codes .................................................................. 3.17
VISA Error Codes .......................................................... 3.17
Section 4
Applications ....................................................................... 4.1
Programming example ................................................. 4.1
Section 5
Demo Software Guide ....................................................... 5.1
AWG Demo Description ............................................... 5.1
AWG Demo Controls and Displays ............................. 5.1
AWG Demo Files and Utilities ..................................... 5.3
Function Generator Demo ........................................... 5.3
Fuction Generator Controls and Displays ................. 5.4
CONTENTS
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Page viii
Section 6
Alignment Procedure ......................................................... 6.1
Start the Alignment Utility ............................................ 6.1
Select the card .............................................................. 6.1
Select channel(s) .......................................................... 6.1
Connect Voltmeter ........................................................ 6.2
Offset balance calibration ............................................ 6.2
Offset Calibration at Positive Output .......................... 6.3
DC Offset min. and max. voltages ............................... 6.3
Gain min. and max. voltages ....................................... 6.3
Offset Calibration at Negative Output ......................... 6.3
Finish .............................................................................. 6.3
Section 7
Warnings and Cautions .................................................... 7.1
CONTENTS

SECTION 1 - INTRODUCTION & INSTALLATION
Page 1.1
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
SECTION 1 - INTRODUCTION & INSTALLATION
Introduction
The 41-610 is a dual-channel PXI-based Arbitrary Waveform Generator.(AWG or ARB) using a 14-bit high speed
digital to analog converter. Figure 1-1 shows the functional block diagram from the 41-610.
Channel-B is an exact copy of channel-A except for the addition in the signal path to Channel-A that permits the
two channels to be combined (B channel inverted) and routed to the Channel A output connector.
On the left of the diagram is the PXI interface from the chassis backplane.
The core of the ARB contains an address counter and a 14bit x 512k RAM memory, the memory output being
supplied to a 14 bit DAC system.
When the 41-610 is triggered, the memory contents are read out, starting from a user defined start address.
While the ARB is running an internal or external clock increments the memory counter. When the counter reaches
the value of the stop address it jumps back to the start address to allow the generation of continues analog pat-
terns.
If desired the generated analog signal can be filtered to remove broadband signals when operated at lower fre-
quencies.
The output level is adjusted by two controls, an attenuator and Dc reference voltage. The attenuator has 7 steps
of 3dB each. Fine control is managed by the DAC programmable reference voltage that allows a proportional
output level variation of 3 dB. The reference voltage to the DAC can be adjusted over a larger range, but may
impact the performance of the converter. The 7 of 3 dB steps and and the 3 dB adjustment of the reference volt-
age provides a total voltage range of 24 dB. The output voltage range can be reduced further using the reference
voltage.
A DC-offset voltage can be added to the signal. The outputs for both channels use differential 50 Ohm amplifiers,
the differential signals appearing on two outputs for each channel.
Figure 1-1 41-610 Functional Block Diagram

Page 1.2
SECTION 1 - INTRODUCTION & INSTALLATION
DUAL 100MSPS ARBITRARY WAVEFORM GENERATOR CARD
pickering
ARB Characteristics
Resolution 14 bits on both channels
Internal clock sample rate 100 Ms/s, 70 Ms/s, 10 Ms/s
(PXI CLK10) When set to
internal clock the clock is
provided on the front panel
at TTL levels
Internal clock accuracy 100 ppm
External clock sample rate DC to 100 Ms/s
Clock division ratio Settable from 1 to 256
Memory Depth 512 k per for each output
ARB Trigger
Supported trigger sources Front panel source (TTL)
PXI Trigger 0 to 5.
Star Trigger
Software trigger
ARB Output
Output Differential output for both
channels
Output Impedance 50 ohms
Output Voltage
41-610-001 315 mV to 5 Vpp into an
open circuit
41-610-002 126mV to 2 Vpp into an
open circuit
Output level can be further
reduced with reduced
SFDR
DC Output Offset ±2.5 V
Combined output A channel – B channel on a
differential output
(A connectors used)
Output filters Selectable as none, 6 MHz,
15 MHz or 30 MHz
(3 pole Butterworth)
Output range control Range of 24 dB in 3 dB
steps (7 off) with fine level
control between steps.
Range can be extended
use fine level control
(performance not specified)
Output accuracy (DC) 0.1% of range ±0.5 mV
(at DC)
Frequency response
envelope is less than
±0.5 dB relative to 30MHz
from DC to 50MHz
Output Spectral Purity For 100 Ms/s sample rate,
2 V pp output into 50 ohms
SFDR (with harmonics)
1MHz sine wave -78 dB
10MHz sine wave -64dB, typically -70 dB
Channel crosstalk: better than >80 dB @ 10MHz
Waveform Generation
Internal Sine, pulsed
(adjustable duty cycle),
triangle
(adjustable symmetry)
External Files created using external
tools can be imported
Connectors SMB front panel connectors
Physical Parameters
Physical Characteristics One slot, 3UPXI
PCI Interface 33 MHz
32-bit Address
16-bit Data
PXI Power Supply
+5 V +3.3 V +12 V -12 V
0.3 A 0.38 A 0.24 A 0.24 A
Deviation from a sinx/x
with no filter selected