Pico Computing E-102 Quick user guide
E-102
Hardware Reference Manual
www.picocomputing.com Pico Computing
E-102 Hardware Reference Manual 150 Nickerson treet. uite 311
(206) 283-2178 eattle, WA 98109
Table of Contents
Table of Contents ......................................................................................................................................................................................... 2
Theory of Operation .................................................................................................................................................................................... 3
Specifications ............................................................................................................................................................................................... 3
XC7Z020-CLG4 4C Programmable SoC (Engineering Silicon) ........................................................................................................ 3
DDR3 DRAM ...................................................................................................................................................................................... 3
USB OTG ............................................................................................................................................................................................. 3
USB UART .......................................................................................................................................................................................... 3
HDMI Output ....................................................................................................................................................................................... 3
MicroSD Card ...................................................................................................................................................................................... 3
33 Zynq MIO GPIO ............................................................................................................................................................................. 4
150 Zynq SelectIO GPIO .................................................................................................................................................................... 4
DONE, INIT, and GPIO status LEDs ................................................................................................................................................. 4
Mechanical and Environmental .......................................................................................................................................................... 4
System Monitoring .............................................................................................................................................................................. 4
Included with E-102 ............................................................................................................................................................................ 4
Board Overview ........................................................................................................................................................................................... 5
E-102 Block Diagram .................................................................................................................................................................................. 6
Mechanical ................................................................................................................................................................................................... 7
Status LED Description ...............................................................................................................................................................................
Clock Circuitry ............................................................................................................................................................................................. 9
PS_CLK ............................................................................................................................................................................................... 9
SYS_CLK ............................................................................................................................................................................................ 9
GPIO Header Pin Locations ....................................................................................................................................................................... 10
Power ........................................................................................................................................................................................................ 32
GPIO connectors (J5 & J ) ................................................................................................................................................................ 32
USB-OTG Receptacle (J7) ................................................................................................................................................................ 32
USB-UART Receptacle (J4) ............................................................................................................................................................. 32
Errata .......................................................................................................................................................................................................... 32
Board Revision History ............................................................................................................................................................................. 32
Document Revision History ....................................................................................................................................................................... 32
Legal Notices ............................................................................................................................................................................................. 33
E-102 Hardware Reference Manual www.picocomputing.com
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Theory of Operation
The purpose of this document is to familiarize you with the E-102 hardware.
The E-102 features a Xilinx Zynq Z-7020 System-on-a-Chip. It is to designed to be a flexible solution in
multiple applications. It can run as an embedded module with a large amount of user I/O, in a standalone
application, or as a USB peripheral device.
Specifications
XC7Z020-CLG484C Programmable SoC (Engineering Silicon)
- 5K Logic Cells
- Dual core ARM Cortex-A9 MPCores up to 667 MHz (-1 speed grade)
- Commercial Temperature grade (0°C to + 5°C)
DDR3 DR M
- 512 MB total density
- 32 bit data bus
- Up to 533 MHz DDR
- 3.97 GB/s total DDR3 bandwidth
USB OTG
- Supports either host or peripheral operation through USB Micro-AB receptacle
- Access to onboard ARM processors through Zynq MIO
USB U RT
- Supports UART connection through USB Micro-B receptacle
- Access to onboard ARM processors through Zynq MIO
HDMI Output
- Output up to 10 0P 24-bit color video through HDMI-Micro (Type-D) receptacle
MicroSD Card
- Boot from MicroSD or MicroSDHC card through Zynq MIO
- A 4GB Class 4 MicroSD card is included
33 Zynq MIO GPIO
- Accessed through Samtec QSH-030-01-L-D-A
⋅Mating Part: QTH-030-02-L-D-A
- 1. V operation
150 Zynq SelectIO GPIO
- Accessed through Samtec QSH-090-01-L-D-A
⋅Mating Part: QTH-090-02-L-D-A
- 3 separate GPIO banks with 2 separate programmable voltage rails
⋅3 pin Voltage ID programming available through hardware or from FPGA
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⋅GPIO Voltage rails available to mating card for up to 1A current draw
DONE, INIT, and GPIO status LEDs
- See “Status LED Description” section for more details
Mechanical and Environmental
- Board Dimensions: 50mm x 0mm
- Commercial Temperature rating
System Monitoring
- Die temperature monitoring
- VCCINT and VCCAUX Voltage monitoring
Included with E-102
- 4GB Class 4 MicroSD card
- MicroSD to full size SD adapter
- USB A Male to Micro-B Male Cable
- JTAG Cable Adapter
Please use anti-static handling precautions when handling the board.
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Mechanical
The E-102 is 50mm x 0mm
It has 1 mounting hole in each of the 4 corners that will fit either a standard #4 screw or a metric M3 screw.
It can mate to a carrier board using Samtec Q-Series I/O connectors (see 33 Zynq MIO GPIO and “150 Zynq SelectIO
GPIO” for mating parts)
Figure – Mechanical drawing - View from top of E-102
Configuration
The Zynq boots through the MicroSD slot. See Firmware and Software docs for more details.
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60mm
Status LED Description
The E-102 utilizes LEDs in order to provide status feedback. The DONE and INIT pins drive the 2 right-most
LEDs in the Figure below. There are also 2 LEDs that are driven by pins on the FPGA and can be used to
indicate statuses chosen by the user.
Figure – Status LEDs
E-102 Hardware Reference Manual www.picocomputing.com
Clock Circuitry
The Zynq on the E-102 has 2 separate clock inputs.
PS_CLK
-PS_CLK is driven by a 33.33 MHz oscillator.
-The Zynq uses this clock to generate all of the appropriate clocks for the ARM and Memory.
-This clock can also be used to generate a logic clock.
SYS_CLK
-SYS_CLK is driven by a 200 MHz low-jitter differential oscillator.
-This clock drives a Multi-Region-Clock-Capable input in the FPGA’s SelectIO.
-SYS_CLK_P and SYS_CLK_N are on FPGA balls Y6 and Y5 respectively.
-
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Table - J pinout
Net Name
FPGA
Ball
J
pin
Logic
Level Pin Type Notes
GND ------ 0 ------ POWER GND Blade on Q-Series Connector
1. V ------ 1 ------ POWER 1. V Power Output
5V ------ 2 ------ POWER Main Power Input OR Output
1. V ------ 3 ------ POWER 1. V Power Output
5V ------ 4 ------ POWER Main Power Input OR Output
1. V ------ 5 ------ POWER 1. V Power Output
5V ------ 6 ------ POWER Main Power Input OR Output
PS_MIO9_500 C4 7 1. V
INPUT/OUTPU
T
PS_MIO13_500 A6 1. V
INPUT/OUTPU
T
PS_MIO7_500 D5 9 1. V
INPUT/OUTPU
T
Pulled high with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_POR_B_500 B5 10 1. V INPUT Held low until 1.5V DDR3 Rail is stable
PS_MIO16_501 D6 11 1. V
INPUT/OUTPU
T
PS_MIO6_500 A4 12 1. V
INPUT/OUTPU
T
Pulled low with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_MIO27_501 D7 13 1. V
INPUT/OUTPU
T
PS_MIO5_500 A3 14 1. V
INPUT/OUTPU
T
Pulled high with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_MIO3_500 F6 15 1. V
INPUT/OUTPU
T
Pulled low with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_MIO14_500 B6 16 1. V
INPUT/OUTPU
T
PS_MIO17_501 E9 17 1. V
INPUT/OUTPU
T
PS_MIO24_501 B7 1 1. V
INPUT/OUTPU
T
PS_SRST_B_50
1 C9 19 1. V INPUT Pulled high with 10K resisitor on E-102
PS_MIO20_501 A 20 1. V
INPUT/OUTPU
T
PS_MIO19_501 E10 21 1. V
INPUT/OUTPU
T
PS_MIO47_501 B10 22 1. V
INPUT/OUTPU
T
PS_MIO11_500 B4 23 1. V
INPUT/OUTPU
T
PS_MIO23_501 E11 24 1. V
INPUT/OUTPU
T
PS_MIO _500 E5 25 1. V
INPUT/OUTPU
T
Pulled high with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_MIO51_501 C10 26 1. V
INPUT/OUTPU
T
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PS_MIO12_500 C5 27 1. V
INPUT/OUTPU
T
PS_MIO1 _501 A7 2 1. V
INPUT/OUTPU
T
PS_MIO15_500 E6 29 1. V
INPUT/OUTPU
T
PS_MIO26_501 A13 30 1. V
INPUT/OUTPU
T
PS_MIO10_500 G7 31 1. V
INPUT/OUTPU
T
PS_MIO22_501 A14 32 1. V
INPUT/OUTPU
T
PS_MIO52_501 D10 33 1. V
INPUT/OUTPU
T
PS_MIO50_501 D13 34 1. V
INPUT/OUTPU
T
PS_MIO53_501 C12 35 1. V
INPUT/OUTPU
T
PS_MIO46_501 D12 36 1. V
INPUT/OUTPU
T
PS_MIO4_500 E4 37 1. V
INPUT/OUTPU
T
Pulled high with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_MIO21_501 F11 3 1. V
INPUT/OUTPU
T
PS_MIO2_500 A2 39 1. V
INPUT/OUTPU
T
Pulled low with 20K resistor on E-102. Pin is polled at
powerup for Boot-up settings
PS_MIO25_501 F12 40 1. V
INPUT/OUTPU
T
PS_MIO1_500 A1 41 1. V
INPUT/OUTPU
T
------ ------ 42 ------ NC
------ ------ 43 ------ NC
------ ------ 44 ------ NC
------ ------ 45 ------ NC
------ ------ 46 ------ NC
------ ------ 47 ------ NC
------ ------ 4 ------ NC
------ ------ 49 ------ NC
------ ------ 50 ------ NC
------ ------ 51 ------ NC
------ ------ 52 ------ NC
------ ------ 53 ------ NC
------ ------ 54 ------ NC
------ ------ 55 ------ NC
------ ------ 56 ------ NC
------ ------ 57 ------ NC
------ ------ 5 ------ NC
------ ------ 59 ------ NC
------ ------ 60 ------ NC
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Table - J5 pinout
Net Name
FPGA
Ball
J5
pin
Logic
Level Pin Type Notes
GND ------ 0 ------ POWER GND Blade on Q-Series Connector
GPIO_001 Y16 1 VGPIO0
INPUT/OUTPU
T
GPIO_002 W21 2 VGPIO0
INPUT/OUTPU
T
GPIO_003 W17 3 VGPIO0
INPUT/OUTPU
T
GPIO_004 W22 4 VGPIO0
INPUT/OUTPU
T
GPIO_005 AA1 5 VGPIO0
INPUT/OUTPU
T
GPIO_006 AA19 6 VGPIO0
INPUT/OUTPU
T
GPIO_007 Y1 7 VGPIO0
INPUT/OUTPU
T
GPIO_00 AB17 VGPIO0
INPUT/OUTPU
T
GPIO_009 Y19 9 VGPIO0
INPUT/OUTPU
T
GPIO_010 AB14 10 VGPIO0
INPUT/OUTPU
T
GPIO_011 Y20 11 VGPIO0
INPUT/OUTPU
T
GPIO_012 AB15 12 VGPIO0
INPUT/OUTPU
T
GPIO_013 Y21 13 VGPIO0
INPUT/OUTPU
T
GPIO_014 AA14 14 VGPIO0
INPUT/OUTPU
T
GPIO_015 AA21 15 VGPIO0
INPUT/OUTPU
T
GPIO_016 AA17 16 VGPIO0
INPUT/OUTPU
T
GPIO_017 AA16 17 VGPIO0
INPUT/OUTPU
T
GPIO_01 AA13 1 VGPIO0
INPUT/OUTPU
T
GPIO_019 V15 19 VGPIO0
INPUT/OUTPU
T
GPIO_020 AB16 20 VGPIO0
INPUT/OUTPU
T
GPIO_021 W15 21 VGPIO0
INPUT/OUTPU
T
GPIO_022 V13 22 VGPIO0
INPUT/OUTPU
T
GPIO_023 Y14 23 VGPIO0
INPUT/OUTPU
T
GPIO_024 U17 24 VGPIO0
INPUT/OUTPU
T
GPIO_025 V14 25 VGPIO0
INPUT/OUTPU
T
GPIO_026 U14 26 VGPIO0
INPUT/OUTPU
T
GPIO_027 Y13 27 VGPIO0
INPUT/OUTPU
T
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GPIO_02 U15 2 VGPIO0
INPUT/OUTPU
T
GPIO_029 W13 29 VGPIO0
INPUT/OUTPU
T
GPIO_030 U16 30 VGPIO0
INPUT/OUTPU
T
GPIO_031 Y15 31 VGPIO0
INPUT/OUTPU
T
GPIO_032 W16 32 VGPIO0
INPUT/OUTPU
T
GPIO_033 U20 33 VGPIO0
INPUT/OUTPU
T
GPIO_034 V17 34 VGPIO0
INPUT/OUTPU
T
GPIO_035 U19 35 VGPIO0
INPUT/OUTPU
T
GPIO_036 T22 36 VGPIO0
INPUT/OUTPU
T
GPIO_037 V1 37 VGPIO0
INPUT/OUTPU
T
GPIO_03 U22 3 VGPIO0
INPUT/OUTPU
T
GPIO_039 V19 39 VGPIO0
INPUT/OUTPU
T
GPIO_040 V22 40 VGPIO0
INPUT/OUTPU
T
GPIO_041 W1 41 VGPIO0
INPUT/OUTPU
T
GPIO_042 AB22 42 VGPIO0
INPUT/OUTPU
T
GPIO_043 V20 43 VGPIO0
INPUT/OUTPU
T
GPIO_044 AB21 44 VGPIO0
INPUT/OUTPU
T
GPIO_045 W20 45 VGPIO0
INPUT/OUTPU
T
GPIO_046 AB20 46 VGPIO0
INPUT/OUTPU
T
GPIO_047 U21 47 VGPIO0
INPUT/OUTPU
T
GPIO_04 AB19 4 VGPIO0
INPUT/OUTPU
T
GPIO_049 T21 49 VGPIO0
INPUT/OUTPU
T
GPIO_050 AA22 50 VGPIO0
INPUT/OUTPU
T
------ ------ 51 ------ NC
------ ------ 52 ------ NC
------ ------ 53 ------ NC
USER_VGPIO_E
N Y11 54 1. V INPUT
Enable for VGPIO0 and VGPIO1. Pulled low WITH
1.62K resistor on E-102 to diable these regulators by
default. Can be controlled in hardware from carrier
board or in firmware from FPGA
VGPIO0 ------ 55 ------ POWER Voltage ouput for VGPIO0 - Disabled by default
VGPIO0_VS2 V 56 1. V INPUT
Voltage Selection for VGPIO0. Pulled low WITH 1K
resistor on E-102 for default 3.3V operation. Can be
controlled in hardware from carrier board or in
firmware from FPGA
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VGPIO0 ------ 57 ------ POWER Voltage ouput for VGPIO0 - Disabled by default
VGPIO0_VS1 V7 5 1. V INPUT
Voltage Selection for VGPIO0. Pulled low WITH 1K
resistor on E-102 for default 3.3V operation. Can be
controlled in hardware from carrier board or in
firmware from FPGA
VGPIO0 ------ 59 ------ POWER Voltage ouput for VGPIO0 - Disabled by default
VGPIO0_VS0 U6 60 1. V INPUT
Voltage Selection for VGPIO0. Pulled low WITH 1K
resistor on E-102 for default 3.3V operation. Can be
controlled in hardware from carrier board or in
firmware from FPGA
------ ------ 61 ------ NC
5V ------ 62 ------ POWER Main Power Input OR Output
------ ------ 63 ------ NC
5V ------ 64 ------ POWER Main Power Input OR Output
GPIO_051 R16 65 VGPIO1
INPUT/OUTPU
T
GPIO_052 P15 66 VGPIO1
INPUT/OUTPU
T
GPIO_053 P16 67 VGPIO1
INPUT/OUTPU
T
GPIO_054 E19 6 VGPIO1
INPUT/OUTPU
T
GPIO_055 T16 69 VGPIO1
INPUT/OUTPU
T
GPIO_056 F19 70 VGPIO1
INPUT/OUTPU
T
GPIO_057 P17 71 VGPIO1
INPUT/OUTPU
T
GPIO_05 G20 72 VGPIO1
INPUT/OUTPU
T
GPIO_059 R1 73 VGPIO1
INPUT/OUTPU
T
GPIO_060 T19 74 VGPIO1
INPUT/OUTPU
T
GPIO_061 T17 75 VGPIO1
INPUT/OUTPU
T
GPIO_062 H19 76 VGPIO1
INPUT/OUTPU
T
GPIO_063 P20 77 VGPIO1
INPUT/OUTPU
T
GPIO_064 R20 7 VGPIO1
INPUT/OUTPU
T
GPIO_065 T1 79 VGPIO1
INPUT/OUTPU
T
GPIO_066 R21 0 VGPIO1
INPUT/OUTPU
T
GPIO_067 P1 1 VGPIO1
INPUT/OUTPU
T
GPIO_06 P22 2 VGPIO1
INPUT/OUTPU
T
GPIO_069 R19 3 VGPIO1
INPUT/OUTPU
T
GPIO_070 P21 4 VGPIO1
INPUT/OUTPU
T
GPIO_071 N17 5 VGPIO1
INPUT/OUTPU
T
GPIO_072 N22 6 VGPIO1
INPUT/OUTPU
T
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GPIO_073 M17 7 VGPIO1
INPUT/OUTPU
T
GPIO_074 N20 VGPIO1
INPUT/OUTPU
T
GPIO_075 R15 9 VGPIO1
INPUT/OUTPU
T
GPIO_076 M22 90 VGPIO1
INPUT/OUTPU
T
GPIO_077 N19 91 VGPIO1
INPUT/OUTPU
T
GPIO_07 E20 92 VGPIO1
INPUT/OUTPU
T
GPIO_079 M19 93 VGPIO1
INPUT/OUTPU
T
GPIO_0 0 D20 94 VGPIO1
INPUT/OUTPU
T
GPIO_0 1 M20 95 VGPIO1
INPUT/OUTPU
T
GPIO_0 2 D1 96 VGPIO1
INPUT/OUTPU
T
GPIO_0 3 L19 97 VGPIO1
INPUT/OUTPU
T
GPIO_0 4 C19 9 VGPIO1
INPUT/OUTPU
T
GPIO_0 5 K19 99 VGPIO1
INPUT/OUTPU
T
GPIO_0 6 B20 100 VGPIO1
INPUT/OUTPU
T
GPIO_0 7 J1 101 VGPIO1
INPUT/OUTPU
T
GPIO_0 D17 102 VGPIO1
INPUT/OUTPU
T
GPIO_0 9 J20 103 VGPIO1
INPUT/OUTPU
T
GPIO_090 C17 104 VGPIO1
INPUT/OUTPU
T
GPIO_091 K20 105 VGPIO1
INPUT/OUTPU
T
GPIO_092 D16 106 VGPIO1
INPUT/OUTPU
T
GPIO_093 K21 107 VGPIO1
INPUT/OUTPU
T
GPIO_094 N15 10 VGPIO1
INPUT/OUTPU
T
GPIO_095 L21 109 VGPIO1
INPUT/OUTPU
T
GPIO_096 N1 110 VGPIO1
INPUT/OUTPU
T
GPIO_097 L22 111 VGPIO1
INPUT/OUTPU
T
GPIO_09 M16 112 VGPIO1
INPUT/OUTPU
T
GPIO_099 M21 113 VGPIO1
INPUT/OUTPU
T
GPIO_100 L1 114 VGPIO1
INPUT/OUTPU
T
VGPIO1 ------ 115 ------ POWER Voltage ouput for VGPIO1 - Disabled by default
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VGPIO1_VS2 U12 116 1. V INPUT
Voltage Selection for VGPIO1. Pulled low WITH 1K
resistor on E-102 for default 3.3V operation. Can be
controlled in hardware from carrier board or in
firmware from FPGA
VGPIO1 ------ 117 ------ POWER Voltage ouput for VGPIO1 - Disabled by default
VGPIO1_VS1 V12 11 1. V INPUT
Voltage Selection for VGPIO1. Pulled low WITH 1K
resistor on E-102 for default 3.3V operation. Can be
controlled in hardware from carrier board or in
firmware from FPGA
VGPIO1 ------ 119 ------ POWER Voltage ouput for VGPIO1 - Disabled by default
VGPIO1_VS0 W12 120 1. V INPUT
Voltage Selection for VGPIO1. Pulled low WITH 1K
resistor on E-102 for default 3.3V operation. Can be
controlled in hardware from carrier board or in
firmware from FPGA
------ ------ 121 ------ NC
5V ------ 122 ------ POWER Main Power Input OR Output
------ ------ 123 ------ NC
5V ------ 124 ------ POWER Main Power Input OR Output
------ ------ 125 ------ NC
------ ------ 126 ------ NC
------ ------ 127 ------ NC
------ ------ 12 ------ NC
------ ------ 129 ------ NC
------ ------ 130 ------ NC
GPIO_101 G22 131 VGPIO1
INPUT/OUTPU
T
GPIO_102 K1 132 VGPIO1
INPUT/OUTPU
T
GPIO_103 H20 133 VGPIO1
INPUT/OUTPU
T
GPIO_104 J17 134 VGPIO1
INPUT/OUTPU
T
GPIO_105 H22 135 VGPIO1
INPUT/OUTPU
T
GPIO_106 H1 136 VGPIO1
INPUT/OUTPU
T
GPIO_107 J21 137 VGPIO1
INPUT/OUTPU
T
GPIO_10 H17 13 VGPIO1
INPUT/OUTPU
T
GPIO_109 J22 139 VGPIO1
INPUT/OUTPU
T
GPIO_110 G19 140 VGPIO1
INPUT/OUTPU
T
GPIO_111 E21 141 VGPIO1
INPUT/OUTPU
T
GPIO_112 F1 142 VGPIO1
INPUT/OUTPU
T
GPIO_113 F21 143 VGPIO1
INPUT/OUTPU
T
GPIO_114 E1 144 VGPIO1
INPUT/OUTPU
T
GPIO_115 F22 145 VGPIO1
INPUT/OUTPU
T
GPIO_116 E16 146 VGPIO1
INPUT/OUTPU
T
GPIO_117 G21 147 VGPIO1
INPUT/OUTPU
T
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GPIO_11 D15 14 VGPIO1
INPUT/OUTPU
T
GPIO_119 D22 149 VGPIO1
INPUT/OUTPU
T
GPIO_120 C15 150 VGPIO1
INPUT/OUTPU
T
GPIO_121 B22 151 VGPIO1
INPUT/OUTPU
T
GPIO_122 B15 152 VGPIO1
INPUT/OUTPU
T
GPIO_123 C20 153 VGPIO1
INPUT/OUTPU
T
GPIO_124 E15 154 VGPIO1
INPUT/OUTPU
T
GPIO_125 C22 155 VGPIO1
INPUT/OUTPU
T
GPIO_126 M15 156 VGPIO1
INPUT/OUTPU
T
GPIO_127 D21 157 VGPIO1
INPUT/OUTPU
T
GPIO_12 L17 15 VGPIO1
INPUT/OUTPU
T
GPIO_129 B21 159 VGPIO1
INPUT/OUTPU
T
GPIO_130 L16 160 VGPIO1
INPUT/OUTPU
T
GPIO_131 A19 161 VGPIO1
INPUT/OUTPU
T
GPIO_132 K16 162 VGPIO1
INPUT/OUTPU
T
Pulled low on E-102 with 10K resistor for proper
PUDC operation
GPIO_133 B19 163 VGPIO1
INPUT/OUTPU
T
GPIO_134 J16 164 VGPIO1
INPUT/OUTPU
T
GPIO_135 A21 165 VGPIO1
INPUT/OUTPU
T
GPIO_136 G17 166 VGPIO1
INPUT/OUTPU
T
GPIO_137 A22 167 VGPIO1
INPUT/OUTPU
T
GPIO_13 F17 16 VGPIO1
INPUT/OUTPU
T
GPIO_139 A1 169 VGPIO1
INPUT/OUTPU
T
GPIO_140 F16 170 VGPIO1
INPUT/OUTPU
T
GPIO_141 C1 171 VGPIO1
INPUT/OUTPU
T
GPIO_142 K15 172 VGPIO1
INPUT/OUTPU
T
GPIO_143 A17 173 VGPIO1
INPUT/OUTPU
T
GPIO_144 J15 174 VGPIO1
INPUT/OUTPU
T
GPIO_145 B17 175 VGPIO1
INPUT/OUTPU
T
GPIO_146 H15 176 VGPIO1
INPUT/OUTPU
T
E-102 Hardware Reference Manual www.picocomputing.com
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Power
The E-102 can be powered AND supply power through multiple channels:
GPIO connectors (J5 & J8)
-The 5V rail connects directly to 4 pins on J5 and 3 pins on J .
-Power can be sourced from either the E-102 OR from a carrier board using these pins.
-If power is sourced through these connectors, proper precautions (power OR-ing and current
backflow protection) should be taken to ensure no damage is done to the power supply.
USB-OTG Receptacle (J7)
-There is Power OR-ing circuitry in place to prevent over-currenting and current backflow to the
source through this connector.
-When the E-102 is operating as a USB peripheral, power can be sourced to the E-102 through this
connector.
-When the E-102 is operating as a USB Host, power can be sourced from the E-102 to the
downstream peripheral device. In order to support doing this, a jumper needs to be placed across the
2 pins on S1 (this bypasses the power OR-ing circuitry).
oTotal current available for powering peripheral devices is limited by the method used to
source this current (whether the card is powered through the J5 & J , or J4).
USB-U RT Receptacle (J4)
-There is Power OR-ing circuitry in place to prevent over-currenting and current backflow to the
source through this connector.
When power is supplied to the E-102 through either the USB-OTG or the USB-UART receptacles, power
consumption should be limited to the USB specified 2.5W. Sourcing power through both the USB-OTG and the
USB-UART receptacles will allow for up to a 5W power budget. When power is sourced through the GPIO
connectors, power consumption is limited by the power supplies onboard. Refer to “Table - Power Specifications”
for more detailed information about power consumption.
Table - Power Specifications
Minimum Nominal Maximum
DC Input Voltag J5, J8, J7, J4 4.75V 5.0V 5.25V
PS Pow r TBD TBD TBD
PL Pow r TBD TBD TBD
Errata
Board Revision History
Table - Board Revision History
V rsion
R l as
Dat D scription
Rev A Jul-12 Prototype Release – E ilicon
Rev B Oct-12 First Production Release – E ilicon
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