Pioneer QX-949A Series User manual

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CONTENTS
1.
2.
3.
4.
5.
6.
SPECIFICATIONS 3
5
I
FRONT PANEL FACILITIES ...
CONNECTION DIAGRAM
BLOCK DIAGRAM
LEVEL DIAGRAM
CIRCUIT DESCRIPTIONS
6.1 FM Tuner Section
6.2 AM Tuner Section
6.3 CD-4 Demodulator Section
6.4 SO Full Logic/RM Decoder Section
6.5 Control Amplifier
6.6 Power Amplifier Section
6.7 Protection Circuit
DISASSEMBLY
7.1 Wooden Gabinet
7.2 Bottom Plate .
7.3 Front Panel .
ADJUSTMENTS
8.1 AM Section
8.2 FM Section
9.3 FM MPX Section
C
8.4 Power Amplifier Section
DIAL CORD STRINGING
PARTS LOCATIONS
10.1 Front View 1
1O.2 Front View 2
10.3 TopView ...... 37
10.4 Bottom View. 39
10.5 Rear View 41
11. EXPLODED VIEWS 43
12. PACKING 52
13. SCHEMATIC DIAGRAMS, P.C. BOARD PATTERNS AND
PARTS LISTS
13.1 Schematic Diagrams and Miscellaneous Parts . 53
'13.2 TunerAssembly(AwE-041) .... 61
11
13
7.
8.
14
14
16
20
23
24
24
26
26
27
28
29
30
31
32
33
35
9.
10.

13.3 Headphone Jack Assembly (AWX-054) . . G7
13.4 Power Supply Circuit B Assembly (AWR-039) 68
13.5 CD-4Assembly(AWM-076) ...... 69
13.6 SO/RM Decoder Assembly (AWM-077) 77
13.7 ProtectionCircuitAssembly (AWM-079) ...... 83
13.8 Control Amplifier Assembly (AWG-023) 86
13.9 Power Supply Circuit A Assembly (AWR-080) 91
13.10 SwitchCircuitAssembly (AWS-048) ...... 94
13.11 Power Amplifier Assembly (AWH-027) gB
14. PARTS LIST OF EXPLODED VIEWS . . . . . .102
NOTE:
THE MODEL QX-949A COMES IN TWO VERSIONS DISTINGUISHED AS FOLLOWS:
Round label on
rear panel Voltage Type
F
KCU
110V, ]-20V,130V,220V,
and 240V (switchable)
120V only
General export model
UL (U.S.A.) and
CSA(Canada) approved

ABOUT 2CH POWER BOOSTING SWITCH
To increase available power when using the QX-949A for
2-channel reproduction, a convenient power select fea-
ture is incorporated. The covered compartment on the
rear panel houses a reversable connector panel. When
added power is desired during 2-channel operation tum
off set power. Open the cover, remove the connector
panel and rotate it 180o, then re-insert it and close the
cover. Be sure to reverse the connector again before
retuming to 4-channel operation.
These illustrations show how the boosting switch is employed.
:1 J
Pull out connector Rotate connector 180" and re-insert it
Loosen screw to open cover
CHANGING LINE VOLTAGE SETTING AND FUSE
(F MODEL)
To remove the fuse, unscrew the fuse cap located in the
center of the line voltage selector and withdraw it,
together with the fuse. Next, pull the line voltage
selector plug out of its socket, rotate it until the
cutaway aligns with the appropriate line voltage marked
on the back of the unit, then push it back into its socket.
It is important to check the rating of the fuse; a 3A
fuse should be used with either 220Y or 240V, while a
6.4 fuse should be used for 110V, 720V, or 130V
operation. If the fuse rating is correct, reinsert it and
screw in the fuse cap.
No selector plug is provided for "KCU" type (120V only
model).
PHTLLTPS
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LECTOR PLUG

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5. LEVEL DIAGRAM
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.trequency at lkllz
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6. CIRCUIT DESCRIPTIONS
6.1 FM TUNER SECTION
Front End
This consists of. a 4-gang variable capacitor tuning
circuit, dual-gate MOS FET RF amplifier and
mixer, and local oscillator with buffer. By employ-
ing a glounded gate-Z of the dual-gate MOS FpT,
the circuit becomes equivalent to a cascade ampli-
fier, providing large gain with stable operation in
the RF amplifier.
In the mixer stage, the signal is applied from the
local oscillator to gate-2. This method allows input
power from the local oscillator to be minimized
and features low mutual interference. A variation
of a Clapp circuit forms the local oscillator and by
inserting a buffer amplifier between it and the
mixer, the oscillator load is reduced and waveform
distortion suppressed. The oscillation frequency
drawing effect is also eliminated, to provide
extremely stable operation even with strong inputs.
lF Amplifier and Detector
These are composed of three dual-element ceramic
filters and two integrated circuits. The first stage
IC (HA1201") incorporates a current limiter, while
the second stage IC (HA1137) is shown in Fig. 2.
When pin 12 of HA1137 is at more than xTOkHz
detuning and with an extremely low input level,
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a DC voltage is produced. By setting the FM
Muting switch to ON, pin 12 is connected to pin
5, and the analog switch in HA1137 is operated
ON-OFF to perform muting.
Multiplex Decoder
Demodulation is performed by switching detection
with the circuit contained in the IC (HA1156),
depicted in Fig. 3. A phase locked loop (PLL)
produces a 38kHz square wave synchronized to
the pilot signal. The two gates are alternately
switched ON-OFF by this signal to derive the L
and R channels from the composite signal. By
detecting the pilot signal level, the switching signal
from PLL to demodulator is operated ON-OFF.
The STEREO indicator lights at the same time.
6.2 AM TUNER SECTION
This consists of a 3-gang variable capacitor tuning
circuit, a dual element ceramic filter and an IC
(HA1138). The IC (Fig. 4) contains an RF stage
and two IF amplifier stages.
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4channel
level indicator
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Switching signat ( 3gkllz)
lC: HA1156
lC: HA1138
Fis.4
15

6.3 CD-4 DEMODULATOR SECTION
Fig. 5 illustrates the composition of this section.
Sum Signal System
IC HA1452 is an orthodox 2-channel equalizer
amplifier. In CD-4 operation, a variable resistor is
inserted in the NFB circuit to provide separation
control by varying the main signal (sum signal)
gain. Although the final objective of the CD-4
demodulator is to matrix the sum and difference
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Separati on
control
RECORDING AND PLAYBACK OF CD.4 DISCS
The CD-4 disc is a recent development. Being a
"Discrete" 4-channel medium, it features excellent
channel separation when played over suitable 4-
channel equipment, but can also be played as a
conventional 2-channel stereo record.
Fig. 6 shows the configuration of signals present
in a CD-4 record.
Each of the two sub-signals occupies a frequency
modulated supersonic carrier with a center fre-
quency of 30kHz.
The sub-signal conveys the "Front-Rear" differ-
ence information.
The main signals are recorded as a conventional
LEFT CHANNEL
signals, as the difference signal is demodulated
from a frequency modulated 30kHz carrier (sub
signal), and the sum signal varies according to the
cartridge output level (though indirectly related),
level matching becomes necessaq/.
In other than the CD-4 mode, a fixed resistor
replaces of the variable resistor to provide a fixed
gain (35.6d8 at lkHz) equalizer amplifier. The
inclusion of a balanced power supply with this
circuit maintains input and output point potentials
at 0V, preventing click noises when switches are
operated. The 100kS2 impedance of this circuit is
changed to 50kA by inserting two 100k0 resistors
in parallel during other than CD-4 operation.
A. 11. R. S. Fig. 5
stereo record, occupying the 30Hz - 15kHz audio
band and conveying the "Front+Rear" sum inform-
ation.
From these sum and difference signals, the original
4 channel signals are retrieved in a series of
algebraic operations performed in the demodulatori
(Lf+Lr)+(Lf-Lr\=ZLf.
(Lf+Lr)-(Lf-Lr)=2Lr
(Rt+Rr)+(Rf-Rr)=2R,t
(Rf+Rr)-(Rf-Rr):2Rr
where (6R" stands for Right, "L" for Left, "f" for
front, "r" for rear.
DISC SURFACE
R]GHT CHANNEL
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The equalizer amplifier output goes through a low
pass filter (LPF) to remove the sub signal (30kHz
FM signal). This LPF is an active filter whose
frequency response is shown in Fig. 7.
5I I 0k 30t 50k I 00r
Frequency (llz) Fig.7
Difference Signal System
The sub signal is taken from the equalizer amplifier
NFB circuit. As it does not pass through the RIAA
playback standard equalizer, it possesses a flat
frequency response. After passing through a high
pass filter (fc = 27kHz, L?dBloct.), the sub signal
enters IC HA1335.
This IC contains a phase locked loop (PLL) FM
demodulator circuit, an automatic gain control
(AGC) circuit to stabilize the PLL input signal,
a muting circuit to cut the demodulated output
in the absence of an input signal, and a demodu-
Iated signal amplifier. In addition to the IC, a
de-emphasis circuit, automatic capture range con-
trol (ACC) circuit, LPF, HPF, indicator lamp drive,
and other circuits are used to demodulate the dif-
ference signal from the sub signal.
*AGC Amplifier
Fig. 8 shows the AGC amplifier principle. In this
circuit, e1 is the input signal voltage, e2 the output
signal voltage, Vr the reference voltage, and Vb
the control voltage.
If Vb is much greater than Vr, 13 becomes approx-
imately equal to I, and e2 o. 0. Conversely, if Vb
is much less than Vr, 13 becomes approximately
equal to I, and e, reaches a maximum (determined
by the murimum gain of the AGC amplifier). The
amplifier gain can therefore be controlled by Vb
in this manner, Vb being obtained from a synchro-
nous detector.
*FM Demodulator
The block diagram of the PLL FM demodulator
circuit is depicted in Fig. 9. This circuit consists
of a voltage control oscillator (VCO), phase com-
parator (PC), DC amplifier (A) and low pass filter
(LPF), with a type of NFB loop following the
input signal. The VCO oscillates at a controlled
frequency according to the LPF output voltage.
A voltage proportional to the phase difference
between the input signal and VCO oscillation out-
put is generated in the PC. By using this voltage
to control the VCO oscillation, the oscillation
becomes locked to the input signal phase.
If the input signal is frequency modulated, the
control signal obtained from the LPF becomes the
FM demodulated output. With an excessively
large frequency deviation of the input signal, which
the PLL circuit cannot follow, the lock becomes
disengaged. The frequency range in which locking
can be performed is termed the lock range.
Locking also becomes impossible when the VCO
free running frequency (oscillating frequency with-
out an input signal) and input signal frequency are
excessively separated. The frequency range in
which locking can be performed is termed the
capture range. The locking and capture ranges are
determined by the PLL loop gain and LPF con-
stant.
Fig.8
-30
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I
17

6.4 SO FULL LOGIC/RM DECODER SECTION
SQ System
The Matrix four channel system utilizes 2-channel
media (tape, records, broadcasts, etc.) to transmit
4 or more channel signals. Four channel playback
systems employ matrixing 4-2-4 (n-2-$ to convert
2-channel into 4-channel. The main systems cur-
rently available for this purpose are RM (Regular
Matrix) and SQ (Stereo Quad).
With the RM system, if the only sound source is
LF (left front), - 3dB crosstalk occurs in the RF
(right front) and LB (left back). In the SQ system
however, - 3dB occurs in LB and RB (right back).
RM and SQ are therefore not compatible.
Fig. 13 shows the basic SQ decoder construction
and signal vectors. LT and RT are combined in LB
and RB, while LF' and RF' are taken directly
from LT and RT. LB' and RB' are obtained from
LT and RT by phase shifting and blending. But
LB' and RB' contain respective LF, RF other than
necessary components. Left and right separation
remains good since LF' does not combine with
RF, and RF' does not combine with LF.
If the sound source is CF (center front) or CB
(center back), front to rear separation cannot be
obtained since LF', RF', LB' and RB' all become
the same volume. The logic circuit is provided for
improve this effect.
With CF crosstalk to LB and RB is at out of and
since with CB crosstalk to LF and RF is also at
out of, only these anti-phase components are
cancelled. This is termed front-back logic. The
objective of full logic is to deal not only with CF
and CB sound sources, but also with various other
directions.
Front-back logic performs CF and CB detection,
while wave matching logic performs LF, RF-, LB
and RB detection. The combined detector signal
passes through a time constant circuit and is
applied to the gain control circuit, where gain is
controlled in order to adequately reduce the cross-
talk level.
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Circuit Composition
Three ICs are employed, as shown in Fig. lb.
M5165LP is an SQ basic decoder and can function
€rs an SQ decoder without independent logic.
Although a phase shift network is not included,
by a CR network, this IC perform to shift the
phase 90' with cover wide range. A selector switch
also permits the IC to be used as an RM decoder.
During RM, a blend resistor is added at the front,
while the rear is blended internally by the IC and
taken from separate terminals.
CX.049 is a high density full logic IC incorporating
both wave matching and front back logic. CX-718D
is a gain control IC and contains four MOS FETs
to form a variable resistance voltage control circuit.
Since these MOS FETs are P channel enhancement
types, equivalent internal resistance becomes in-
finite when gate voltage is zero. By applying a
negative voltage to the gate (Fig.!4), the equivalent
internal resistance can be varied from infinity to
several hundred ohms.
r--- -_J
Basic decoder
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2SK40V (FET) is employed for back blending.
With a CF sound source, it functions to cancel
the mutually opposite crosstalk phase to LB and
RB. This is an N channel depletion type junction
FET and when the gate voltage is zero) the channel
is already established. LB and RB become normally
blended for this reason, and the gate becomes open
only in the case of a single signal from LB or RB.
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Fis. 14
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Time constant circuit
F is. 15

Operating Description
The input signal (LT & RT) enters the Se basic
decoder (M51651P), where 4-channel signals LF,
RF, LB and RB are obtained by the Se decode
matrix, then these signals enter the gain control,
back blend and logic cirbuits. The front-back logic
produces a positive voltage with a CF sound
source, and a negative one with a CB source. This
voltage passes through the time constant circuit
and is applied to the gates of the MOS FETs for
LF and RF gain control.
As these FETs are P channel enhancement types,
their equivalent internal resistance decreases only
when a negative voltage is applied. Front (LF &
RF) output signal levels are attenuated with a CB
sound source.
For rear control, wave matching logic produces a
negative voltage with respect to a front single signal
(LF or RF) and a positive voltage with respect to
a rear single signal (LB or RB). Front control is
also performed by producing the reverse polarity
of these voltages.
The rear control voltage passes through the time
constant circuit and is applied to the gates of
MOS FETs for LB and RB gain control. The front
control voltage passes through the time constant
circuit and is applied to the gates of the junction
FET for back blend and the MOS FETs for LF
and LB gain control. As the junction FET is an N
channel depletion type, LB and RB are normally
blended, but the device becomes open when a
negative voltage is applied.
The detector outputs of the full logic IC (CX-049)
with respect to sound source are as shown in the
following table.
*Gain control operates (attenuates) with (-) detecting
mode.
*xFront bach logic output B is not employed.
x**Back blend is not p?rformed only when waue matching
logic output F mode is (-).
LF RF LB RB CF CB Gain control*
FIB
logic
W/M
logic
F00 0 0+LF, RF
B0000+IF iF
F++00LF, RF***
B++0 0 LB, RB
CAUTI ON
The gain control lC (CX-718D) is an MOS (metal oxide semiconductor) type and subject to
dielectric breakdown from static electricity. Note the following precaution when handling.
*Do not remove the aluminum cap from the tC until it has been instalted in teh circuit. First
solder the lc to the circuit board, then remove the aluminum cap.
?2

6.5 CONTROL AMPLIFIER CIRCUIT
The control amplifier circuit of the QX-949A is
the NFB type, using a FET (fietd effect transistor)
in the first stage.
The FET amplifier being a controlable voltage
type, which holds"the input impedance constant,
even if the level of the NFB changes, and has
additional advantage as a coupled circuit, as the
input impedance can be raised
Low Frequency Control
The low frequency control circuit is shown in
Fig. 16, and the equivalent circuit, when boosting
low frequency, is shown in Fig. 17.
As the parallel impedance of VR1 and C29, in
Fig. 17, is high at low frequency, the volume of
the NFB decreases and the gain in the low
frequency range increases.
The equivalent circuit, when cutting out low
frequencies, is shown in Fig. 18. In this case, the
input signal is applied to Q9, through the parallel
impedance of VR1 and C33, which is high in the
low frequency range and suppresses the lower
frequency signals.
High Frequency Control
The high frequency control circuit is shown in
Fig. 19, and the equivalent circuit, when boosting
high frequencies, is shown in Fig. 20.
In this circuit, the input signal is applied to Q9
through the parallel impedance circuit. This imped-
ance is small in the high frequency range and
produces a signal with an enhanced high range.
Fig. 21 shows the equivalent circuit when cutting
out high frequencies. As the impedance of R53,
R41 and C4L of the circuit becomes small, the
level of the NFB increases and the gain of the
circuit decreases.
BX.949A
Fis. 16
Fig. 17
Fis. 18
F is. 19
7
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Fig. 20 Fig.21
23

6.6 POWER AMPLIFIER SECTION
This unit possesses four power amplifiers. The
circuitry employs a balanced power supply and
consists of direct-coupled Darlington connection
pure complementary OCL amplifiers. By applying
1007o DC NFB from the output stage center point
to the first stage differential amplifier, circuit DC
gain becomes 0dB. Since the center point potential
is determined by the first stage base potenfial,
temperature compensating and fine adjustment
circuits are included in the first stage base bias
circuit to maintain the center point potential at 0V.
2-channel Power Boosting Circuit
The power supply can be boosted when using this
unit as a Z-channel stereo amplifier (using only
ch1 and ch3, and with the MODE switch set to
zCH). Power transistors of channels 1 and 3 are
of higher rating than those of channels 2 and 4.
Their supply voltage can be raised during 2-channel
operation to provide increased power to each chan-
nel.
Power boosting is available by turning over the
rear panel plug. This raises the power transformer
secondary winding taps and opens CHz and CH4
power amplifier output circuits.
For safety reasons, a microswitch in the power
transformer primary side cuts off the power supply
when the selector plug cover is opened.
6"7 PROTECTION CIRCUIT
This protection circuit functions to protect the
speakers from damage due to short-circuit of the
load, etc., and performs a muting operation to cut
noise and distortion which occur when switching
the power on and off.
The circuit is shown in Fig. 22, and consists of a
bridge type over-current and overload detector, a
differential amplifier DC voltage detector, and a
power switch on/off detector section.
Relay Driving Circuit
Q7 - Q9, in Fig. 22, comprise the relay driving
circuit.
In the normal condition reverse bias is applied to
the base of Q7, and Q7 is in a cutout condition.
When one of the above mentioned detection
circuits goes on, current flows through R28, the
base potential falls and Q7 is turned on. Con-
sequently Q8 comes on and Q9 goes off. When
Q9 goes off, the current of the relay circuit is
cut, to release the switch of the output circuit.
When the power switch is turned oo, a delay
operation occurs in this circuit. R33, R34 and
C7, in the base circuit of Q9, are the time con-
stant elements which determine the delay time.
When the power switch is switched on, C7 charges
to a potential of +30 volts through R33 and R34,
and Q9 is kept in the OFF condition during this
time. When the power source is switched off the
muting operation of Q8 prevents shock noise.
In the normal condition, the potentials of +30
volts and - 5.1 volts are applied to Q8 through
R31 and R32. The resultant potential at the base
of Q8 is -1 volt in the cutout condition. When the
power supply is turned off, the potential of - 5.1
volts disappears immediately, due to the small
time constant of the power circuit. Thus a positive
base potential remains, switching Q8 on, which in
turn switches off Q9 and hence the relay.
Relay driving circuit
L ---- ---- --l
DC voltage
detection circuit
---- r--r-iivl
Fig.22

Over-current and Overload Detection
The equivalent circuit of this detector section is
shown in Fig. 23, andFig. 24 shows the equivalent
circuit at the time of a positive half cycle. When
this equivalent circuit is overloaded, the balance of
the bridge, formed by REI-, R1, Rg and RL, is
disturbed, and a potential is produced between b
and a in such a direction that Q1 is turned on.
When Q1 is turned oo, the collector- current
increases, the relay driving circuit functions and
the relay switch of the output circuit is turned off.
After the cause of the overload is removed, the
bias of Q1 is reduced and the relay switch turns
on to automatically restore normal operation,
Fig. 25 shows the equivalent circuit at the time
of a negative half cycle. In this circuit a potentiat
is produced between b and e as above, and Q1
is turned on.
Detection of DC Voltage
This is a differential amplifier consisting of Qb
and Q6, as shown in Fig. 26. The bases of Qb
and Q6 are connected to the junction-points of
the power amplifiers. When the DC balance of the
power stage is lost for some reason, a potential
difference is produced in the input signal to the
differential amplifier, and the collector currents of
Q5 and QG are put out of balance. Thus, the relay
driving circuit functions, and the relay switch is
turned off.
Glx-g4slA
Fig.23
Fig.24
Fis.25
Power
Amplifier
Relay driving circuit
Relay driving circuit
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Fis.26