QMTECH XC7A35T SDRAM User manual

QM_XC7A35T_SDRAM Core Board User Manual V02
QM_XC7A35T_SDRAM CORE BOARD
USER MANUAL
Preface
The QMTech®XC7A35T SDRAM core board uses Xilinx Artix®-7 devices to demonstrate the highest
performance-per-watt fabric, transceiver line rates, DSP processing, and AMS integration in a cost-
optimized FPGA. Featuring the MicroBlaze™ soft processor and 1,066Mb/s DDR3 support, the family is the
best value for a variety of cost and power-sensitive applications including software-defined radio, machine
vision cameras, and low-end wireless backhaul.

QM_XC7A35T_SDRAM Core Board User Manual V02
Table of Contents
1. INTRODUCTION .................................................................................. 3
1.1 DOCUMENT SCOPE ..................................................................... 3
1.2 KIT OVERVIEW........................................................................... 3
2. GETTING STARTED .............................................................................. 4
2.1 INSTALL DEVELOPMENT TOOLS ...................................................... 5
2.2 QM_XC7A35T_SDRAM HARDWARE DESIGN................................ 6
2.2.1 QM_XC7A35T_SDRAM Power Supply......................... 6
2.2.2 QM_XC7A35T_SDRAM SPI Boot................................. 7
2.2.3 QM_XC7A35T_SDRAM Memory................................. 8
2.2.4 QM_XC7A35T_SDRAM System Clock.......................... 8
2.2.5 QM_XC7A35T_SDRAM Extension IO .......................... 9
2.2.1 QM_XC7A35T_SDRAM 3.3V Power Supply............... 10
2.2.2 QM_XC7A35T_SDRAM JTAG Port............................. 10
2.2.3 QM_XC7A35T_SDRAM User LED .............................. 10
2.2.4 QM_XC7A35T_SDRAM User Key .............................. 11
3. REFERENCE........................................................................................ 12
4. REVISION .......................................................................................... 13

QM_XC7A35T_SDRAM Core Board User Manual V02
1. Introduction
1.1 Document Scope
This demo user manual introduces the QM_XC7A35T_SDRAM core board and describes how to setup
the core board running with application software Xilinx Vivado 2016.4. Users may employee the on board
rich logic resource FPGA XC7A35T-1FTG256C and large SDRAM memory MT48LC16M16 to implement
various applications. The core board also has 108 non-multiplexed FPGA IOs for extending customized
modules, such as UART module, CMOS/CCD camera module, LCD/HDMI/VGA display module etc.
1.2 Kit Overview
Below section lists the parameters of the QM_XC7A35T_SDRAM core board:
On-Board FPGA: XC7A35T-1FTG256C;
On-Board FPGA external crystal frequency: 50MHz;
XC7A35T-1FTG256C has rich block RAM resource up to 1,800Kb;
XC7A35T-1FTG256C has 33,280 logic cells;
On-Board N25Q064 SPI Flash，8M bytes for user configuration code;
On-Board 32MB Micron SDRAM，MT48LC16M16A2-75;
On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC;
XC7A35T development board has two 64p, 2.54mm pitch headers for extending user IOs. All IOs are
precisely designed with length matching;
XC7A35T development board has 2 user switches;
XC7A35T development board has 3 user LEDs;
XC7A35T development board has JTAG interface, by using 6p, 2.54mm pitch header;
XC7A35T development board PCB size is: 6.7cm x 8.4cm;
Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm;
Figure 1-1. QM_XC7A35T_SDRAM Core Board Overview

QM_XC7A35T_SDRAM Core Board User Manual V02
2. Getting Started
The QM_XCA35T_SDRAM core board includes below item:
Figure 2-1. QM_XC7A35T_SDRAM Top View
Below image shows the dimension of the QM_XC7A35T_SDRAM core board: 6.7cm x 8.4cm. The unit in
below image is millimeter(mm).
Figure 2-2. QM_XC7A35T_SDRAM Core Board Dimension

QM_XC7A35T_SDRAM Core Board User Manual V02
2.1 Install Development Tools
The QM_XC7A35T_SDRAM core board tool chain consists of Xilinx Vivado 2016.4, Xilinx USB platform cable,
XC7A35T core board and 5V DC power supply. Below image shows the Xilinx Vivado 2016.4 development
environment which could be downloaded from Xilinx office website:
Figure 2-3. Vivado 2016.4
Below image shows the JTAG connection between Xilinx USB platform cable and XC7A35T core board:
Figure 2-4. JTAG Connection and Power Supply
TMS (Green)
TDI (Purple)
TDO (White)
TCK (Yellow)
GND (Black)
VREF (Red)
5V DC

QM_XC7A35T_SDRAM Core Board User Manual V02
2.2 QM_XC7A35T_SDRAM Hardware Design
2.2.1 QM_XC7A35T_SDRAM Power Supply
The core board needs 5V DC input as power supply which could be directly injected from power header or the 64P
female header U7/U8. Users may refer to the hardware schematic for the detailed design. The on board LED D4
indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In default status, all the FPGA banks
IO power level is 3.3V because bank power supply is 3.3V. However, BANK34 and BANK35 IO’s power level could be
changed according to detailed custom requirement. There’re three 0 ohm resisters could be removed: R223/R224/
R225, and instead the BANK34 and BANK35’s power supply could be injected from 64P female header U8. Detailed
design refer to hardware schematic.
Note: FPGA core supply 1.0V is regulated by On-Semi DC/DC chip NCP1529 which could output maximum 1A
current.
Figure 2-5. Power Supply for the FPGA
3V3
1V8
C22
100NF
C20
100NF
C21
100NF
C19
100NF
1V0
C18
10V
4.7uF
C35
10V
4.7uF
C37
100NF
C36
100NF
3V3
1V0
C74
10V
4.7uF
C76
100NF
C75
100NF
VCCO_34_35
C61
10V
4.7uF
C62
100NF
XADC is not used!
C63
100NF
C28
100NF
C29
100NF
C53
10V
4.7uF
3V3
VCCO_34_35
1V8
C77
10V
4.7uF
1V8
C78
100NF
C79
100NF
XC7A35T-FTG256
U9F
GND_30
A1 GND_29
A11 GND_28
B8 GND_27
C5 GND_26
C15 GND_25
D2 GND_24
D12 GND_23
E9 GND_22
F6 GND_21
F10 GND_20
F16 GND_19
G3 GND_18
G9 GND_17
G13 GND_16
H6 GND_15
J9 GND_14
J11 GND_13
K4 GND_12
K6 GND_11
K14 GND_9
L1 GND_8
L11 GND_7
M8 GND_6
N5 GND_5
N15 GND_4
P2 GND_3
P12 GND_2
R9 GND_1
T6 GND_0
T16
VCCINT_0 F7
VCCINT_1 F9
VCCINT_2 G6
VCCINT_3 H9
VCCINT_4 J6
VCCINT_5 K9
VCCINT_6 L8
VCCAUX_3
G10 VCCAUX_2
J10 VCCAUX_1
K11 VCCAUX_0
L10 VCCO_0 L6
VCCO_14_0 L16
VCCO_14_1 M13
VCCO_14_2 N10
VCCO_14_3 P7
VCCO_14_4 R14
VCCO_14_5 T11
VCCO_15_0 A16
VCCO_15_1 B13
VCCO_15_2 C10
VCCO_15_3 E14
VCCO_15_4 H15
VCCO_15_5 J12
VCCO_34_0 M3
VCCO_34_1 R4
VCCO_34_2 T1
VCCO_35_0 A6
VCCO_35_1 B3
VCCO_35_2 D7
VCCO_35_3 E4
VCCO_35_4 F1
VCCO_35_5 J2
VCCBRAM_0 E10
VCCBRAM_1 F11
GNDADC_0
G7
VCCADC_0
G8
VREFP_0
J8
VN_0
J7
VCCBATT_0 F8
VREFN_0
H7
VP_0
H8
CFGBVS_0 E7
3V3
1V8

QM_XC7A35T_SDRAM Core Board User Manual V02
2.2.2 QM_XC7A35T_SDRAM SPI Boot
In default, QM_XC7A35T boots from external SPI Flash, detailed hardware design is shown in below figure.
The SPI flash is using N25Q064 manufactured by Micron, with 64Mbit memory storage.
Figure 2-6. SPI Flash
The FPGA boot sequence setting M0:M1:M2 is configured as 1:0:0 which indicates FPGA will boot from SPI
Flash after power on. In default, the jumper J1 is under closed status.
Figure 2-7. M0:M1 Hardware Settings
The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during
power on stage. In this case, LED D2 could be used as FPGA loading status indicator.
Figure 2-8. FPGA_DONE Status Indicator
FPGA_DQ1 FPGA_DQ3
FPGA_CCLK
FPGA_DQ0
FPGA_DQ2
U2
N25Q064A13ESE40F
nCE
1
SIO3 7 SO/SIO1
2
VSS
4SI/SIO0 5
SCK 6 SIO2
3
VDD 8
C33
100nF
3V3
R154.7K FPGA_CSO_B
3V3
R2334.7K
R2344.7K
TMS
TCK
TDI
TDO
FPGA_DONE
PROG_B
R229 4.7K 3V3
R230 1K 3V3
XC7A35T-FTG256
U9A
DONE_0 H10
DXP_0 K8
TCK_0 L7
DXN_0 K7
M0_0 M9
M1_0 M10
INIT_B_0 K10
TDI_0 N7
TDO_0 N8
M2_0 M11
PROGRAM_B_0 L9
TMS_0 M7
3V3
R231 1K
J1
R13
1K
D2
Red
1
2
3V3
R25
1K
FPGA_DONE

QM_XC7A35T_SDRAM Core Board User Manual V02
2.2.3 QM_XC7A35T_SDRAM Memory
QM_XC7A35T has on board 16bit width data bus, 32MB memory size SDRAM MT48LC16M16 provided by
Micron. Below image shows the detailed hardware design:
Figure 2-9. SDRAM
2.2.4 QM_XC7A35T_SDRAM System Clock
FPGA chip XC7A35T-1FTG256C has system clock frequency 50MHz which is directly provided by external
crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/°c. Below
image shows the detailed hardware design:
Figure 2-10. 50MHz System Clock
DQML
A8
A9
SD_NCS0
A13
D2
A6
D4
A11
A4
D10
A14
CAS
A1
D5
D12
D15
D9
D14
C4
100NF
SDCLK0
C7
100NF
C8
100NF
C9
100NF
C6
100NF
C5
100NF
MT48LC16M16A2
MN1
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38 CKE
37
DQML
15
DQMH
39
CAS
17
RAS
18
WE
16
CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
A12
DQMH
3V3
D3
RAS
SDCKE0
D6
A7
D0
256 M bit s
A10
D7
SDWE
A3
D8
A0
A2
D13
D1
D11
A5
C42
100NF
50 MHz
VDD
VSS OUT
OE
Y1
SG-8002JC-50.0000M-PCB
41
32 SYS_CLK
R9 4.7K
3V3

QM_XC7A35T_SDRAM Core Board User Manual V02
2.2.5 QM_XC7A35T_SDRAM Extension IO
The core board has two 64P 2.54mm pitch female headers which are used for extending user modules,
such as ADC/DAC module, audio/video module, ethernet module, etc.
Figure 2-11. Extension IO
BANK35_K3
BANK35_J3 BANK35_K2
BANK35_H3
BANK35_A7
BANK35_B5
BANK35_B7
BANK35_B6
U8
HDR_32X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
BANK35_H4BANK35_H5
VCCO_34_35
BANK35_F2
BANK35_A5
BANK35_L3
BANK35_K1
BANK35_H2
BANK35_G2
BANK35_F4
BANK35_D4
BANK35_B2
BANK35_C3
BANK35_D6
BANK35_B4
BANK35_F5
BANK35_E3
BANK35_E2
BANK35_C1
VCCO_34_35
BANK35_F3
BANK35_E1
BANK35_A3
BANK35_A4
BANK35_L2
BANK35_J1
BANK35_H1
BANK35_G1
BANK35_B1
BANK35_C4
BANK35_A2
BANK35_C2
BANK35_D5
BANK35_E5
BANK35_D3
BANK35_D1
BANK35_K5BANK35_E6
BANK35_C6BANK35_C7 BANK35_G4BANK35_G5
BANK35_J5 BANK35_J4
BANK34_L4 BANK34_M4
BANK34_N3 BANK34_N2
5V_IN 5V_IN
BANK14_M12
BANK14_N9
BANK14_P10 BANK14_P11
BANK14_T13 BANK14_R12 BANK14_R13
BANK14_T15BANK14_T14 BANK14_P14
BANK14_T12
BANK14_N14 BANK14_N16
BANK14_P16BANK14_P15 BANK14_R16BANK14_R15
BANK14_N13
BANK14_K12 BANK14_K13
5V_IN5V_IN
3V33V3
BANK34_M2 BANK34_M1
BANK34_N1 BANK34_P1
BANK34_P4
BANK34_M5 BANK34_N4
BANK34_P3
BANK34_R2 BANK34_R1
BANK34_R3 BANK34_T2
BANK34_T3BANK34_T4
BANK34_L5 BANK34_P5
BANK14_N6
U7
HDR_32X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
BANK14_R5
BANK14_T5 BANK14_R6
BANK14_T7 BANK14_R7
BANK14_T8
BANK14_M6
BANK14_R8
BANK14_P6
BANK14_P9
BANK14_T9
BANK14_N12
BANK14_M16
BANK14_T10
BANK14_P13
BANK14_R11
BANK14_R10
BANK34/35 Voltage
Supply Pins.
Connected to 5V_IN
power header.
Connected to 5V_IN
power header.

QM_XC7A35T_SDRAM Core Board User Manual V02
2.2.1 QM_XC7A35T_SDRAM 3.3V Power Supply
The core board’s 3.3V power supply is using high efficiency DC/DC chip MP2359 provided by MPS Inc. The
MP2359 supports wide voltage input range from 4.5V to 24V. In normal use case, 5V DC power supply is
suggested to be applied on the board. Below image shows the MP2359 hardware design:
Figure 2-12. MP2359 Hardware Design
2.2.2 QM_XC7A35T_SDRAM JTAG Port
The on board JTAG port uses 6P 2.54mm pitch header which could be easily connected to Xilinx USB platform
cable. Below image shows the hardware design of the JTAG port:
Figure 2-13. JTAG Port
2.2.3 QM_XC7A35T_SDRAM User LED
Below image shows one user LED and 3.3V power supply indicator:
Figure 2-14. LEDs
REGULATED
C67 10nF
5V O NLY
+C58
47uF
R126
100K
R127
DNP
D5
IN5819
12
L6
4.7uH
R128
100K
R129
33K
C60
DNP
C68
100nF
U4
MP2359
BST
1
GND
2
FB
3EN 4
VIN 5
SW 6
JP5
Power_Header_SMT
1
2
3
4
3V3
5V_IN
C69
4.7uF
VCCO_34_35
R223 0R
R224 0R
R225 0R
J2
JTAG
1
2
3
4
5
6
TCK
TMS
TDI
TDO
3V3
3V3
D4
1 2
R131
1K
D3
1 2
R218
1K
3V3
BANK15_C8

QM_XC7A35T_SDRAM Core Board User Manual V02
2.2.4 QM_XC7A35T_SDRAM User Key
Below image shows the PROGRAM_B key and one user key:
Figure 2-15. Keys
3V3
SW1
1
2
PROG_B
SW2
1
2
BANK15_A8
R221
4.7k
R228
4.7k
3V3

QM_XC7A35T_SDRAM Core Board User Manual V02
3. Reference
[1] ug470_7Series_Config.pdf
[2] ds181_Artix_7_Data_Sheet.pdf
[3] ug475_7Series_Pkg_Pinout.pdf
[4] n25q_64a_3v_65nm.pdf
[5] MT48LC16M16.pdf
[6] MP2359.pdf
[7] NCP1529-D.PDF

QM_XC7A35T_SDRAM Core Board User Manual V02
4. Revision
Doc. Rev.
Date
Comments
0.1
05/10/2017
Initial Version.
1.0
05/14/2017
V1.0 Formal Release.
2.0
18/02/2018
Update PCB color to black.