QMTECH XILINX SPARTAN-7 User manual

QM_Spartan-7 Development Board User Manual V01
XILINX SPARTAN-7 CORE BOARD
USER MANUAL
Preface
The QMTech® Spartan-7 Core Board uses Xilinx XC7S15 device to demonstrate the newest
addition to the Cost-Optimized Portfolio, offer the best in class performance per watt, along
with small form factor packaging to meet the most stringent requirements. These devices
feature a MicroBlaze™ soft processor running over 200 DMIPs with 800Mb/s DDR3 support
built on 28nm technology. Additionally, Spartan-7 devices offer an integrated ADC, dedicated
security features, and Q-grade (-40 to +125°C) on all commercial devices. These devices are
ideally suited for industrial, consumer, and automotive applications including any-to-any
connectivity, sensor fusion, and embedded vision.

QM_Spartan-7 Development Board User Manual V01
Table of Contents
1. INTRODUCTION .................................................................................. 3
1.1 DOCUMENT SCOPE..................................................................... 3
1.2 KIT OVERVIEW...........................................................................3
2. GETTING STARTED ..............................................................................4
2.1 INSTALL DEVELOPMENT TOOLS......................................................4
2.2 QM_SPARTAN-7 HARDWARE DESIGN ............................................7
2.2.1 QM_Spartan-7 Power Supply ..................................... 7
2.2.1 QM_Spartan-7 3.3V Power Supply ............................. 8
2.2.2 QM_Spartan-7 SPI Boot ............................................. 9
2.2.3 QM_Spartan-7 System Clock.................................... 10
2.2.4 QM_Spartan-7 JTAG Port......................................... 10
2.2.5 QM_Spartan-7 User LED .......................................... 10
2.2.6 QM_Spartan-7 Extension IO..................................... 11
2.2.7 QM_Spartan-7 User Key .......................................... 12
2.2.8 QM_Spartan-7 UART Port ........................................ 13
3. REFERENCE........................................................................................ 14
4. REVISION ..........................................................................................15

QM_Spartan-7 Development Board User Manual V01
1. Introduction
1.1 Document Scope
This demo user manual introduces the QM_Spartan-7 development board and describes how to setup
the development board running with application software Xilinx Vivado 2018.2. Users may employee the
on board rich logic resource FPGA XC7S15-1FTGB196C to implement various applications. The
development board has 88 non-multiplexed FPGA IOs for extending customized modules, such as UART
module, CMOS/CCD camera module, LCD/HDMI/VGA display module etc.
1.2 Kit Overview
Below section lists the parameters of the QM_Spartan-7 development board:
On-Board FPGA: XC7S15-1FTGB196C;
On-Board FPGA external crystal frequency: 50MHz;
XC7S15-1FTGB196C has rich block RAM resource up to 360Kb;
XC7S15-1FTGB196C has 12,800 logic cells;
On-Board N25Q064 SPI Flash, 8M bytes for user configuration code;
On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC;
QM_Spartan-7 development board has two 50p, 2.54mm pitch headers for extending user IOs. All
IOs are precisely designed with length matching;
QM_Spartan-7 development board has 3 user switches;
QM_Spartan-7 development board has 4 user LEDs;
QM_Spartan-7 development board has JTAG interface, by using 6p, 2.54mm pitch header;
QM_Spartan-7 development board has USB to UART Serial Port, by using Silicon Labs’ CP2102-
GMR chip.
QM_Spartan-7 development board PCB size is: 6.6cm x 5.7cm;
Default power source for board is from Mini USB: 1A@5V DC;
Figure 1-1. QM_Spartan-7 Development Board Overview

QM_Spartan-7 Development Board User Manual V01
2. Getting Started
Below image shows the dimension of the QM_Spartan-7 development board: 6.6cm x 5.7cm. The unit in
below image is millimeter(mm).
Figure 2-1. QM_Spartan-7 Development Board Dimension
2.1 Install Development Tools
The QM_Spartan-7 development board tool chain consists of Xilinx Vivado 2018.2, Xilinx USB platform cable,
Mini USB cable for power supply. Below image shows the Xilinx Vivado 2018.2 development environment
which could be downloaded from Xilinx office website:
Figure 2-2. Vivado 2018.2

QM_Spartan-7 Development Board User Manual V01
Below image shows the JTAG connection between Xilinx USB platform cable and QM_Spartan-7 development
board:
Figure 2-3. JTAG Connection and Power Supply
Once the FPGA test program is correctly 【Synthesized】, 【Implemented】and 【Generated with
Bitstream】, users may click the 【Open Target】option to connect the XC7S15 FPGA.
Figure 2-4. Vivado to Connect FPGA
TMS (Green)
TDI (Purple)
TDO (White)
TCK (Yellow)
GND (Black)
VREF (Red)
5V DC
Step1
Step2
Step3
Step4

QM_Spartan-7 Development Board User Manual V01
Chip info like xc7s15_0(1) is shown in Hardware Manager as below image. Users then could right click the
device to choose 【Program Device】to load the Bitstream *.bit into FPGA or to choose【Add Configuration
Memory Device】to program the *.mcs file into on-board SPI flash.
Figure 2-5. Program FPGA
Users could convert the *.bit file into the *.mcs file by using the Vivado tool. Choose the 【Tools】on the menu
bar and then select 【Generate Memory Configuration File】, and then configure the parameters shown in
below image:
Figure 2-6. Generate *.mcs File

QM_Spartan-7 Development Board User Manual V01
2.2 QM_Spartan-7 Hardware Design
2.2.1 QM_Spartan-7 Power Supply
The development board needs 5V DC input as power supply which could be directly injected from JP1/JP2
header or the Mini USB connector. Users may refer to the hardware schematic for the detailed design. The on
board LED D5 indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In default
status, all the FPGA banks IO power level is 3.3V because bank power supply is 3.3V. Detailed design refer to
hardware schematic.
Note: FPGA core supply 1.0V is regulated by On-Semi DC/DC chip NCP1529 which could output maximum 1A
current.
Figure 2-7. Power Supply for the FPGA
3V3
1V0
1V0
1V8
XC7S15-1FTGB196
U1D
VCCAUX_1 F10
VCCAUX_2 H10
VCCAUX_3 K10
VCCAUX_4 L9
VCCINT_1 D6
VCCINT_2 D8
VCCINT_3 E7
VCCINT_4 E9
VCCINT_5 F6
VCCINT_6 G9
VCCINT_7 H6
VCCINT_8 J9
VCCINT_9 K6
VCCINT_10 K8
VCCO_0_1
N6
VCCO_0_2
N8
VCCO_14_1
G13
VCCO_14_2
K13
VCCO_14_3
N13
VCCO_14_4
G2
VCCO_14_5
K2
VCCO_14_6
N2
VCCBRAM_1
E5
VCCBRAM_2
G5
VCCBRAM_3
J5
XC7S15-1FTGB196
U1E
GND_1 A1
GND_2 A6
GND_3 A9
GND_4 A11
GND_5 A14
GND_6 B4
GND_7 B7
GND_8 B9
GND_9 C2
GND_10 C6
GND_11 C7
GND_12 C8
GND_13 C9
GND_14 C13
GND_15 D5
GND_16 D7
GND_17 D9
GND_18 D11
GND_19 E1
GND_20 E3
GND_21 E6
GND_22 E8
GND_23 E10
GND_24 E14
GND_25 F5
GND_26 F9
GND_27 G3
GND_28 G6
GND_29 G10
GND_30 G12
GND_31 H5
GND_32 H9
GND_33 J6
GND_34 J10
GND_35 K1
GND_36 K5
GND_37 K7
GND_38 K9
GND_39 K14
GND_40 L4
GND_41 L6
GND_42 L8
GND_43 L10
GND_44 L11
GND_45 N3
GND_46 N5
GND_47 N9
GND_48 N12
GND_49 P1
GND_50 P14

QM_Spartan-7 Development Board User Manual V01
2.2.1 QM_Spartan-7 3.3V Power Supply
The development board’s 3.3V power supply is using high efficiency DC/DC chip MP2359 provided by MPS
Inc. The MP2359 supports wide voltage input range from 4.5V to 24V. In normal use case, 5V DC power
supply is suggested to be applied on the board. Below image shows the MP2359 hardware design:
Figure 2-8. MP2359 Hardware Design
Figure 2-9. 1.0V Core Voltage DC/DC
R1
100K
R3
33K
C5
100nF
U2
MP2359
BST
1
GND
2
FB
3EN 4
VIN 5
SW 6
C2
4.7uF
3V3
C4
4.7uF
C3
4.7uF
USB_5V
C1 10nF
R2 100K
L1
4.7uH
D1
IN5819
12
C17
4.7uF
L3 4.7uH 1V0
C13
4.7uF
3V3
U5
NCP1529
GND
2
FB 5 EN
1
VIN
4SW 3R7
100K C11 22pF
R8
150K
M
1V
C12
4.7uF
C16
4.7uF
C8
4.7uF
1V8
L2 4.7uH
3V3
C9
4.7uF
U4
NCP1529
GND
2
FB 5 EN
1
VIN
4SW 3R5
53.6K C7 22pF
M
1V8
R6
27K

QM_Spartan-7 Development Board User Manual V01
Figure 2-10. 1.8V AUX Voltage DC/DC
2.2.2 QM_Spartan-7 SPI Boot
In default, XC7S15 boots from external SPI Flash, detailed hardware design is shown in below figure. The SPI
flash is using N25Q064 manufactured by Micron, with 64Mbit memory storage.
Figure 2-11. SPI Flash
The FPGA boot sequence setting M0:M1:M2 is configured as 1:0:0 which indicates FPGA will boot from SPI
Flash after power on. In default, the jumper J3 is under open status.
Figure 2-12. M0:M1 Hardware Settings
The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during
power on stage. In this case, LED D2 could be used as FPGA loading status indicator.
FPGA_DQ3
FPGA_DQ0
FPGA_DQ2
FPGA_DQ1
U6
N25Q064A13ESE40F
nCE
1
SIO3 7 SO/SIO1
2
VSS
4SI/SIO0 5
SCK 6 SIO2
3
VDD 8
C14
100nF
3V3
FPGA_CSO_B
R104.7K
3V3
R124.7K
R134.7K FPGA_CCLK
TDI
TMS
TDO
TCK
FPGA_DONE
3V3 3V3
R22 1K
J3
R23 1K 3V3
3V3
R21 4.7K
PROG_B FPGA_CCLK
XC7S15-1FTGB196
U1A
DONE_0 P9
TCK_0
A7
CCLK_0 A8
M0_0 M7
M1_0 M8
INIT_B_0 P8
TDI_0
P7
TDO_0
P6
M2_0 M9
CFGBVS_0
N7
PROGRAM_B_0 L7
TMS_0
M6
DXP_0
J8 DXN_0
J7
NC_1
F7
NC_2
F8
NC_3
B8
NC_4
G7
NC_5
G8
NC_6
H7
NC_7
H8
R14
1K
3V3
R20
1K
D2
Red
1
2
FPGA_DONE

QM_Spartan-7 Development Board User Manual V01
Figure 2-13. FPGA_DONE Status Indicator
2.2.3 QM_Spartan-7 System Clock
FPGA chip XC7S15-1FTGB196C has system clock frequency 50MHz which is directly provided by external
crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/°c. Below
image shows the detailed hardware design:
Figure 2-14. 50MHz System Clock
2.2.4 QM_Spartan-7 JTAG Port
The on board JTAG port uses 6P 2.54mm pitch header which could be easily connected to Xilinx USB platform
cable. Below image shows the hardware design of the JTAG port:
Figure 2-15. JTAG Port
2.2.5 QM_Spartan-7 User LED
Below image shows two user LEDs and one LED for 3.3V power supply indicator:
CLK_50M
50 MHz
VDD
VSS OUT
OE
Y1
SG-8002JC-50.0000M-PCB
41
32
C15
100NF
3V3
R11 4.7K
J2
JTAG
1
2
3
4
5
6
TCK
3V3
TMS
TDI
TDO

QM_Spartan-7 Development Board User Manual V01
Figure 2-16. LEDs
2.2.6 QM_Spartan-7 Extension IO
The development board has two 50P 2.54mm pitch headers which are used for extending user modules,
such as ADC/DAC module, audio/video module, ethernet module, etc.
3V3
R18
1K
D5
1 2
D3
1 2
R19
1K
3V3
LED_D3
D4
1 2
R24
1K
LED_D4
3V3

QM_Spartan-7 Development Board User Manual V01
Figure 2-17. Extension IO
2.2.7 QM_Spartan-7 User Key
Below image shows the PROGRAM_B key and two user keys:
IO_C12 IO_E11
IO_M10IO_H12
IO_A10
IO_N11 IO_N10
IO_P11 IO_P10
IO_B10
IO_L13IO_L12
IO_P13 IO_P12
IO_M12 IO_M11
IO_K12 IO_N14IO_M14 IO_M13IO_L14
IO_J14IO_J13 IO_J12IO_J11 IO_K11
IO_F14IO_G14 IO_F11IO_G11 IO_H14IO_H13
IO_D14 IO_E12IO_F12 IO_E13IO_F13
JP1
HDR_25X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
IO_B13IO_B14 IO_D12IO_D13 IO_C14
IO_A12IO_A13
JP2
HDR_25X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
USB_5V
USB_5V 3V3
3V3
IO_A2IO_B3
IO_A4 IO_A3
IO_A5 IO_B5
IO_C3 IO_D3
IO_P4
IO_M4IO_M5 IO_N1IO_P2 IO_P3
IO_L3 IO_L2
IO_L1IO_M1 IO_M2IO_M3
IO_J2 IO_J3IO_J4 IO_K3IO_K4
IO_H2IO_H1 IO_H4IO_H3 IO_J1
IO_G1IO_F1 IO_F2IO_F3 IO_G4IO_F4
IO_B2 IO_E2IO_D2 IO_D1IO_C1 IO_B1
IO_D4 IO_E4

QM_Spartan-7 Development Board User Manual V01
Figure 2-18. Keys
2.2.8 QM_Spartan-7 UART Port
The CP2102-GMR is a USB 2.0 to serial port bridge chip designed by Silicon Labs. The CP2102-GMR includes
a USB 2.0 full-speed function controller, USB transceiver, oscillator, UART and eliminates the need for other
external USB components are required for development. Below figure shows the hardware design of CP2102-
GMR on the QM_Spartan-7.
Figure 2-19. UART Port
KEY0
SW2
1
2
nRESET
3V3
R16
4.7k
SW1
1
2
SW3
1
2
PROG_B
R17
4.7K
3V3
3V3
R15
4.7k
PIN_RX
PIN_TX
C10
4.7uF
R4 4.7K
U3
CP2102-GM
DCD 1
RI 2
GND
3
D+
4D-
5
VDD
6
REGIN
7VBUS
8
RST 9
NC1
10
SUSPEND 11
SUSPEND 12
NC2
13
CTS 23
RTS 24
RXD 25
TXD 26
DSR 27
DTR 28
NC3
14
NC4
15
NC5
16
NC6
17 NC7 18
NC8 19 NC9 20
NC10 21 NC11 22
GND_TP
29
J1
MINI_USB
Vcc 1
D- 2
D+ 3
ID 4
GND 5
G3
8G4
9
G2
7
G1
6
USB_5V
C6
100nF

QM_Spartan-7 Development Board User Manual V01
3. Reference
[1] ug470_7Series_Config.pdf
[2] ds181_Artix_7_Data_Sheet.pdf
[3] ug475_7Series_Pkg_Pinout.pdf
[4] n25q_64a_3v_65nm.pdf
[5] MP2359.pdf
[6] NCP1529-D.PDF

QM_Spartan-7 Development Board User Manual V01
4. Revision
Doc. Rev.
Date
Comments
0.1
05/12/2018
Initial Version.
1.0
05/12/2018
V1.0 Formal Release.