Qorivva MPC5 Series User manual

Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 1
©1989-2021 Lauterbach GmbH
Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ...................................................................................................................... 
ICD In-Circuit Debugger ................................................................................................................ 
Processor Architecture Manuals .............................................................................................. 
Qorivva MPC5xxx/SPC5xx ...................................................................................................... 
Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace ................................................. 1
Introduction ....................................................................................................................... 8
Available Tools 8
JTAG/OnCE Debugger 8
On-chip Trace 9
High-Speed Serial Off-chip Trace (Aurora NEXUS) 9
Parallel Off-chip Trace (parallel NEXUS) 10
Co-Processor Debugging (eTPU/GTM/SPT) 10
Multicore Debugging 10
Software-only Debugging (HostMCI) via XCP 10
Software Installation 11
Hardware Installation 12
JTAG Debugger 12
Parallel Nexus Debugger and Trace 13
Aurora Nexus Debugger and Trace 14
ESD Protection Considerations 15
Demo and Start-up Scripts 15
Debug Cable / Nexus Adapter Versions and Detection 16
Brief Overview of Documents for New Users 17
Target Design Requirement/Recommendations ............................................................ 18
General (ICD Debugger) 18
Quick Start ......................................................................................................................... 19
Run Program from On-chip SRAM 19
Run Program from FLASH 21
Connect to Running Program (hot plug-in) 22
FAQ ..................................................................................................................................... 23
Debugging .......................................................................................................................... 24
Breakpoints 24
Software Breakpoints 24

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On-chip Breakpoints 24
Breakpoints on Program Addresses 25
Breakpoints on Data Addresses 26
Breakpoints on Data Access at Program Address 27
Breakpoints on Data Value 27
Counting Debug Events with Core Performance Monitor 28
Memory Access 29
Access Classes 29
Access Classes to Memory and Memory Mapped Resources 29
Access Classes to Other Addressable Core and Peripheral Resources 30
Cache Debugging Support 32
Memory Coherency 32
Memory Coherency During run-time Memory Access 32
Viewing Cache Contents 33
MESI States and Cache Status Flags 34
Using Cache Lines as SRAM Extension 34
Support for Peripheral Modules 35
Displaying Peripheral Module Registers 35
Peripheral Registers Modified by TRACE32 36
Debugging and Tracing Through Reset 37
Multicore Debugging 39
SMP Debugging 40
AMP Debugging 41
Watchdog Timer Support 42
e200 Core Watchdog (TCR/TSR) 42
On-chip Watchdog (SWT) 42
Chip External Watchdog 43
Censorship Unlock 44
Censorship unlock on MPC56XX and SPC56X processors 44
Censorship unlock on MPC57XX, SPC57X/SPC58X and S32R processors 44
Recovering a censored processor (MPC57XX, SPC57X/SPC58X and S32R) 46
Non-secure boot (S32R294) 48
Non-secure boot by script 48
Non-secure boot if fuses blown 48
Troubleshooting Debug 49
Tracing ............................................................................................................................... 51
e200 PCFIFO On-chip Trace 51
MPC57XX/SPC57X/SPC58X NEXUS On-chip Trace (trace-to-memory) 51
External Trace Ports (Parallel NEXUS/Aurora NEXUS) 53
Basic Setup for Parallel Nexus 53
Basic Setup for Aurora Nexus 53
Tracing the Program Flow 54
Tracing of Data (read/write) Transactions 55

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Example: Data Trace with Address Range 55
Tracing of Context Switches 55
Trace Context Switches using Data Trace Messaging (DTM) 55
Trace Context Switch using Ownership Trace Messaging (OTM) 56
Trace Based Run-time Measurement / Timestamping 56
Trace Based Run-time Measurement for off-chip Parallel NEXUS 57
Trace Based Run-time Measurement for off-chip Aurora NEXUS 57
Trace Based Run-time Measurement for on-chip Trace / Trace-to-memory 57
Correlation of the Trace Timestamp with Other Tool Timestamps 58
Implications of Using the Processor Generated Timestamps 58
Processors with on-chip timestamp support 59
Trace Filtering and Triggering with Debug Events 59
Overview 59
Example: Selective Program Tracing 61
Example: Event Controlled Program/Data Trace Start and End 62
Example: Event Controlled Trace Recording 63
Example: Event Controlled Trigger Signals 63
Example: Event Counter 64
Tracing Peripheral Modules / Bus Masters 64
Example: Filter by Address Range 64
Example: Event Controlled Trace Start and End 64
Trace Filtering and Triggering Features Provided by TRACE32 65
Troubleshooting Trace 65
Tracing VLE or Mixed FLE/VLE Applications 65
FLASH Programming Support ......................................................................................... 67
FLASH Programming Scripts 67
Requirements due to FLASH ECC Protection 69
Programming the RCHW or Boot Header 70
Programming the Shadow Row 70
Programming Serial Boot Password and Censorship Word 72
TEST / UTEST / OTP FLASH Programming 73
Programming an OTP Sector 73
Programming an UTEST Sector which is not set to OTP 74
Brownout Depletion Recovery 75
Troubleshooting FLASH 75
Command Reference: SYStem Commands .................................................................... 77
SYStem.BdmClock Set BDM clock frequency 77
SYStem.CONFIG.state Display target configuration 78
SYStem.CONFIG Configure debugger according to target topology 79
SYStem.CONFIG.DEBUGPORTTYPE Set debug cable interface mode 84
Hardware Requirements for cJTAG Operation 84
SYStem.CONFIG.EXTWDTDIS Disable external watchdog 85
SYStem.CONFIG PortSHaRing Control sharing of debug port with other tool 86

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SYStem.CPU Select the target processor 86
SYStem.LOCK Lock and tristate the debug port 87
SYStem.MemAccess Run-time memory access (non-intrusive) 87
SYStem.Mode Select operation mode 89
Command Reference: SYStem.Option Commands ....................................................... 90
SYStem.Option BISTRUN Debug with BIST enabled 90
SYStem.Option CoreStandBy On-the-fly breakpoint and trace setup 90
SYStem.Option DCFREEZE Data cache state frozen while core halted 90
SYStem.Option DCREAD Read from data cache 91
SYStem.Option DISableResetEscalation Control reset escalation disabling 91
SYStem.Option DISableShortSequence Short reset sequence handling 92
SYStem.Option DisMode Disassembler operation mode 92
SYStem.Option DUALPORT Implicitly use run-time memory access 93
SYStem.Option FASTACCESS Special operation mode for fast run control 94
SYStem.Option FREEZE Freeze system timers on debug events 94
SYStem.Option HoldReset Set reset hold time 95
SYStem.Option ICFLUSH Invalidate instruction cache before go and step 95
SYStem.Option ICREAD Read from instruction cache 95
SYStem.Option IMASKASM Disable interrupts while single stepping 96
SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 96
SYStem.Option KEYCODE Inhibit censorship protection 96
SYStem.Option LPMDebug Enable low power mode debug handshake 98
SYStem.Option LockStepDebug Enable lock-step core register access 99
SYStem.Option MMUSPACES Separate address spaces by space IDs 99
SYStem.Option NexusMemoryCoherency Coherent NEXUS mem-access 100
SYStem.Option NoDebugStop Disable JTAG stop on debug events 101
SYStem.Option NoJtagRdy Do not evaluate JTAG_RDY signal 101
SYStem.Option NOTRAP Use brkpt instruction for software breakpoints 102
SYStem.Option OVERLAY Enable overlay support 103
SYStem.Option PC Set fetch address debug actions 103
SYStem.Option RESetBehavior Set behavior when target reset detected 104
SYStem.Option ResBreak Halt the core while reset asserted 104
SYStem.Option ResetDetection Configure reset detection method 105
SYStem.Option ResetMode Select reset mode for SYStem.Up 106
SYStem.Option SLOWRESET Relaxed reset timing 107
SYStem.Option STEPSOFT Use alternative method for ASM single step 107
SYStem.Option TDOSELect Select TDO source of lock step core pair 107
SYStem.Option VECTORS Specify interrupt vector table address 107
SYStem.Option WaitReset Set reset wait time 109
SYStem.Option WATCHDOG Debug with software watchdog timer 110
Command Reference: MMU Commands ......................................................................... 112
MMU.DUMP Page wise display of MMU translation table 112
MMU.List Compact display of MMU translation table 114

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MMU.SCAN Load MMU table from CPU 116
MMU.Set Set an MMU TLB entry 117
Command Reference: BenchMarkCounter ..................................................................... 118
BMC.<counter>.ATOB Enable event triggered counter start and stop 118
BMC.<counter>.FREEZE Freeze counter in certain core states 121
BMC.FREEZE Freeze counters while core halted 122
Command Reference: TrOnchip ...................................................................................... 123
TrOnchip.CONVert Adjust range breakpoint in on-chip resource 123
TrOnchip.EDBRAC0 Assign debug events to target software 124
TrOnchip.EVTEN Enable EVTI and EVTO pins 125
TrOnchip.RESet Reset on-chip trigger settings 126
TrOnchip.Set Enable special on-chip breakpoints 126
TrOnchip.VarCONVert Set single address breakpoint for scalar 127
TrOnchip.state View on-chip trigger setup window 128
Command Reference: Onchip .......................................................................................... 129
Onchip.TBARange Set on-chip trace buffer address range 129
Command Reference: NEXUS .......................................................................................... 130
NEXUS.BTM Enable program trace messaging 130
NEXUS.CLIENT<x>.BUSSEL Set NXMC target RAM 130
NEXUS.CLIENT<x>.MODE Set data trace mode of nexus client 130
NEXUS.CLIENT<x>.SELECT Select a nexus client for data tracing 131
NEXUS.CLIENT3.SPTACQMASTER Trace individual SPT masters 131
NEXUS.CoreENable Enable core tracing for dedicated cores in SMP 131
NEXUS.DDR Enable NEXUS double data rate mode 132
NEXUS.DMADTM Enable DMA data trace messaging 132
NEXUS.DTM Enable data trace messaging 133
NEXUS.DTMARK Data trace mark 133
NEXUS.DTMWhileHalted Data trace messaging while core halted 134
NEXUS.DQM Enable data acquisition messaging 134
NEXUS.FRAYDTM Enable FlexRay data trace messaging 134
NEXUS.HTM Enable branch history messaging 135
NEXUS.OFF Switch the NEXUS trace port off 135
NEXUS.ON Switch the NEXUS trace port on 136
NEXUS.OTM Enable ownership trace messaging 137
NEXUS.PCRCONFIG Configure NEXUS PCR for tracing 137
NEXUS.PINCR Define DCI PINCR register value 138
NEXUS.PortMode Set NEXUS trace port frequency 138
NEXUS.PortSize Set trace port width 139
NEXUS.POTD Periodic ownership trace disable 139
NEXUS.PTCM Enable program trace correlation messages 140
NEXUS.PTMARK Program trace mark 140
NEXUS.RefClock Enable Aurora reference clock 141

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NEXUS.Register Display NEXUS trace control registers 141
NEXUS.RESet Reset NEXUS trace port settings 141
NEXUS.RFMHISTBUGFIX Double RFM workaround 141
NEXUS.SmartTrace Enable smart trace analysis 142
NEXUS.Spen<messagetype> Enable message suppression 142
NEXUS.STALL Stall the program execution when FIFO full 142
NEXUS.state Display NEXUS port configuration window 143
NEXUS.SupprTHReshold Set fill level for message suppression 143
NEXUS.TimeStamps Enable on-chip timestamp generation 143
NEXUS.WTM Enable watchpoint messaging 144
Nexus specific TrOnchip Commands .............................................................................. 145
TrOnchip.Alpha Set special breakpoint function 145
TrOnchip.Beta Set special breakpoint function 145
TrOnchip.Charly Set special breakpoint function 146
TrOnchip.Delta Set special breakpoint function 146
TrOnchip.DISable Disable NEXUS trace register control 146
TrOnchip.Echo Set special breakpoint function 146
TrOnchip.ENable Enable NEXUS trace register control 147
TrOnchip.EVTI Allow the EVTI signal to stop the program execution 147
TrOnchip.EVTO Use EVTO signal for runtime measurement 147
TrOnchip.EXTernal Enable trace trigger input of NEXUS adapter 148
TrOnchip.Out0 Select OUT0 pin signal source 148
TrOnchip.Out1 Select OUT1 pin signal source 149
TrOnchip.TOOLIO2 Select TOOLIO2 pin signal source 150
TrOnchip.TRaceControl Trace control with special debug events 151
Debug and Trace Connectors .......................................................................................... 152
14-pin JTAG/OnCE Connector (JTAG) 152
AUTO26 Connector (JTAG) 152
10-pin ECU14 Connector (with converter LA-3843) 153
38-pin Mictor Connector (NEXUS parallel) 153
50-pin SAMTEC ERF8 Connector (NEXUS parallel) 154
51-pin GlenAir / ROBUST Connector (NEXUS parallel) 155
34-pin SAMTEC ERF8 Connector (Aurora NEXUS) 156
Mechanical Dimensions .................................................................................................... 157
Technical Data ................................................................................................................... 166
Operation Voltage 166
Operation Frequency 166

Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 7
©1989-2021 Lauterbach GmbH
Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
Version 30-Apr-2021

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©1989-2021 Lauterbach GmbH
Introduction
This document describes the processor specific settings and features for TRACE32-ICD for the following
CPU families:
• NXP/Freescale Qorivva MPC55XX, MPC56XX, MPC57XX and S32R (PowerPC series)
• STMicroelectronics SPC56X, SPC57X and SPC58X series
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
Available Tools
This chapter gives an overview over available Lauterbach TRACE32 tools for MPC5XXX/SPC5XX
processors.
JTAG/OnCE Debugger
Debugging MPC5XXX/SPC5XX requires a Lauterbach
Debug Cable together with a Lauterbach PowerDebug
Module. The following debug cables are available:
• LA-2708: Debugger for MPC5xxx Automotive PRO
• LA-3736: Debugger for MPC5xxx Automotive
• LA-7753: JTAG Debugger MPC5xxx/SPC5xx
NOTE: The processor specific information in this document is collected thoroughly from
processor reference manuals, data sheets and other sources. Lauterbach can
however not guarantee that the processor specific information provided in this
document is correct. Please refer to the processor reference manual and/or
manufacturer.
Processor specific information includes but is not limited to:
- existence of a processor
- number and types of cores
- availability of certain debug features on a processor or core
- existence and sizes of memory
- availability of on-chip and off-chip trace features

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The following debug modules are supported:
• LA-3500: POWER DEBUG INTERFACE / USB 3
• LA-3505: POWER DEBUG PRO
• LA-7699: POWER DEBUG II Ethernet
• LA-7708: POWER DEBUG INTERFACE / USB 2
• LA-7707/LA-7690: POWER TRACE / ETHERNET 256 / 512MB
• LA-7705: POWER DEBUG Ethernet
LA-7753 is additionally supported by:
• LA-7702: POWER DEBUG INTERFACE
• LA-7704: POWER DEBUG INTERFACE / USB
The DEBUG INTERFACE (LA-7701) does not support this processor series.
For a comparison of the Debug Cables see:
https://www.lauterbach.com/differences_between_standard_and_automotive_debug_cables.pdf
On-chip Trace
On-chip tracing requires no extra Lauterbach hardware, it can be configured and read out with a regular
JTAG/OnCE Debugger. Depending on the on-chip trace module implemented in the processor, a trace
license might or might not ne required. See e200 PCFIFO on-chip trace and MPC57XX/SPC57X NEXUS
on-chip trace for details.
High-Speed Serial Off-chip Trace (Aurora NEXUS)
Lauterbach offers an off-chip trace solution for processors
with Aurora NEXUS trace port. Aurora is a high-speed serial
interface defined by Xilinx.
Tracing requires the Aurora NEXUS Preprocessor for
Qorivva MPC57xx/SPC5XX (LA-3911) and a POWER
TRACE II module. A POWERTRACE / ETHERNET module
can be used with reduced speed and limited functionality.
See Basic Setup for Aurora Nexus for more information.

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Parallel Off-chip Trace (parallel NEXUS)
The parallel NEXUS trace port can be used with a PowerTrace/Ethernet or PowerTrace II module and one of
the following NEXUS adapters:
• LA-7630 NEXUS AutoFocus adapter:
up to 16 MDOs, I/O Voltage 1.0-5.2V, Trace clock up to 200 MHz SDR (up to 100 MHz in DDR)
Debug port sharing support, ext. Watchdog control, cJTAG support
• LA-7610 NEXUS Adapter MPC55XX:
up to 12 MDOs, I/O Voltage 2.6-3.6V, Trace clock up to 120 MHz SDR.
Debug port sharing support, ext. Watchdog control
• LA-7612 NEXUS Adapter MPC5510:
up to 8 MDOs, I/O Voltage 3V or 5V, Trace clock up to 110 MHz SDR.
See Basic Setup for Parallel Nexus for more information.
Co-Processor Debugging (eTPU/GTM/SPT)
Debugging the MPC5XXX coprocessors eTPU/eTPU2, GTM and SPT is included free of charge, i.e. there
is no additional license required.
For details about coprocessor debugging, see the specific Processor Architecture Manuals:
•“eTPU Debugger and Trace” (debugger_etpu.pdf)
•“GTM Debugger and Trace” (debugger_gtm.pdf)
Multicore Debugging
Lauterbach offers multicore debugging and tracing solutions, which can be done in two different setups:
Symmetric Multiprocessing (SMP) and Asymmetric Multiprocessing (AMP). For details see chapter
Multicore Debugging.
Concurrent debugging of multiple e200 cores requires a License for Multicore Debugging (MULTICORE).
Software-only Debugging (HostMCI) via XCP
TRACE32 PowerView also supports debugging and tracing without using TRACE32 PowerTools hardware.
The debug accesses are done via a 3rd party XCP slave. The following licenses are required to unlock this
feature:
• LA-8892L: 1 User Floating License PPC Front-End
• LA-9012L: 1 User Floating License XCP MPC5xxx Debug Back-End
• LA-8902L: 1 User Floating License Multicore Debugging (optional)
• LA-9013L: 1 User Floating License XCP MPC5xxx Trace License (optional)

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For more information see below documents:
•“XCP Debug Back-End” (backend_xcp.pdf)
•“Software-only Debugging (Host MCI)” (app_t32start.pdf)
Software Installation
Please follow chapter “Software Installation” (icd_quick_installation.pdf) on how to install the TRACE32
software:
• An installer is available for a complete TRACE32 installation under Windows.
See “MS Windows” in ICD Quick Installation, page 24 (icd_quick_installation.pdf).
• For a complete installation of TRACE32 under Linux, see “PC_LINUX” in ICD Quick Installation,
page 26 (icd_quick_installation.pdf).

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Hardware Installation
JTAG Debugger

POWER DEBUG USB INTERFACE / USB 3
POWER DEBUG INTERFACE / USB 3
PC or
Workstation
USB
Cable
Target
Debug
Connector
Debug Cable

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Parallel Nexus Debugger and Trace
POWER DEBUG PRO


POWER TRACE II
POWER DEBUG PRO
POWER TRACE II
SWITCH PC or
Workstation
1 GBit Ethernet
Ethernet
Cable
Target
CABLE
CBA
NEXUS ADAPTER
Nexus
Connector
NEXUS Adapter

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Aurora Nexus Debugger and Trace
POWER DEBUG PRO
POWER TRACE II
POWER DEBUG PRO
POWER TRACE II
SWITCH PC or
Workstation
1 GBit Ethernet
Ethernet
Cable
Target
Debug Cable
CABLE
CBA
Aurora
& JTAG
Adapter
Samtec34
Extension
Cable
Samtec 34
JTAG
Connector
(optional)
Preprocessor

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ESD Protection Considerations
Demo and Start-up Scripts
In your TRACE32 installation directory, there is a subdirectory ~~/demo/powerpc/ where you will find
example scripts and demo software.
For getting started there is a start-up script for every available PowerPC processor.
1. In TRACE32, choose File menu > Run Script.
2. Navigate to ~~/demo/powerpc/hardware/ and select your board and CPU. The demo scripts
can be started through the menu MPC5XXX > Tools > Start Demo:
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the debug cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the debug
cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the debug cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the debug cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.

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The directory ~~/demo/powerpc/ includes the following subdirectories:
Debug Cable / Nexus Adapter Versions and Detection
The following table shows how to detect which JTAG debug cable or NEXUS adapter is connected:
hardware/ Ready-to-run debugging and flash programming demos. The
demos are compiles to run in internal SRAM and therefore can be
used on any evaluation board and custom hardware.
flash/ Flash setup scripts and flash programming algorithm binaries for
on-chip and external flash. See chapter FLASH programming for
more information.
etc/ Examples for various PowerPC related debugger features.
kernel/ Example scripts for RTOS support.
compiler/ Compiler examples.
Debug cable and/or
Nexus adapter version
Condition in PRACTICE script language
LA-2708
(Automotive debug cable
PRO)
PRINT ID.CABLE()==0x4150
LA-3736
(Automotive debug cable)
PRINT ID.CABLE()==0x4155
LA-7753 rev. 1
(OnCE debug cable,
JTAG only,
no reset detection)
PRINT (ID.CABLE()&0xEFFF)==0x604F
LA-7753 rev. 2
(OnCE debug cable,
JTAG and cJTAG,
supports reset detection)
PRINT ID.CABLE()==0x3535
LA-7630
(Nexus Adapter,
max 16 MDO / 2 MSEO,
1-5V, SDR and DDR)
PRINT POWERNEXUS()&&(ID.CABLE()==0x0002)

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Brief Overview of Documents for New Users
Architecture-independent information:
•“Debugger Basics - Training” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.
•“XCP Debug Back-End” (backend_xcp.pdf): This manual describes how to debug a target over a
3rd-party tool using the XCP protocol.
Further information:
•“Nexus Training” (training_nexus.pdf): Training for the NEXUS trace
•“Onchip/NOR FLASH Programming User’s Guide” (norflash.pdf): Onchip FLASH and off-chip
NOR FLASH programming.
•“Debugger Basics - SMP Training” (training_debugger_smp.pdf): SMP debugging.
•“eTPU Debugger and Trace” (debugger_etpu.pdf): Debugging and tracing the eTPU/eTPU2.
•“GTM Debugger and Trace” (debugger_gtm.pdf): Debugging and tracing the Generic Timer
Module (GTM).
LA-7610
(Nexus Adapter,
max 12 MDO / 2 MSEO
3.3V, SDR only)
PRINT POWERNEXUS()&&(ID.CABLE()==0x0000)
LA-7612
(Nexus Adapter,
max 8 MDO / 1 MSEO,
5V, SDR only)
PRINT POWERNEXUS()&&(ID.CABLE()==0x0001)
LA-3911
(High speed serial prepro-
cessor for Aurora NEXUS)
PRINT POWERTRACE()&&!POWERNEXUS()

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Target Design Requirement/Recommendations
General (ICD Debugger)
• Locate the JTAG/OnCE or Trace connector as close as possible to the processor to minimize
the capacitive influence of the trace length and cross coupling of noise onto the JTAG signals.
Don’t put any capacitors (or RC combinations) on the JTAG lines.
• Connect TDI, TDO, TMS and TCK directly to the CPU. Buffers on the JTAG lines will add delays
and will reduce the maximum possible JTAG frequency. If you need to use buffers, select ones
with little delay. Most CPUs will support JTAG above 30 MHz, and you might want to use high
frequencies for optimized download performance.
• Ensure that JTAG RESET is connected directly to the RESET of the processor. This will provide
the ability for the debugger to drive and sense the status of RESET
. The target design should
only drive RESET with open collector/open drain.
• For optimal operation, the debugger should be able to reset the target board completely
(processor external peripherals, e.g. memory controllers) with RESET.
• In order to start debugging right from reset, the debugger must be able to control CPU RESET
and CPU TRST (JCOMP) independently. There are board design recommendations to tie CPU
TRST (JCOMP) to CPU RESET, but this recommendation is not suitable for JTAG debuggers.
.
Debug cable
with blue
ribbon cable
The T32 internal buffer/level shifter will be supplied via the VCCS pin.
Therefore it is necessary to reduce the VCCS pull-up on the target board
to a value smaller 10 .

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Quick Start
Run Program from On-chip SRAM
Follow these steps to run a program from the on-chip SRAM:
1. Select the target processor, or use automatic CPU detection.
2. Multi-core processors: Select the core that starts running directly form reset
3. Start debug session. Debugger resets processor and halts the core at the reset address.
4. Cores with MMU: After SYStem.Up, the core’s MMU holds only a single TLB that maps the reset
address. In order to run an application from SRAM, set up the required TLBs manually.
5. Cores with MMU: In order to run an application from SRAM, set up the required TLBs manually.
For run-time memory access, the debugger requires a static translation table. As the core is
halted and MMU set up, we can take the translation form the TLBs:
SYStem.CPU MPC5554
; or
SYStem.DETECT CPU
;MPC55XX/56XX: select core_0
SYStem.CONFIG.CORE 1. 1.
;MPC5746M: select core_2
SYStem.CONFIG.CORE 3. 1.
SYStem.Up
;initialize MPC55XX MMU (same as BAM)
MMU.Set TLB1 0. 0x00000000 0x00000000 0x00000000
MMU.Set TLB1 1. 0xC0000500 0xFFF0000A 0xFFF0003F
MMU.Set TLB1 2. 0xC0000700 0x20000000 0x2000003F
MMU.Set TLB1 3. 0xC0000400 0x40000000 0x4000003F
MMU.Set TLB1 4. 0xC0000500 0xC3F00008 0xC3F0003F
MMU.Set TLB1 5. 0xC0000700 0x00000000 0x0000003F
;copy core TLBs to debugger translation table
MMU.SCAN TLB1
;enable debugger based address translation
TRANSlation.ON

Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 2 0
©1989-2021 Lauterbach GmbH
6. MPC5XXX on-chip SRAM must be initialized (ECC) before usage.
7. Load the program.
8. Run program, e.g. until function main.
9. Display ASM/HLL core at current instruction pointer
Data.Set EA:0x40000000--0x4000FFFF%Quad 0x1122334455667788
Data.LOAD.Elf demo.elf ; ELF specifies the format,
; demo.elf is the file name
Go main
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