SONIX SN8P2511 User manual

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version 1.2
SN8P2511
USER’S MANUAL
Version 1.2
SN8P2511
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version 1.2
AMENDENT HISTORY
Version
Date
Description
VER 1.0
Feb. 2012
First issue.
VER 1.1
Apr. 2012
Add features selection table and migration section.
VER 1.2
Jan. 2013
Modify 32KHz oscillator to match capacitor in external high-speed oscillator section.

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 1.2
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1PRODUCT OVERVIEW........................................................................................................................... 6
1.1 FEATURES........................................................................................................................................ 6
1.2 SYSTEM BLOCK DIAGRAM.......................................................................................................... 7
1.3 PIN ASSIGNMENT........................................................................................................................... 7
1.4 PIN DESCRIPTIONS......................................................................................................................... 8
1.5 PIN CIRCUIT DIAGRAMS............................................................................................................... 9
2
2
2CENTRAL PROCESSOR UNIT (CPU).................................................................................................. 10
2.1 PROGRAM MEMORY (ROM)....................................................................................................... 10
2.1.1 RESET VECTOR (0000H) ...................................................................................................... 11
2.1.2 INTERRUPT VECTOR (0008H)............................................................................................. 12
2.1.3 LOOK-UP TABLE DESCRIPTION........................................................................................ 14
2.1.4 JUMP TABLE DESCRIPTION............................................................................................... 16
2.1.5 CHECKSUM CALCULATION............................................................................................... 18
2.2 DATA MEMORY (RAM)................................................................................................................ 19
2.2.1 SYSTEM REGISTER .............................................................................................................. 19
2.2.1.1 SYSTEM REGISTER TABLE ............................................................................................ 19
2.2.1.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 19
2.2.1.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 20
2.2.2 ACCUMULATOR ................................................................................................................... 21
2.2.3 PROGRAM FLAG................................................................................................................... 22
2.2.4 PROGRAM COUNTER........................................................................................................... 23
2.2.5 Y, Z REGISTERS..................................................................................................................... 25
2.2.6 R REGISTER ........................................................................................................................... 25
2.3 ADDRESSING MODE .................................................................................................................... 26
2.3.1 IMMEDIATE ADDRESSING MODE .................................................................................... 26
2.3.2 DIRECTLY ADDRESSING MODE ....................................................................................... 26
2.3.3 INDIRECTLY ADDRESSING MODE................................................................................... 26
2.4 STACK OPERATION...................................................................................................................... 27
2.4.1 OVERVIEW............................................................................................................................. 27
2.4.2 STACK REGISTERS............................................................................................................... 27
2.4.3 STACK OPERATION EXAMPLE.......................................................................................... 28
2.5 CODE OPTION TABLE.................................................................................................................. 29
2.5.1 Fcpu code option ...................................................................................................................... 29
2.5.2 Reset_Pin code option.............................................................................................................. 29
2.5.3 Security code option................................................................................................................. 29
2.5.4 Noise Filter code option ........................................................................................................... 29
3
3
3RESET...................................................................................................................................................... 30
3.1 OVERVIEW..................................................................................................................................... 30
3.2 POWER ON RESET......................................................................................................................... 31
3.3 WATCHDOG RESET...................................................................................................................... 31
3.4 BROWN OUT RESET ..................................................................................................................... 31
3.5 THE SYSTEM OPERATING VOLTAGE....................................................................................... 32
3.6 LOW VOLTAGE DETECTOR (LVD)............................................................................................ 32
3.7 BROWN OUT RESET IMPROVEMENT....................................................................................... 34
3.8 EXTERNAL RESET........................................................................................................................ 35
3.9 EXTERNAL RESET CIRCUIT ....................................................................................................... 35
3.9.1 Simply RC Reset Circuit .......................................................................................................... 35

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version 1.2
3.9.2 Diode & RC Reset Circuit........................................................................................................ 36
3.9.3 Zener Diode Reset Circuit........................................................................................................ 36
3.9.4 Voltage Bias Reset Circuit ....................................................................................................... 37
3.9.5 External Reset IC...................................................................................................................... 37
4
4
4SYSTEM CLOCK.................................................................................................................................... 38
4.1 OVERVIEW..................................................................................................................................... 38
4.2 FCPU (INSTRUCTION CYCLE)...................................................................................................... 38
4.3 NOISE FILTER................................................................................................................................ 39
4.4 SYSTEM HIGH-SPEED CLOCK.................................................................................................... 39
4.4.1 HIGH_CLK CODE OPTION................................................................................................... 39
4.4.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC)............................................. 39
4.4.3 EXTERNAL HIGH-SPEED OSCILLATOR........................................................................... 39
4.4.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT....................................................... 40
4.5 SYSTEM LOW-SPEED CLOCK..................................................................................................... 41
4.6 OSCM REGISTER........................................................................................................................... 42
4.7 SYSTEM CLOCK MEASUREMENT............................................................................................. 42
4.8 SYSTEM CLOCK TIMING............................................................................................................. 43
5
5
5SYSTEM OPERATION MODE.............................................................................................................. 46
5.1 OVERVIEW..................................................................................................................................... 46
5.2 NORMAL MODE ............................................................................................................................ 47
5.3 SLOW MODE .................................................................................................................................. 47
5.4 POWER DOWN MODE .................................................................................................................. 47
5.5 GREEN MODE ................................................................................................................................ 48
5.6 OPERATING MODE CONTROL MACRO.................................................................................... 49
5.7 WAKEUP......................................................................................................................................... 50
5.7.1 OVERVIEW............................................................................................................................. 50
5.7.2 WAKEUP TIME ...................................................................................................................... 50
5.7.3 P1W WAKEUP CONTROL REGISTER................................................................................ 51
6
6
6INTERRUPT............................................................................................................................................ 52
6.1 OVERVIEW..................................................................................................................................... 52
6.2 INTEN INTERRUPT ENABLE REGISTER................................................................................... 52
6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 53
6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 53
6.5 PUSH, POP ROUTINE..................................................................................................................... 54
6.6 EXTERNAL INTERRUPT OPERATION (INT0)........................................................................... 55
6.7 T0 INTERRUPT OPERATION........................................................................................................ 56
6.8 TC0 INTERRUPT OPERATION..................................................................................................... 58
6.9 MULTI-INTERRUPT OPERATION............................................................................................... 59
7
7
7I/O PORT.................................................................................................................................................. 60
7.1 OVERVIEW..................................................................................................................................... 60
7.2 I/O PORT MODE ............................................................................................................................. 61
7.3 I/O PULL UP REGISTER ................................................................................................................ 62
7.4 I/O OPEN-DRAIN REGISTER........................................................................................................ 63
7.5 I/O PORT DATA REGISTER.......................................................................................................... 64
8
8
8TIMERS.................................................................................................................................................... 65
8.1 WATCHDOG TIMER...................................................................................................................... 65
8.2 TIMER 0(T0)................................................................................................................................... 67
8.2.1 OVERVIEW............................................................................................................................. 67
8.2.2 T0 Timer Operation.................................................................................................................. 68
8.2.3 T0M MODE REGISTER ......................................................................................................... 69
8.2.4 T0C COUNTING REGISTER................................................................................................. 69
8.2.5 T0 TIMER OPERATION EXPLAME..................................................................................... 70

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version 1.2
8.3 TC0 8-BIT TIMER/COUNTER ....................................................................................................... 71
8.3.1 OVERVIEW............................................................................................................................. 71
8.3.2 TC0 TIMER OPERATION...................................................................................................... 72
8.3.3 TC0M MODE REGISTER....................................................................................................... 73
8.3.4 TC0C COUNTING REGISTER .............................................................................................. 74
8.3.5 TC0R AUTO-RELOAD REGISTER....................................................................................... 75
8.3.6 TC0 EVENT COUNTER......................................................................................................... 76
8.3.7 TC0 BUZZER OUTPUT.......................................................................................................... 76
8.3.8 PULSE WIDTH MODULATION (PWM) .............................................................................. 77
8.3.9 TC0 TIMER OPERATION EXPLAME.................................................................................. 79
9
9
9INSTRUCTION TABLE.......................................................................................................................... 81
1
1
10
0
0ELECTRICAL CHARACTERISTIC................................................................................................... 82
10.1 ABSOLUTE MAXIMUM RATING................................................................................................ 82
10.2 ELECTRICAL CHARACTERISTIC............................................................................................... 82
10.3 CHARACTERISTIC GRAPHS ....................................................................................................... 83
1
1
11
1
1DEVELOPMENT TOOL..................................................................................................................... 84
11.1 SN8P2511/2501A/B/C EV-KIT......................................................................................................... 84
11.2 ICE AND EV-KIT APPLICATION NOTIC...................................................................................... 85
1
1
12
2
2OTP PROGRAMMING PIN................................................................................................................ 86
12.1 WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT................................................. 86
12.2 PROGRAMMING PIN MAPPING:................................................................................................. 87
1
1
13
3
3MARKING DEFINITION ................................................................................................................... 88
13.1 INTRODUCTION............................................................................................................................ 88
13.2 MARKING INDETIFICATION SYSTEM...................................................................................... 88
13.3 MARKING EXAMPLE ................................................................................................................... 89
13.4 DATECODE SYSTEM.................................................................................................................... 89
1
1
14
4
4PACKAGE INFORMATION .............................................................................................................. 90
14.1 P-DIP 14 PIN.................................................................................................................................... 90
14.2 SOP 14 PIN....................................................................................................................................... 91
14.3 SSOP 16 PIN..................................................................................................................................... 92

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version 1.2
1
1
1 PRODUCT OVERVIEW
1.1 FEATURES
Features Selection Table
CHIP
ROM
RAM
Stack
Timer
I/O
IHRC
PWM
Buzzer
Wake-up
Pin No.
Package
T0
TC0
SN8P2501B
1K
48
4
V
V
12
V
1
1
5
DIP14/SOP14/SSOP16
SN8P2511
1K
48
4
V
V
12
V
1
1
5
DIP14/SOP14/SSOP16
Migration SN8P2501B to SN8P2511
Item
SN8P2501B
SN8P2511
T0 timer
In RTC mode, clear T0IRQ must be after
1/2 RTC clock source (32768Hz), or the
RTC interval time is error.
No limitation.
IHRC 16MHz
IHRC_16M and IHRC_RTC modes don't
support Fosc/1 and Fosc/2.
No limitation.
SN8P2511 is compatible to SN8P2501B.
SN8P2501B code can transfer to SN8P2511 directly. Program the original SN8 of SN8P2501B into SN8P2511
directly with declare SN8P2511 chip name in source code and re-compile again.

Memory configuration

Fcpu (Instruction cycle)
ROM size: 1K * 16 bits.
Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16.
RAM size: 48 * 8 bits.

One 8-bit basic timer with RTC (0.5Sec).

4 levels stack buffer.

One 8-bit timer with external event counter,
Buzzer and PWM. (TC0).

3 interrupt sources
2 internal interrupts: T0, TC0

On chip watchdog timer and clock source is
1 external interrupt: INT0
Internal low clock RC type (16KHz(3V), 32KHz(5V))

I/O pin configuration

Four system clocks
Bi-directional: P0, P1, P2, P5.
External high clock: RC type up to 10 MHz
Wakeup: P0, P1 level change.
External high clock: Crystal type up to 16 MHz
Pull-up resisters: P0, P1, P2, P5.
Internal high clock: 16MHz RC type
Input only: P1.1
Internal low clock: RC type 16KHz(3V), 32KHz(5V)
Programmable open-drain: P1.0
External interrupt: P0.0 (PEDGE edge trigger)

Four operating modes
Normal mode: Both high and low clock active

3-Level LVD.
Slow mode: Low clock only.
Reset system and power monitor.
Sleep mode: Both high and low clock stop
Green mode: Periodical wakeup by T0 timer

Powerful instructions
Instruction’s length is one word.

Package (Chip form support)
Most of instructions are one cycle only.
DIP 14 pin
All ROM area JMP/CALL instruction.
SOP 14 pin
All ROM area lookup table function (MOVC).
SSOP 16 pin

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 1.2
1.2 SYSTEM BLOCK DIAGRAM
INTERRUPT
CONTROL
EXTERNAL
HIGH OSC.
ACC
INTERNAL
LOW RC
INTERNAL HIGH
RC 16MHz
TIMING GENERATOR
RAM
SYSTEM REGISTERS
3 Level LVD
(Low Voltage Detector)
WATCHDOG TIMER
TIMER & COUNTER
P0 P5P1
PWM / BUZZER
ALU
PC
FLAGS
IR OTP
ROM
PWM0 /
BUZZER0
P2
1.3 PIN ASSIGNMENT
SN8P2511P (P-DIP 14 pins)
SN8P2511S (SOP 14 pins)
P2.2
1
U
14
P2.3
P2.1
2
13
P2.4
P2.0
3
12
P2.5
VDD
4
11
VSS
P1.3/XIN
5
10
P0.0/INT0
P1.2/XOUT
6
9
P1.0
P1.1/RST/VPP
7
8
P5.4/BZ0/PWM0
SN8P2511P
SN8P2511S
SN8P2511X (SSOP 16 pins)
P2.2
1
U
16
P2.3
P2.1
2
15
P2.4
P2.0
3
14
P2.5
VDD
4
13
VSS
VDD
5
12
VSS
P1.3/XIN
6
11
P0.0/INT0
P1.2/XOUT
7
10
P1.0
P1.1/RST/VPP
8
9
P5.4/BZ0/PWM0
SN8P2511X

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version 1.2
1.4 PIN DESCRIPTIONS
PIN NAME
TYPE
DESCRIPTION
VDD, VSS
P
Power supply input pins for digital and analog circuit.
P1.1/RST/VPP
I, P
RST: System external reset input pin. Schmitt trigger structure, active “low”, normal stay
to “high”.
VPP: OTP 12.3V power input pin in programming mode.
P1.1: Input only pin with Schmitt trigger structure and no pull-up resistor. Level change
wake-up.
P0.0/INT0
I/O
P0.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
INT0: External interrupt 0 input pin.
P1.0
I/O
P1.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up. Programmable open-drain structure.
P1.2/XOUT
I/O
XOUT: Oscillator output pin while external crystal enable.
P1.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
P1.3/XIN
I/O
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
P1.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
P5.4/PWM0/BZ0
I/O
P5.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
PWM0: PWM output pin.
BZ0: Buzzer TC0/2 output pin.
P2 [5:0]
I/O
P2 [5:0]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up
resisters.

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version 1.2
1.5 PIN CIRCUIT DIAGRAMS
Reset shared pin structure:
Pin
Ext. Reset
Code Option
I/O Input Bus
Reset
Oscillator shared pin structure:
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
High_Clk
Code Option
Oscillator Driver
GPIO structure:
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
Open-drain share pin structure:
Open-Drain
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
P1OC

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 Version 1.2
2
2
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 PROGRAM MEMORY (ROM)
1K words ROM
ROM
0000H
Reset vector
User reset vector
Jump to user start address
0001H
General purpose area
.
.
0007H
0008H
Interrupt vector
User interrupt vector
0009H
General purpose area
User program
.
.
000FH
0010H
0011H
.
.
03FCH
End of user program
03FDH
Reserved
03FEH
03FFH
The ROM includes Reset vector, Interrupt vector, General purpose area and Reserved area. The Reset vector is
program beginning address. The Interrupt vector is the head of interrupt service routine when any interrupt occurring.
The General purpose area is main program area including main loop, sub-routines and data table.

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version 1.2
2.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
Power On Reset (NT0=1, NPD=0).
Watchdog Reset (NT0=0, NPD=0).
External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
Example: Defining Reset Vector
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
10H
START:
; 0010H, The head of user program.
…
; User program
…
ENDP
; End of program

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version 1.2
2.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP”instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
PUSH
; Save ACC and PFLAG register to buffers.
…
…
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine
…
START:
; The head of user program.
…
; User program
…
JMP
START
; End of user program
…
ENDP
; End of program

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version 1.2
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
JMP
MY_IRQ
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
; 0010H, The head of user program.
…
; User program.
…
…
JMP
START
; End of user program.
…
MY_IRQ:
;The head of interrupt service routine.
PUSH
; Save ACC and PFLAG register to buffers.
…
…
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine.
…
ENDP
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP”instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version 1.2
2.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
Example: To look up the ROM data located “TABLE1”.
B0MOV
Y, #TABLE1$M
; To set lookup table1’s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1’s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS
Z
; Z+1
JMP
@F
; Z is not overflow.
INCMS
Y
; Z overflow (FFH 00), Y=Y+1
NOP
;
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
…
;
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must be take care such situation to avoid look-up table errors. If Z register is
overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process
Y and Z registers automatically.
Example: INC_YZ macro.
INC_YZ
MACRO
INCMS
Z
; Z+1
JMP
@F
; Not overflow
INCMS
Y
; Y+1
NOP
; Not overflow
@@:
ENDM

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version 1.2
Example: Modify above example by “INC_YZ”macro.
B0MOV
Y, #TABLE1$M
; To set lookup table1’s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1’s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
INC_YZ
; Increment the index address for next address.
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
…
;
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV
Y, #TABLE1$M
; To set lookup table’s middle address.
B0MOV
Z, #TABLE1$L
; To set lookup table’s low address.
B0MOV
A, BUF
; Z = Z + BUF.
B0ADD
Z, A
B0BTS1
FC
; Check the carry flag.
JMP
GETDATA
; FC = 0
INCMS
Y
; FC = 1. Y+1.
NOP
GETDATA:
;
MOVC
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version 1.2
2.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: Jump table.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
PCL, A
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A
MACRO
VAL
IF
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP
($ | 0XFF)
ORG
($ | 0XFF)
ENDIF
B0ADD
PCL, A
ENDM
Note: “VAL”is the number of the jump table listing number.
Example: “@JMP_A”application in SONIX macro file called “MACRO3.H”.
B0MOV
A, BUF0
; “BUF0”is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
JMP
A4POINT
; ACC = 4, jump to A4POINT

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version 1.2
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A”macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
Example: “@JMP_A”operation.
; Before compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0”is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X00FD
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X00FE
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X00FF
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0100
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0101
JMP
A4POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0”is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X0100
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X0101
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X0102
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0103
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0104
JMP
A4POINT
; ACC = 4, jump to A4POINT

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 Version 1.2
2.1.5 CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV
A,#END_USER_CODE$L
B0MOV
END_ADDR1, A
; Save low end address to end_addr1
MOV
A,#END_USER_CODE$M
B0MOV
END_ADDR2, A
; Save middle end address to end_addr2
CLR
Y
; Set Y to 00H
CLR
Z
; Set Z to 00H
@@:
MOVC
B0BSET
FC
; Clear C flag
ADD
DATA1, A
; Add A to Data1
MOV
A, R
ADC
DATA2, A
; Add R to Data2
JMP
END_CHECK
; Check if the YZ address = the end of code
AAA:
INCMS
Z
; Z=Z+1
JMP
@B
; If Z != 00H calculate to next address
JMP
Y_ADD_1
; If Z = 00H increase Y
END_CHECK:
MOV
A, END_ADDR1
CMPRS
A, Z
; Check if Z = low end address
JMP
AAA
; If Not jump to checksum calculate
MOV
A, END_ADDR2
CMPRS
A, Y
; If Yes, check if Y = middle end address
JMP
AAA
; If Not jump to checksum calculate
JMP
CHECKSUM_END
; If Yes checksum calculated is done.
Y_ADD_1:
INCMS
Y
; Increase Y
NOP
JMP
@B
; Jump to checksum calculate
CHECKSUM_END:
…
…
END_USER_CODE:
; Label of program end

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 Version 1.2
2.2 DATA MEMORY (RAM)
48 X 8-bit RAM
Address
RAM Location
BANK 0
000h
General Purpose Area
RAM Bank 0
“
“
“
02Fh
080h
System Register
080h~0FFh of Bank 0 store system
registers (128 bytes).
“
“
“
0FFh
End of Bank 0
The 48-byte general purpose RAM is separated into Bank 0. Sonix provides “Bank 0”type instructions (e.g. b0mov,
b0add, b0bts1, b0bset…) to control Bank 0 RAM directly.
2.2.1 SYSTEM REGISTER
2.2.1.1 SYSTEM REGISTER TABLE
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8
-
-
R
Z
Y
-
PFLAG
-
-
-
-
-
-
-
-
-
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B
-
-
-
-
-
-
-
-
P0M
-
-
-
-
-
-
PEDGE
C
P1W
P1M
P2M
-
-
P5M
-
-
INTRQ
INTEN
OSCM
-
WDTR
TC0R
PCL
PCH
D
P0
P1
P2
-
-
P5
-
-
T0M
T0C
TC0M
TC0C
-
-
-
STKP
E
P0UR
P1UR
P2UR
-
-
P5UR
-
@YZ
-
P1OC
-
-
-
-
-
-
F
-
-
-
-
-
-
-
-
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
2.2.1.2 SYSTEM REGISTER DESCRIPTION
R =
Working register and ROM look-up data buffer.
Y, Z =
Working, @YZ and ROM addressing register.
PFLAG =
Special flag register.
PEDGE =
P0.0 edge direction register.
INTRQ =
Interrupt request register.
INTEN =
Interrupt enable register.
WDTR =
Watchdog timer clear register.
Pn =
Port n data buffer.
PnM =
Port n input/output mode register.
OSCM =
Oscillator mode register.
PnUR =
Port n pull-up resister control register.
T0M =
T0 mode register.
PCH, PCL =
Program counter.
TC0M =
TC0 mode register.
T0C =
T0 counting register.
TC0R =
TC0 auto-reload data buffer.
TC0C =
TC0 counting register.
@YZ =
RAM YZ indirect addressing index pointer.
P1OC =
P1.0 open-drain control register.
STK0~STK3 =
Stack 0 ~ stack 3 buffer.
STKP =
Stack pointer buffer.

SN8P2511
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version 1.2
2.2.1.3 BIT DEFINITION of SYSTEM REGISTER
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Remarks
082H
RBIT7
RBIT6
RBIT5
RBIT4
RBIT3
RBIT2
RBIT1
RBIT0
R/W
R
083H
ZBIT7
ZBIT6
ZBIT5
ZBIT4
ZBIT3
ZBIT2
ZBIT1
ZBIT0
R/W
Z
084H
YBIT7
YBIT6
YBIT5
YBIT4
YBIT3
YBIT2
YBIT1
YBIT0
R/W
Y
086H
NT0
NPD
LVD36
LVD24
C
DC
Z
R/W
PFLAG
0B8H
P00M
R/W
P0M
0BFH
P00G1
P00G0
R/W
PEDGE
0C0H
P13W
P12W
P11W
P10W
W
P1W
0C1H
P13M
P12M
P10M
R/W
P1M
0C2H
P25M
P24M
P23M
P22M
P21M
P20M
R/W
P2M
0C5H
P54M
R/W
P5M
0C8H
TC0IRQ
T0IRQ
P00IRQ
R/W
INTRQ
0C9H
TC0IEN
T0IEN
P00IEN
R/W
INTEN
0CAH
CPUM1
CPUM0
CLKMD
STPHX
R/W
OSCM
0CCH
WDTR7
WDTR6
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0
W
WDTR
0CDH
TC0R7
TC0R6
TC0R5
TC0R4
TC0R3
TC0R2
TC0R1
TC0R0
W
TC0R
0CEH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
R/W
PCL
0CFH
PC9
PC8
R/W
PCH
0D0H
P00
R/W
P0
0D1H
P13
P12
P11
P10
R/W
P1
0D2H
P25
P24
P23
P22
P21
P20
R/W
P2
0D5H
P54
R/W
P5
0D8H
T0ENB
T0rate2
T0rate1
T0rate0
T0TB
R/W
T0M
0D9H
T0C7
T0C6
T0C5
T0C4
T0C3
T0C2
T0C1
T0C0
R/W
T0C
0DAH
TC0ENB
TC0rate2
TC0rate1
TC0rate0
TC0CKS
ALOAD0
TC0OUT
PWM0OUT
R/W
TC0M
0DBH
TC0C7
TC0C6
TC0C5
TC0C4
TC0C3
TC0C2
TC0C1
TC0C0
R/W
TC0C
0DFH
GIE
STKPB1
STKPB0
R/W
STKP
0E0H
P00R
W
P0UR
0E1H
P13R
P12R
P10R
W
P1UR
0E2H
P25R
P24R
P23R
P22R
P21R
P20R
W
P2UR
0E5H
P54R
W
P5UR
0E7H
@YZ7
@YZ6
@YZ5
@YZ4
@YZ3
@YZ2
@YZ1
@YZ0
R/W
@YZ
0E9H
P10OC
W
P1OC
0F8H
S3PC7
S3PC6
S3PC5
S3PC4
S3PC3
S3PC2
S3PC1
S3PC0
R/W
STK3L
0F9H
S3PC9
S3PC8
R/W
STK3H
0FAH
S2PC7
S2PC6
S2PC5
S2PC4
S2PC3
S2PC2
S2PC1
S2PC0
R/W
STK2L
0FBH
S2PC9
S2PC8
R/W
STK2H
0FCH
S1PC7
S1PC6
S1PC5
S1PC4
S1PC3
S1PC2
S1PC1
S1PC0
R/W
STK1L
0FDH
S1PC9
S1PC8
R/W
STK1H
0FEH
S0PC7
S0PC6
S0PC5
S0PC4
S0PC3
S0PC2
S0PC1
S0PC0
R/W
STK0L
0FFH
S0PC9
S0PC8
R/W
STK0H
Note:
1. To avoid system error, make sure to put all the “0” and “1” as it indicates in the above table.
2. All of register names had been declared in SN8ASM assembler.
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.