Fujitsu FR Family FR60 Lite User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR60
32-BIT MICROCONTROLLER
MB91350A Series
HARDWARE MANUAL
CM71-10121-3E

FUJITSU LIMITED
FR60
32-BIT MICROCONTROLLER
MB91350A Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

i
CONTENTS
■Objectives and Intended Reader
The MB91350A series is one of the FR60 family of microcontrollers. The FR60 family of microcontrollers
is based on the FR30/40 family of CPUs, which use a 32-bit high-performance RISC CPU as the core CPU.
The FR60 family offers enhanced bus access. The MB91350A series is a single-chip microcontroller with
built-in peripheral resources. The MB91350A series is ideal for embedded control applications that require
high-performance or high-speed CPU processing.
This manual is intended for engineers who will develop products using the MB91350A series and describes
the functions and operations of the MB91350A series. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
Note : FR, which is an abbreviation of FUJITSU RISC controller, is a product of FUJITSU LIMITED.
■Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■License
Purchase of Fujitsu I2C components conveys a licence under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■Organization of This Manual
This manual consists of the following 19 chapters and an appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information required to understand the MB91350A series. It covers features
and dimensions, and presents a block diagram of the MB91350A series.
CHAPTER 2 HANDLING THE DEVICE
This chapter provides precautions on handling the device.
CHAPTER 3 CPU AND CONTROL UNITS
This chapter provides basic information required to understand the MB91350A series core CPU
functions. It covers architecture, specifications, and instructions.
CHAPTER 4 EXTERNAL BUS INTERFACE
This chapter describes basic items related to the external bus interface, register configuration/functions,
bus operation, bus timing, and procedures for setting the registers.
CHAPTER 5 I/O PORT
This chapter describes the I/O ports and the configuration and functions of registers.

ii
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
This chapter outlines the 8/16-bit up/down counter/timer and U-TIMER and explains the configuration
and functions of the registers and timer operations.
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER
This chapter outlines the 16-bit free-running timer and 16-bit reload timer and explains the
configuration and functions of the registers and timer operations.
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER
This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the
register configuration and functions and the timer operations.
CHAPTER 9 INTERRUPT CONTROLLER
This chapter describes the overview of the interrupt controller, the configuration and functions of
registers, and interrupt controller operation.
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter outlines the external interrupt/NMI controller and explains the configuration and functions
of the registers and operations of the external interrupt/NMI controller.
CHAPTER 11 REALOS-RELATED HARDWARE
This chapter outlines the delayed interrupt module and bit search module, and explains the
configuration and functions of registers and operations.
CHAPTER 12 A/D CONVERTER
This chapter outlines the A/D converter and explains the configuration and functions of registers and
the A/D converter operations.
CHAPTER 13 8-BIT D/A CONVERTER
This chapter gives an overview of the 8-bit D/A converter, register configuration and functions, and 8-
bit D/A converter operation.
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND
OUTPUT COMPARE MODULE
This chapter outlines the UART, SIO, input capture, and output compare, and explains the configuration
and functions of registers. It also explains UART, SIO, input capture, and output compare operations.
CHAPTER 15 I2C INTERFACE
This chapter describes the overview of the I2C interface, the configuration and functions of registers,
and I2C interface operation.
CHAPTER 16 DMA CONTROLLER (DMAC)
This chapter describes the overview of the DMAC, the configuration and functions of registers, and
DMAC operation.
CHAPTER 17 FLASH MEMORY
This chapter provides an outline of flash memory and explains its register configuration, register
functions, and operations.
CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION
This chapter describes the serial onboard writing connection (Fujitsu standard) using the AF220/AF210/
AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation.

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CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS
RESTRICTION FUNCTIONS
This chapter outlines a function that restricts access to data internal RAM and instruction internal RAM.
It also explains the configuration and functions of registers and internal RAM operations.
APPENDIX
This appendix consists of the following parts: I/O map, interrupt vectors, pin state for each CPU state,
and the instruction lists.

iv
Copyright ©2003-2007 FUJITSU LIMITED All rights reserved
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such
information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection
with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Features .............................................................................................................................................. 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimensions .......................................................................................................................... 9
1.4 Pin Layout ......................................................................................................................................... 11
1.5 List of Pin Functions ......................................................................................................................... 13
1.6 Input-output Circuit Forms ................................................................................................................ 27
CHAPTER 2 HANDLING THE DEVICE .......................................................................... 31
2.1 Precautions on Handling the Device ................................................................................................. 32
2.2 Precautions on Using the Little-Endian Area .................................................................................... 37
2.2.1 C Compiler (fcc911) ..................................................................................................................... 38
2.2.2 Assembler (fasm911) .................................................................................................................. 41
2.2.3 Linker (flnk911) ............................................................................................................................ 42
2.2.4 Debuggers (sim911, eml911, and mon911) ................................................................................ 43
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 45
3.1 Memory Space .................................................................................................................................. 46
3.2 Internal Architecture .......................................................................................................................... 49
3.2.1 Internal Architecture .................................................................................................................... 50
3.2.2 Overview of Instructions .............................................................................................................. 53
3.3 Programming Model ......................................................................................................................... 55
3.3.1 General-Purpose Registers ......................................................................................................... 56
3.3.2 Dedicated Registers .................................................................................................................... 57
3.4 Data Configuration ............................................................................................................................ 64
3.5 Memory Map ..................................................................................................................................... 66
3.6 Branch Instructions ........................................................................................................................... 67
3.6.1 Operations with a Delay Slot ....................................................................................................... 68
3.6.2 Operation without Delay Slot ....................................................................................................... 71
3.7 EIT (Exception, Interrupt, and Trap) ................................................................................................. 72
3.7.1 EIT Interrupt Levels ..................................................................................................................... 73
3.7.2 ICR (Interrupt Control Register) ................................................................................................... 75
3.7.3 SSP (System Stack Pointer) ........................................................................................................ 77
3.7.4 Interrupt Stack ............................................................................................................................. 78
3.7.5 TBR (Table Base Register) ......................................................................................................... 79
3.7.6 EIT Vector Table .......................................................................................................................... 80
3.7.7 Multiple EIT Processing ............................................................................................................... 84
3.7.8 Operations ................................................................................................................................... 86
3.8 Operating Modes .............................................................................................................................. 90
3.8.1 Bus Modes ................................................................................................................................... 91
3.8.2 Mode Settings .............................................................................................................................. 92
3.9 Reset (Device Initialization) .............................................................................................................. 94
3.9.1 Reset Levels ................................................................................................................................ 95

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3.9.2 Reset Sources ............................................................................................................................. 96
3.9.3 Reset Sequence .......................................................................................................................... 98
3.9.4 Oscillation Stabilization Wait Time .............................................................................................. 99
3.9.5 Reset Operation Modes ............................................................................................................. 102
3.10 Clock Generation Control ............................................................................................................... 104
3.10.1 PLL Controls .............................................................................................................................. 105
3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .................................................... 106
3.10.3 Clock Distribution ....................................................................................................................... 108
3.10.4 Clock Division ............................................................................................................................ 110
3.10.5 Block Diagram of Clock Generation Controller .......................................................................... 111
3.10.6 Register of Clock Generation Controller .................................................................................... 112
3.10.7 Peripheral Circuits of Clock Controller ....................................................................................... 129
3.11 Device State Control ....................................................................................................................... 133
3.11.1 Device States and State Transitions ......................................................................................... 134
3.11.2 Low-power Consumption Modes ............................................................................................... 138
3.12 Watch Timer ................................................................................................................................... 143
3.13 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 149
3.14 Peripheral Stop Control .................................................................................................................. 155
CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................ 161
4.1 Overview of the External Bus Interface .......................................................................................... 162
4.2 External Bus Interface Registers .................................................................................................... 167
4.2.1 ASR0 to ASR3 (Area Select Register) ...................................................................................... 168
4.2.2 ACR0 to ACR7 (Area Configuration Registers) ......................................................................... 169
4.2.3 AWR0 to AWR3 (Area Wait Register) ....................................................................................... 175
4.2.4 IOWR0 to IOWR3 (I/O Wait Registers for DMAC) ..................................................................... 181
4.2.5 Chip Select Enable Register (CSER) ........................................................................................ 183
4.2.6 TCR (Terminal and Timing Control Register) ............................................................................ 184
4.3 Setting Example of the Chip Select Area ........................................................................................ 186
4.4 Byte Ordering (Endian) and Bus Access ........................................................................................ 188
4.4.1 Relationship Between Data Bus Widths and Control Signals .................................................... 189
4.4.2 Big Endian Bus Access ............................................................................................................. 190
4.4.3 Little Endian Bus Access ........................................................................................................... 197
4.4.4 External Access ......................................................................................................................... 201
4.5 Ordinary Bus Interface .................................................................................................................... 205
4.6 Address/data Multiplex Interface .................................................................................................... 215
4.7 Prefetch Operation .......................................................................................................................... 218
4.8 DMA Access Operation .................................................................................................................. 222
4.9 Bus Arbitration ................................................................................................................................ 228
4.10 Procedure for Setting a Register .................................................................................................... 230
CHAPTER 5 I/O PORT .................................................................................................. 231
5.1 Overview of the I/O Port ................................................................................................................. 232
5.2 I/O Port Registers ........................................................................................................................... 234
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ................................. 245
6.1 8/16-bit Up/Down Counters/Timers ................................................................................................ 246

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6.1.1 Overview of 8/16-bit Up/Down Counters/Timers ....................................................................... 247
6.1.2 8/16-bit Up/Down Counters/Timer Registers ............................................................................. 252
6.1.3 Operation of the 8/16-bit Up/Down Counters/Timers ................................................................ 259
6.2 U-TIMER ......................................................................................................................................... 268
6.2.1 Overview of the U-TIMER .......................................................................................................... 269
6.2.2 U-TIMER Registers ................................................................................................................... 270
6.2.3 Operation of the U-TIMER ......................................................................................................... 275
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER ............. 277
7.1 16-bit Free-Running Timer .............................................................................................................. 278
7.1.1 Structure of the 16-bit Free-Running Timer ............................................................................... 279
7.1.2 16-bit Free-Running Timer Registers ........................................................................................ 280
7.1.3 Operation of the 16-bit Free-Running Timer .............................................................................. 284
7.2 16-bit Reload Timer ........................................................................................................................ 286
7.2.1 Structure of the 16-bit Reload Timer ......................................................................................... 287
7.2.2 16-bit Reload Timer Register ..................................................................................................... 289
7.2.3 Operation of the 16-bit Reload Register .................................................................................... 292
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ...................... 297
8.1 Overview of the PPG Timer ............................................................................................................ 298
8.2 PPG Timer Registers ...................................................................................................................... 302
8.2.1 Control Status Register ............................................................................................................. 303
8.2.2 PPG Cycle Setting Register (PCSR) ......................................................................................... 307
8.2.3 PPG Duty Setting Register (PDUT) ........................................................................................... 308
8.2.4 PPG Timer Register (PTMR) ..................................................................................................... 309
8.2.5 General Control Register 10 ...................................................................................................... 310
8.2.6 General Control Register 20 ...................................................................................................... 313
8.3 Operation of the PPG Timer ........................................................................................................... 314
8.3.1 Timing Charts for PWM Operation ............................................................................................ 315
8.3.2 Timing Charts for One-Shot Operation ...................................................................................... 317
8.3.3 Interrupt Sources and Timing Chart (with PPG output set for ordinary polarity) ........................ 318
8.3.4 Examples of Methods of All-L and All-H PPG Output ................................................................ 319
8.3.5 Activation of Multiple Channels Using the General Control Register ........................................ 320
CHAPTER 9 INTERRUPT CONTROLLER ................................................................... 323
9.1 Overview of the Interrupt Controller ................................................................................................ 324
9.2 Interrupt Controller Registers .......................................................................................................... 328
9.2.1 Interrupt Control Register (ICR) ................................................................................................. 329
9.2.2 Hold request cancellation request register (HRCL) ................................................................... 331
9.3 Operation of the Interrupt Controller ............................................................................................... 332
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 341
10.1 Overview of the External Interrupt and NMI Controller ................................................................... 342
10.2 External Interrupt and NMI Controller Registers ............................................................................. 344
10.2.1 Enable Interrupt Request Register (ENIRn) .............................................................................. 345
10.2.2 External Interrupt Request Register (EIRRn) ............................................................................ 346
10.2.3 External Level Register (ELVRn) ............................................................................................... 347

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10.3 Operation of the External Interrupt and NMI Controller .................................................................. 348
CHAPTER 11 REALOS-RELATED HARDWARE .......................................................... 351
11.1 Delayed Interrupt Module ............................................................................................................... 352
11.1.1 Overview of the Delayed Interrupt Module ................................................................................ 353
11.1.2 Delayed Interrupt Module Registers .......................................................................................... 354
11.1.3 Operation of the Delayed Interrupt Module ............................................................................... 355
11.2 Bit Search Module .......................................................................................................................... 356
11.2.1 Overview of the Bit Search Module ........................................................................................... 357
11.2.2 Bit Search Module Registers ..................................................................................................... 358
11.2.3 Operation of the Bit Search Module .......................................................................................... 360
CHAPTER 12 A/D CONVERTER .................................................................................... 363
12.1 Overview of the A/D Converter ....................................................................................................... 364
12.2 A/D Converter Registers ................................................................................................................. 366
12.2.1 Control Status Register (ADCS1) .............................................................................................. 367
12.2.2 Control Status Register (ADCS2) .............................................................................................. 370
12.2.3 Conversion Time Setting Register (ADCT) ................................................................................ 373
12.2.4 Data Registers (ADTHx and ADTLx) ......................................................................................... 375
12.3 Operation of the A/D Converter ...................................................................................................... 376
CHAPTER 13 8-BIT D/A CONVERTER .......................................................................... 379
13.1 Overview of the 8-bit D/A Converter ............................................................................................... 380
13.2 8-bit D/A Converter Register ........................................................................................................... 382
13.3 8-bit D/A Converter Operation ........................................................................................................ 384
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE,
AND OUTPUT COMPARE MODULE ...................................................... 385
14.1 UART .............................................................................................................................................. 386
14.1.1 Features of the UART ................................................................................................................ 387
14.1.2 UART Registers ......................................................................................................................... 390
14.1.3 Operation of the UART .............................................................................................................. 399
14.1.4 Example of using the UART ...................................................................................................... 407
14.2 Serial I/O Interface (SIO) ................................................................................................................ 410
14.2.1 Overview of the Serial I/O Interface (SIO) ................................................................................. 411
14.2.2 Serial I/O Interface Registers .................................................................................................... 413
14.2.3 Operation of the Serial I/O Interface (SIO) ................................................................................ 419
14.3 Input Capture Module ..................................................................................................................... 425
14.3.1 Overview of the Input Capture Module ...................................................................................... 426
14.3.2 Input Capture Module Registers ................................................................................................ 428
14.3.3 Input Capture Operation ............................................................................................................ 430
14.4 Output Compare ............................................................................................................................. 431
14.4.1 Features of the Output Compare Module .................................................................................. 432
14.4.2 Output Compare Module Registers ........................................................................................... 434
14.4.3 Operation of the Output Compare Module ................................................................................ 437

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CHAPTER 15 I2C INTERFACE ....................................................................................... 439
15.1 Overview of the I2C Interface .......................................................................................................... 440
15.2 I2C Interface Registers ................................................................................................................... 444
15.2.1 Bus Status Register (IBSR) ....................................................................................................... 445
15.2.2 Bus Control Register (IBCR) ..................................................................................................... 448
15.2.3 Clock Control Register (ICCR) .................................................................................................. 455
15.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 457
15.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 458
15.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 460
15.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 461
15.2.8 Data Register (IDAR) ................................................................................................................. 462
15.2.9 Clock Disable Register (IDBL) ................................................................................................... 463
15.3 Explanation of I2C Interface Operation ........................................................................................... 464
15.4 Operation Flowcharts ...................................................................................................................... 468
CHAPTER 16 DMA CONTROLLER (DMAC) .................................................................. 471
16.1 Overview ......................................................................................................................................... 472
16.2 Detailed Explanation of Registers ................................................................................................... 475
16.2.1 DMAC ch0 to ch4 Control/Status Registers A ........................................................................... 476
16.2.2 DMAC ch0 to ch4 Control/Status Registers B ........................................................................... 482
16.2.3 DMAC ch0 to ch4 Transfer Source/Transfer Destination Address Setting Registers ................ 488
16.2.4 DMAC ch0 to ch4 DMAC All-Channel Control Register ............................................................ 490
16.3 Explanation of Operation ................................................................................................................ 492
16.3.1 Overview of Operation ............................................................................................................... 493
16.3.2 Setting a Transfer Request ........................................................................................................ 496
16.3.3 Transfer Sequence .................................................................................................................... 497
16.3.4 General Aspects of DMA Transfer ............................................................................................. 501
16.3.5 Addressing Mode ....................................................................................................................... 503
16.3.6 Data Types ................................................................................................................................ 504
16.3.7 Transfer Count Control .............................................................................................................. 505
16.3.8 CPU Control .............................................................................................................................. 506
16.3.9 Hold Arbitration .......................................................................................................................... 507
16.3.10 Operation from Starting to End/Stopping ................................................................................... 508
16.3.11 Transfer Request Acceptance and Transfer .............................................................................. 509
16.3.12 Clearing Peripheral Interrupts by DMA ...................................................................................... 510
16.3.13 Temporary Stopping .................................................................................................................. 511
16.3.14 Operation End/Stopping ............................................................................................................ 512
16.3.15 Stopping Due To an Error .......................................................................................................... 513
16.3.16 DMAC Interrupt Control ............................................................................................................. 514
16.3.17 DMA Transfer during Sleep ....................................................................................................... 515
16.3.18 Channel Selection and Control .................................................................................................. 516
16.3.19 Supplement on External Pin and Internal Operation Timing ..................................................... 518
16.4 Operation Flowcharts ...................................................................................................................... 522
16.5 Data Path ........................................................................................................................................ 525
16.6 DMA External Interface ................................................................................................................... 529

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CHAPTER 17 FLASH MEMORY ..................................................................................... 533
17.1 Outline of Flash Memory ................................................................................................................. 534
17.2 Flash Memory Registers ................................................................................................................. 539
17.2.1 Flash Control/Status Register (FLCR) (CPU mode) .................................................................. 540
17.2.2 Flash Memory Wait Register (FLWC) ........................................................................................ 543
17.3 Explanation of Flash Memory Operation ........................................................................................ 545
17.4 Automatic Algorithm of Flash Memory ............................................................................................ 547
17.4.1 Command Sequence ................................................................................................................. 548
17.4.2 Checking the Automatic Algorithm Operating Status ................................................................ 552
17.5 Writing to and Erasing Flash Memory ............................................................................................. 557
17.5.1 Read/Reset Status .................................................................................................................... 558
17.5.2 Data Writing ............................................................................................................................... 559
17.5.3 Data Erasure (Chip Erasure) ..................................................................................................... 561
17.5.4 Data Erasure (Sector Erasure) .................................................................................................. 562
17.5.5 Temporary Sector Erase Stop ................................................................................................... 564
17.5.6 Sector Erase Restart ................................................................................................................. 565
CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION
................................................................................................................... 567
18.1 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection ......... 568
18.2 Pins Used for Fujitsu Standard Serial Onboard Writing .................................................................. 569
18.3 Examples of Serial Programming Connection ................................................................................ 570
18.4 System Configuration of Flash Microcontroller Programmer .......................................................... 572
18.5 Other Precautionary Information ..................................................................................................... 573
CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM
ACCESS RESTRICTION FUNCTIONS .................................................... 575
19.1 Overview ......................................................................................................................................... 576
19.2 Explanation of Registers ................................................................................................................. 577
19.3 Explanation of Operation ................................................................................................................ 579
APPENDIX ......................................................................................................................... 581
APPENDIX A I/O Map ................................................................................................................................ 582
APPENDIX B Interrupt Vector .................................................................................................................... 594
APPENDIX C Pin States in Each CPU State .............................................................................................. 597
APPENDIX D Instruction Lists .................................................................................................................... 603
INDEX................................................................................................................................... 619

xi
Main changes in this edition
Page Changes (For details, refer to main body.)
- - Products were changed.
(MB91F353A/352A/353A →MB91F353A/351A/352A/353A)
(MB91F35 →MB91F353A/351A/352A/353A)
(MB91F35A →MB91F353A/351A/352A/353A)
(MB91F355A/353A →MB91F353A/F355A/F356B/F357B)
(MB91F355A/355A/354A →MB91F355A/355A/354A/F356B/F357B)
- - "flash memories" were changed.
(256 KB flash memories →256K bytes/128K bytes flash memories)
(512 KB flash memories →512K bytes/256K bytes flash memories)
- - The following terms were unified.
(FR series →FR family)
(FR30 series →FR30 family)
3 1.1 Features "Table 1.1-1 Internal Memory Details" was changed.
(The column for MB91351A was added.)
(The columns for MB91F356B and MB91F357B were added.)
5 1.1 Features "■Other Features" was changed.
(LQFP-176 (lead pitch 0.50 mm) →MB91F355A/F356B/F357B/355A/354A:
LQFP-176 (lead pitch 0.50 mm))
6 1.1 Features "Table 1.1-2 Comparison of Functions: Internal Memory (Products whose
Memory Capacity is to be Extended and the Configuration of Memory are Cur-
rently under Study.)" was changed.
(The column for MB91351A was added.)
7, 8 1.2 Block Diagram "Figure 1.2-1 MB91F353A/353A/352A/351A Block Diagram" was changed.
"Figure 1.2-2 MB91355A/354A/F355A/F356B/F357B Block Diagram" was
changed.
12 1.4 Pin Layout "■Pin layout of the MB91352A and MB91F353A (LQFP-120)" was deleted.
46 3.1 Memory Space "Figure 3.1-1 MB91F355A, MB91355A, MB91F353A, MB91353A and
MB95F357B Memory Maps" was changed.
(Internal ROM →Internal RAM)
47 "Figure 3.1-2 MB91351A Memory Map " was added.
"Figure 3.1-3 MB91354A and MB91352A Memory Map" was changed.
(Internal ROM →Internal RAM)
48 "Figure 3.1-4 MB91F356B Memory Map" was added.

xii
48 3.1 Memory Space "■Memory Map" was changed.
(For the MB91V350A, a 512K-byte internal ROM area is used as emulation
RAM for the MB91355A, F355A, 353A, and F353A memory map. In addi-
tion, the instruction internal RAM is extended from 8 KB to 16 KB. →For the
MB91V350A, with the memory map of the MB91355A/F355A/353A/F353A/
F357B, the 512K bytes area of the internal ROM, and with the memory map of
the MB91F356B, the 256K bytes area of the internal ROM, is the emulation
RAM. In addition, internal RAM(Instruction) is extended from 8K bytes to16K
bytes.)
174 4.2.2 ACR0 to ACR7
(Area Configuration Reg-
isters)
"Notes:" was changed.
"(Set both ASR and ACR at the same time using word access. When accessing
ASR and ACR using half word, please set ACR after setting ASR.)" was
added.
230 4.10 Procedure for Setting
a Register "■Procedure for Setting the External Bus Interface" was changed.
238
to
244
5.2 I/O Port Registers "Table 5.2-1 Initial Values and Functions of the Port Function Registers
(PFRs)" was changed.
("*2" was deleted.)
246 6.1 8/16-bit Up/Down
Counters/Timers "■Overview of the 8/16-bit Up/Down Counters/Timers" was changed.
(The MB91F355A/355A/354A/V350A→The MB91F355A/355A/354A/
F356B/F357B)
271 6.2.2 U-TIMER Registers "■Reload Register (UTIMR)" was changed.
("Note:" was added.)
275 6.2.3 Operation of the U-
TIMER "■Calculation of Baud Rate" was changed. ("Note:" was added.)
348 10.3 Operation of the
External Interrupt and
NMI Controller
"■Operating Procedure for an External Interrupt" was changed.
("1. Terminal and general-purpose I/O port used as external interrupt input are
set to input port." was added.)
384 13.3 8-bit D/A Converter
Operation "Table 13.3-1 Logical Expressions for D/A Converter Output Voltage" was changed.
(Values specified in DADR1 DADR2 DADR3 →Values specified in DADR0
DADR1 DADR2)
413, 414 14.2.2 Serial I/O Interface
Registers "[Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode)" was changed.
450 15.2.2 Bus Control Regis-
ter (IBCR) "[Bit 12] MSS (Master Slave Select)" was changed. ("Note:" was changed.)
451
to
454
"■Bus Control Register (IBCR)" was changed.
("Note:" was changed.)
479 16.2.1 DMAC ch0 to ch4
Control/Status Registers A "■[Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer Source Selection" was changed.
Page Changes (For details, refer to main body.)

xiii
The vertical lines marked in the left side of the page show the changes.
494 16.3.1 Overview of Opera-
tion "●Fly-by transfer (I/O →memory)" was changed.
(Access areas used for MB91350A fly-by transfer must be external areas. →
Access areas used for MB91F355A/F356B/F357B/355A fly-by transfer must
be external areas.)
534 17.1 Outline of Flash
Memory "Summary of 17.1 Outline of Flash Memory" was changed.
536 "Figure 17.1-3 Memory Map of MB91F356B Flash Memory" was added.
537, 538 "■Sector Address Table of Flash Memory" was changed.
544 17.2.2 Flash Memory Wait
Register (FLWC) "[Bits 2 to 0] WTC2, WTC1, and WTC0 (wait cycle bits)" was changed.
559 17.5.2 Data Writing "■ How to Specify Address" was changed.
568 18.1 Basic Configuration
of MB91F355A/F353A/
F356B/F357B
Serial Programming Con-
nection
"■Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Pro-
gramming Connection" was changed.
("Either a program operating in single-chip mode or a program operating in
internal ROM external bus mode is selected to write." was added.)
569 18.2 Pins Used for Fujitsu
Standard Serial Onboard
Writing
"Table 18.2-1 Function of Pins Used for Fujitsu Standard Serial Onboard Writ-
ing" was changed.
573 18.5 Other Precautionary
Information "●Oscillation Clock Frequency" was changed.
(4.0 MHz and 12.0 MHz →10.0 MHz and 12.5 MHz)
"●Port State for Write Operations on Flash Memory" was changed.
(reset state except →initial state in the single-chip mode except)
584 APPENDIX A I/O Map "Address 00009CHof Table A-1 I/O Map" was changed.
("*1" was added.)
Page Changes (For details, refer to main body.)

xiv

1
CHAPTER 1
OVERVIEW
The FR family is a standard single-chip microcontroller
that has a 32-bit high-performance RISC CPU as well as
internal I/O resources and bus control configuration for
embedded controllers that require high-performance or
high-speed CPU processing.
This model is an FR60 family model that is based on the
FR30/40 family of CPUs, and offers enhanced bus
access. The FR family is a single-chip microcontroller
with built-in peripheral resources.
1.1 Features
1.2 Block Diagram
1.3 Package Dimensions
1.4 Pin Layout
1.5 List of Pin Functions
1.6 Input-output Circuit Forms

2
CHAPTER 1 OVERVIEW
1.1 Features
This section describes the features of the FR60 family microcontrollers.
■FR CPU Features
• 32-bit RISC, load/store architecture, five stages pipeline
• Maximum operating frequency of 50 MHz [PLL used: Oscillation at 12.5 MHz]
• 16-bit fixed-length instructions (basic instructions), one instruction per cycle
• Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.--instructions
appropriate for embedded applications
• Function entry and exit instructions, multi load/store instructions of register content--instructions
compatible with high-level languages
• Register interlock function to facilitate assembly-language coding
• Built-in multiplier/instruction-level support
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
• Interrupts (saving of PC and PS): 6 cycles, 16 priority levels
• Harvard architecture enabling simultaneous execution of both program access and data access
• Instructions compatible with the FR family
■Bus Interface
• Maximum operating frequency of 25 MHz
• 24-bit address full output (16M bytes space) capability
(21-bit address full output (2M bytes space) capability: MB91F353A/351A/352A/353A)
• 8/16-bit data output
• Prefetch buffer installed
• Use of unused data/address pins as general-purpose I/O ports
• Totally independent 4-area chip select outputs that can be configured in units as small as 64K bytes
• Supported interface for each type of memory
SRAM and ROM/FLASH
Page mode FLASHROM and page mode ROM interface
• Basic bus cycle (2 cycles)
• Automatic wait cycle generator that can be programmed for each area and can insert waits.
• External wait cycle using RDY input
• DMA support of fly-by transfer capable of wait control for independent I/O
(The MB91F353A/351A/352A/353A does not support fly-by transfer.)