Fujitsu FR Family FR60 Lite User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR60
32-BIT MICROCONTROLLER
MB91350A Series
HARDWARE MANUAL
CM71-10121-3E

FUJITSU LIMITED
FR60
32-BIT MICROCONTROLLER
MB91350A Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

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CONTENTS
■Objectives and Intended Reader
The MB91350A series is one of the FR60 family of microcontrollers. The FR60 family of microcontrollers
is based on the FR30/40 family of CPUs, which use a 32-bit high-performance RISC CPU as the core CPU.
The FR60 family offers enhanced bus access. The MB91350A series is a single-chip microcontroller with
built-in peripheral resources. The MB91350A series is ideal for embedded control applications that require
high-performance or high-speed CPU processing.
This manual is intended for engineers who will develop products using the MB91350A series and describes
the functions and operations of the MB91350A series. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
Note : FR, which is an abbreviation of FUJITSU RISC controller, is a product of FUJITSU LIMITED.
■Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■License
Purchase of Fujitsu I2C components conveys a licence under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■Organization of This Manual
This manual consists of the following 19 chapters and an appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information required to understand the MB91350A series. It covers features
and dimensions, and presents a block diagram of the MB91350A series.
CHAPTER 2 HANDLING THE DEVICE
This chapter provides precautions on handling the device.
CHAPTER 3 CPU AND CONTROL UNITS
This chapter provides basic information required to understand the MB91350A series core CPU
functions. It covers architecture, specifications, and instructions.
CHAPTER 4 EXTERNAL BUS INTERFACE
This chapter describes basic items related to the external bus interface, register configuration/functions,
bus operation, bus timing, and procedures for setting the registers.
CHAPTER 5 I/O PORT
This chapter describes the I/O ports and the configuration and functions of registers.

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CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
This chapter outlines the 8/16-bit up/down counter/timer and U-TIMER and explains the configuration
and functions of the registers and timer operations.
CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER
This chapter outlines the 16-bit free-running timer and 16-bit reload timer and explains the
configuration and functions of the registers and timer operations.
CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER
This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the
register configuration and functions and the timer operations.
CHAPTER 9 INTERRUPT CONTROLLER
This chapter describes the overview of the interrupt controller, the configuration and functions of
registers, and interrupt controller operation.
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter outlines the external interrupt/NMI controller and explains the configuration and functions
of the registers and operations of the external interrupt/NMI controller.
CHAPTER 11 REALOS-RELATED HARDWARE
This chapter outlines the delayed interrupt module and bit search module, and explains the
configuration and functions of registers and operations.
CHAPTER 12 A/D CONVERTER
This chapter outlines the A/D converter and explains the configuration and functions of registers and
the A/D converter operations.
CHAPTER 13 8-BIT D/A CONVERTER
This chapter gives an overview of the 8-bit D/A converter, register configuration and functions, and 8-
bit D/A converter operation.
CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND
OUTPUT COMPARE MODULE
This chapter outlines the UART, SIO, input capture, and output compare, and explains the configuration
and functions of registers. It also explains UART, SIO, input capture, and output compare operations.
CHAPTER 15 I2C INTERFACE
This chapter describes the overview of the I2C interface, the configuration and functions of registers,
and I2C interface operation.
CHAPTER 16 DMA CONTROLLER (DMAC)
This chapter describes the overview of the DMAC, the configuration and functions of registers, and
DMAC operation.
CHAPTER 17 FLASH MEMORY
This chapter provides an outline of flash memory and explains its register configuration, register
functions, and operations.
CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION
This chapter describes the serial onboard writing connection (Fujitsu standard) using the AF220/AF210/
AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation.

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CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS
RESTRICTION FUNCTIONS
This chapter outlines a function that restricts access to data internal RAM and instruction internal RAM.
It also explains the configuration and functions of registers and internal RAM operations.
APPENDIX
This appendix consists of the following parts: I/O map, interrupt vectors, pin state for each CPU state,
and the instruction lists.

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Copyright ©2003-2007 FUJITSU LIMITED All rights reserved
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such
information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection
with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Features .............................................................................................................................................. 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimensions .......................................................................................................................... 9
1.4 Pin Layout ......................................................................................................................................... 11
1.5 List of Pin Functions ......................................................................................................................... 13
1.6 Input-output Circuit Forms ................................................................................................................ 27
CHAPTER 2 HANDLING THE DEVICE .......................................................................... 31
2.1 Precautions on Handling the Device ................................................................................................. 32
2.2 Precautions on Using the Little-Endian Area .................................................................................... 37
2.2.1 C Compiler (fcc911) ..................................................................................................................... 38
2.2.2 Assembler (fasm911) .................................................................................................................. 41
2.2.3 Linker (flnk911) ............................................................................................................................ 42
2.2.4 Debuggers (sim911, eml911, and mon911) ................................................................................ 43
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 45
3.1 Memory Space .................................................................................................................................. 46
3.2 Internal Architecture .......................................................................................................................... 49
3.2.1 Internal Architecture .................................................................................................................... 50
3.2.2 Overview of Instructions .............................................................................................................. 53
3.3 Programming Model ......................................................................................................................... 55
3.3.1 General-Purpose Registers ......................................................................................................... 56
3.3.2 Dedicated Registers .................................................................................................................... 57
3.4 Data Configuration ............................................................................................................................ 64
3.5 Memory Map ..................................................................................................................................... 66
3.6 Branch Instructions ........................................................................................................................... 67
3.6.1 Operations with a Delay Slot ....................................................................................................... 68
3.6.2 Operation without Delay Slot ....................................................................................................... 71
3.7 EIT (Exception, Interrupt, and Trap) ................................................................................................. 72
3.7.1 EIT Interrupt Levels ..................................................................................................................... 73
3.7.2 ICR (Interrupt Control Register) ................................................................................................... 75
3.7.3 SSP (System Stack Pointer) ........................................................................................................ 77
3.7.4 Interrupt Stack ............................................................................................................................. 78
3.7.5 TBR (Table Base Register) ......................................................................................................... 79
3.7.6 EIT Vector Table .......................................................................................................................... 80
3.7.7 Multiple EIT Processing ............................................................................................................... 84
3.7.8 Operations ................................................................................................................................... 86
3.8 Operating Modes .............................................................................................................................. 90
3.8.1 Bus Modes ................................................................................................................................... 91
3.8.2 Mode Settings .............................................................................................................................. 92
3.9 Reset (Device Initialization) .............................................................................................................. 94
3.9.1 Reset Levels ................................................................................................................................ 95

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3.9.2 Reset Sources ............................................................................................................................. 96
3.9.3 Reset Sequence .......................................................................................................................... 98
3.9.4 Oscillation Stabilization Wait Time .............................................................................................. 99
3.9.5 Reset Operation Modes ............................................................................................................. 102
3.10 Clock Generation Control ............................................................................................................... 104
3.10.1 PLL Controls .............................................................................................................................. 105
3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .................................................... 106
3.10.3 Clock Distribution ....................................................................................................................... 108
3.10.4 Clock Division ............................................................................................................................ 110
3.10.5 Block Diagram of Clock Generation Controller .......................................................................... 111
3.10.6 Register of Clock Generation Controller .................................................................................... 112
3.10.7 Peripheral Circuits of Clock Controller ....................................................................................... 129
3.11 Device State Control ....................................................................................................................... 133
3.11.1 Device States and State Transitions ......................................................................................... 134
3.11.2 Low-power Consumption Modes ............................................................................................... 138
3.12 Watch Timer ................................................................................................................................... 143
3.13 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 149
3.14 Peripheral Stop Control .................................................................................................................. 155
CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................ 161
4.1 Overview of the External Bus Interface .......................................................................................... 162
4.2 External Bus Interface Registers .................................................................................................... 167
4.2.1 ASR0 to ASR3 (Area Select Register) ...................................................................................... 168
4.2.2 ACR0 to ACR7 (Area Configuration Registers) ......................................................................... 169
4.2.3 AWR0 to AWR3 (Area Wait Register) ....................................................................................... 175
4.2.4 IOWR0 to IOWR3 (I/O Wait Registers for DMAC) ..................................................................... 181
4.2.5 Chip Select Enable Register (CSER) ........................................................................................ 183
4.2.6 TCR (Terminal and Timing Control Register) ............................................................................ 184
4.3 Setting Example of the Chip Select Area ........................................................................................ 186
4.4 Byte Ordering (Endian) and Bus Access ........................................................................................ 188
4.4.1 Relationship Between Data Bus Widths and Control Signals .................................................... 189
4.4.2 Big Endian Bus Access ............................................................................................................. 190
4.4.3 Little Endian Bus Access ........................................................................................................... 197
4.4.4 External Access ......................................................................................................................... 201
4.5 Ordinary Bus Interface .................................................................................................................... 205
4.6 Address/data Multiplex Interface .................................................................................................... 215
4.7 Prefetch Operation .......................................................................................................................... 218
4.8 DMA Access Operation .................................................................................................................. 222
4.9 Bus Arbitration ................................................................................................................................ 228
4.10 Procedure for Setting a Register .................................................................................................... 230
CHAPTER 5 I/O PORT .................................................................................................. 231
5.1 Overview of the I/O Port ................................................................................................................. 232
5.2 I/O Port Registers ........................................................................................................................... 234
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ................................. 245
6.1 8/16-bit Up/Down Counters/Timers ................................................................................................ 246