Redpine Signals RS9110-N-11-02 Quick setup guide

Redpine Signals, Inc. Proprietary and Confidential
RS9110-N-11-02
Module Integration Guide
V
Ve er rs si io on n 1 1. .3 39 9
September 26t 2011
Redpine Signals, Inc
.
2107 N. First Street, #6 0
San Jose, CA 95131.
Tel: (40 ) 74 -33 5
Fax: (40 ) 705-2019
Email: [e-mail]
Website: www.redpinesignals.com

Redpine Signals Inc. Proprietary and Confidential Page 2
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About t is Document:
The RS9110-N-11-02 is an 02.11n single-stream module with built-in
MAC/BBP, RF and PA, and front-end components. It interfaces to a host
processor through an SDIO or SPI interface. This document provides
information that may be used while integrating the module into an end
solution.

Redpine Signals Inc. Proprietary and Confidential Page 3
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Table of Contents
1Reference Sc ematics ....................................................... 4
1.1 SDIO Interface ................................................................... 4
1.2 SPI Interface...................................................................... 5
2Bill of Materials ................................................................. 7
2.1 SDIO Interface Integration ................................................. 7
2.2 SPI Interface Integration.................................................... 8
3Recommended RS9110-N-11-02 PCB Landing Pattern .... 10
4Circuit and Layout Guidelines .......................................... 11
5C ip Antenna Layout Recommendations.......................... 13
5.1 Antenna Matc ing Network ............................................... 14
6Reference Oscillator Specifications ................................. 16
6.1 List of Recommended Crystal Oscillators ........................... 17
7Recommended Specifications for Sc ottky Diode ............ 18
7.1 Recommended Parts ......................................................... 18
8Sample Layout................................................................. 19
8.1 Layer 2 ............................................................................. 20
8.2 Layer 3 ............................................................................. 20
8.3 Bottom Layer.................................................................... 21
8.4 Component Placement ...................................................... 21
9Appendix ......................................................................... 22
9.1 SDIO connectivity for Windows OS.................................... 22

Redpine Signals, Inc. Proprietary and Confidential
1Reference Sc ematics
The following is a reference circuit schematic of an Evaluation Board using RS-9110-N-11-02 WLAN Module. The schematics
show both SDIO and SPI Host Interface options. The layout corresponding to this schematic is also shown in this document
as a reference
1.1 SDIO Interface
C3
0.1uF
PSPI_CSN1
PSPI_MISO
PSPI_MOSI
PSPI_CLK
Microwave switch is used for evaluating
the standalone Transmit/Receive
performance of the WLAN module by
providing direct connectivity to Signal
generator/Analyzer through RF cable
D1LED
UART2_IN
SLEE P_CLK _X1SLEE P_CLK _X1
Z1 , Z2, Z3 form the tuning network
for matching the impedance of the
Antenna. The values depend upon
the layout. In case tuning network is
not implemented Z1 should be
placed as .2pF as default
XTAL_EN
Redpine Signals Confidential
C11
0.1uF
11 2
2
FB4
BEAD
VDD_EXT
C6
1uF
VRF33
11 2
2
FB2
BEAD PSPI_MISO
GPIO_0
BT_PRIORITY
PSPI_MOSI
VIN33
SPI Serial Flash
NOTE::If required C7 can be increased to
22uF for furt er improving t e Transmit
EVM
WLAN_ACTIVE
BT_ACTIVE
PSPI_CLK
CE#
1SCK
6SI
5SO
2
VDD 8
HOLD 7
WP# 3
VSS 4
U3
SST25VF016B-75-4I-QAF-T
L1
4.7uH
VDD_EXT
C14
10uF
PSPI_CSN1
VDD_EXT
OPTIONAL
SDIO_DATA0
DVDD33
VMOD
SDIO_CMD SDIO_CLK SDIO_DATA3
C8
0.1uF
SDIO_DATA2 SDIO_DATA1
VRF33
Power Supply Filter Section
C10
0.1uF
Tantalum
R8
4.7K
Tantalum
11 2
2
FB3
BEAD
11 2
2
FB5
BEAD
Mating Connector Part No::MXHS83QH3000
C13
0.1uF
ANT1 1 ANT2
2
ANT1
ANT-2.45G
I2C_SDA
ANTIN 3 ANTOUT
4
GND
1GND 2
GND
5GND 6
J2
MM8430-2610RA1
C5
8.2pF
I2C_SCL
R3 820E
CLK_REF
UART1_RTS
UART1_CTS
XTAL_IP_EN
GPIO_1
RESET_n
HOST_WAKEUP_INT
UART1_OUT
UART1_IN
UART2_OUT
VMOD
C4
10uF
802.11bgn WLAN Module
C12
22uF(CASE B)
VDD_EXT
C7
10uF(CASE B) RESET_n
C9
0.1uF
VIN33
RESET Circuitry
R7 100K
CLK_REF
Make:: TXC
OE 1 GND
2
OUT
3VDD 4
U1
7C40000192
C1
2.2uF
XTAL_ENXTAL_ENXTAL_ENXTAL_EN
R1 33E
VRF28
11 2
2
FB1
BEAD
Reference Clock Circuitry
TP1
Place Z1-Z3 Close
together and near to
ANT1
SDIO_CLK
SDIO_DATA1
SDIO_DATA3
SDIO_DATA0
CD/DAT3
1CMD 2
VSS1
3VDD 4
CLK
5VSS2 6
DAT0
7DAT1 8
DAT2
9
J1
SDIO Interface Connector
SDIO_DATA2
SDIO_CMD
VIN33
C2
10uF
R25**
SLEE P_CLK _X2
R25** v alueshould be adjustedbased
on driver output impedanceand PCB
TraceImpedance,,(33E isNominal)
TDO
R61K
Z1
TBD
Z3
TBD DVDD33
Z2
TBD
Title
Size DocumentNumber Rev
Date: Sheet of
<Doc>
RS9110-N-11-02 SDIO - Reference Sc ematics
Custom
2 2Tuesday, September 20,2011
R51K
50 Ohm RF li ne
CMS02D2
R41K
Note:
Microwave coaxial
connector with s witch
Rev6.1
Ver6.1
VRF28
RF Out Circuitry
AGND
56
RF_OUT
57
AGND
58
GND 25
NC
1
DVDD33 17
PSPI_CS N0 40
LED_ON 24
MODE_SEL_1
51
VRF28
52
XTAL_EN 23
REF_CLK
14
PSPI_CSN1
46
SLEE P_CLK _X1 35 SLEE P_CLK _X2 34
I2C_SCL
6
I2C_SDA
7
GND 30
GND 26
RESETn
15
NC 41
WLAN_ACTIVE 31
BT_PRIORITY 29
SLEE P_CLK _IN 32
HOST_WAKEUP_INT
53
NC 42
VRF33 43 VRF33 44
SDIO_DATA3/SD3
13
SDIO_DATA2/SP I_INTR
12
SDIO_DATA1/SP I_MISO
11
SDIO_DATA0/SP I_MOSI
10
SDIO_CMD/SPI_CS
9
SDIO_CLK/SP I_CLK
8
GPIO_1
55
GND
16
VINBCKDC 27
VINLDOP12 3 39
FBDC1P3 38
VOUTBCKDC1P 3 37
UART2_IN 36
UART1_RTS 22
UART1_CTS 21
UART1_OUT 18
UART1_IN 19
TCK
2
TDI
3
TMS
4
TDO
5
XTAL_EN_IP
54
GPIO_0 28
BT_ACTIVE 33
UART2_OUT 20
PSPI_MISO
47
GND 45
MODE_SEL_0
50
PSPI_CLK
49
PSPI_MOSI
48
U2
RS9110-N-11-02
Figure 1 SDIO Interface Integration
NOTE: Pull up resistors should be present on SDIO CMD & SDIO Data lines according to the section 6.6.5 of SD physical layer
specification, version 2.00

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1.2 SPI Interface
C3
0.1uF
PSPI_CSN1
PSPI_CLK
PSPI_MOSI
PSPI_MISO
Microwave switch is used for evaluating
the standalone Transmit/Receive
performance of the WLAN module by
providing direct connectivity to Signal
generator/Analyzer through RF cable
D1LED
UART2_IN
SLEEP_CLK_X1SLEEP_CLK_X1
Z1 , Z2, Z3 form the tuning network
for matching the impedance of the
Antenna. The values depend upon
the layout. In case tuning network is
not implemented Z1 should be
placed as .2pF as default
XTA L_EN
Redpine Signals Confidential
C11
0.1uF
11 2
2
FB4
BEAD
VDD_EXT
C6
1uF
11 2
2
FB2
BEAD
VRF33
PSPI_MISO
SPI Serial Flash
VIN33
PSPI_MOSI
BT_PRIORITY
GPIO_0
CE#
1SCK
6SI
5SO
2
VDD 8
HOLD 7
WP# 3
VSS 4
U3
SST25VF016B-75-4I-QAF-T
L1
4.7uH
PSPI_CLK
BT_ACTIVE
WLAN_ACTIV E
C14
10uF
VDD_EXT
VDD_EXT
PSPI_CSN1
OPTIONAL
VMOD
DVDD33
SPI_MOSI
C8
0.1uF
SD3 SPI_CLK SPI_CS
C10
0.1uF
Power Supply Filter Section
VRF33
SPI_MISO SPI_INTR
R8
4.7K
Tantalum
11 2
2
FB3
BEAD
11 2
2
FB5
BEAD
Tantalum
C13
0.1uF
Mating Connector Part No::MXHS83QH3000
ANT1 1 ANT2
2
ANT1
ANT-2.45G
ANTIN 3 ANTOUT
4
GND
1GND 2
GND
5GND 6
J2
MM8430-2610RA1
C5
8.2pF
I2C_SDA I2C_SCL
R3 820E
CLK_REF
UART1_RTS
UART1_CTSGPIO_1
XTA L_IP_EN
HOST_WAKEUP_INT
AGND
56
RF_OUT
57
AGND
58
GND 25
NC
1
DVDD33 17
PSPI_CSN0 40
LED_ON 24
MODE_SEL_1
51
VRF28
52
XTA L_EN 23
REF_CLK
14
PSPI_CSN1
46
SLEE P_CLK_X1 35 SLEE P_CLK_X2 34
I2C_SCL
6
I2C_SDA
7
GND 30
GND 26
RESE Tn
15
NC 41
WLAN_ACTIV E 31
BT_PRIORITY 29
SLEE P_CLK_IN 32
HOST_WAKEUP_INT
53
NC 42
VRF33 43 VRF33 44
SDIO_DATA 3/SD3
13
SDIO_DATA 2/SPI_INTR
12
SDIO_DATA 1/SPI_MISO
11
SDIO_DATA 0/SPI_MOSI
10
SDIO_CMD/SPI_CS
9
SDIO_CLK/SP I_CLK
8
GPIO_1
55
GND
16
VINBCKDC 27
VINLDOP123 39
FBDC1P3 38
VOUTB CKDC1P3 37
UART2_IN 36
UART1_RTS 22
UART1_CTS 21
UART1_OUT 18
UART1_IN 19
TCK
2
TDI
3
TMS
4
TDO
5
XTA L_EN_IP
54
GPIO_0 28
BT_ACTIVE 33
UART2_OUT 20
PSPI_MISO
47
GND 45
MODE_SEL_0
50
PSPI_CLK
49
PSPI_MOSI
48
U2
RS9110-N-11-02
UART1_IN
UART1_OUT
UART2_OUT
VMOD
C4
10uF
802.11bgn WLAN Module
C12
22uF(CASE B)
VDD_EXT
C7
10uF(CASE B)
RESET_n
C9
0.1uF
VIN33
R7 100K
RESET Circuitry OPTIONAL
CLK_REF
Make:: TXC
OE 1 GND
2
OUT
3VDD 4
U1
7C40000192
C1
2.2uF
R1 33E
XTA L_ENXTA L_ENXTA L_ENXTA L_EN
VRF28
11 2
2
FB1
BEAD
Reference Clock Circuitry
MODE_SEL_1MODE_SEL_1
TP1
Place Z1-Z3 Close
together and near to
ANT1
SPI_CLK SPI_MISO
SD3
SPI_MOSI
CD/DAT3
1CMD 2
VSS1
3VDD 4
CLK
5VSS2 6
DAT0
7DAT1 8
DAT2
9
J1
SPI Interface Connector
SPI_CS
SPI_INTR
C2
10uF
R25**
VIN33
SLEE P_CLK_X2
NOTE::If required C7 can be increased to
22uF for furt er improving t e Transmit
EVM
R25** value should be adjuste d base d
on driver output im pe dance and PCB
Trace Impe dance,,(33E is Nominal)
TDO
R61K
Z1
TBD
Z3
TBD
Z2
TBD
DVDD33
Title
Size Document Number Rev
Date: Sheet of
<Doc>
RS9110-N-11-02 SPI - Reference Sc ematics
Custom
2 2Monday, September 26, 2011
R51K
CMS02D2
50 Ohm RF line
R2
3.9K to 4.75K
R41K
Note:
RESE T_nRESE T_nRESE T_nRESE T_n
Microwave coaxial
connector with switch
Rev6.1
Ver6.1
FROM HOST
RF Out Circuitry VRF28
Figure 2 SPI Interface Integration

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NOTE on SPI_CS and SPI_CLK: -
Based on the Host SPI configuration, during BOOT UP, SPI Master could be coming up as GPIO pins.In the wake of this possibility, it
may be needed to add a pull up on the SPI_CS and a pull up (CPOL=1)/pull down(CPOL=0) on the SPI_CLK. The value of pull up/ pull
down resistor should follow the recommendations as given on the HOST side.

Redpine Signals Inc. Proprietary and Confidential Page 7
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2Bill of Materials
2.1 SDIO Interface Integration
Item Qty Reference Value Description Jedec Mfg/ Part No
CAPACITORS
1 1 C5 .2pF CER CHP C .2P +-0.25P C0G 0402 25V LF 0402 Murata GRM1555C1H R2CZ01D
2 5 C3,C ,C9,C11,C13 0.1uF CER CHIP C 0.1U 10% X5R 0402 6.3V 0402 Murata GRM155R61A104KA01D
3 1 C1 2.2uF CER CHIP C 2.2U 20% X5R 0402 4V 0402 Murata GRM155R60G225ME15D
4 1 C6 1uF CAP CER 1.0UF 16V 10% X7R 0 05 0 05 Murata GRM21BR71C105KA01L
5 3 C2,C4,C14 10uF CER CHIP C 10U 20% X5R 0 05 10V 0 05 Murata GRM21BR61A106KE19L
6 1 C7 10uF CAP TANTALUM 10UF 6.3V 10% SMD CASE-B AVX TAJB106K006RNJ
7 1 C12 22uF CAP TANTALUM 22UF 6.3V 20% SMD CASE-B Kemet B45196H1226M209
RESISTORS
2 R1,R25** 33E CHIP RES 33R 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ330X
9 1 R3 20E CHIP RES 20R 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ 21X
10 3 R4,R5,R6 1K RES 1.0K OHM 1/16W 5% 0402 SMD 0402 Yageo RC0402JR-071KL
11 1 R7 100K CHIP RES 100K 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ104X
INDUCTORS
12 1 L1 4.7uH Power Inductor 2520 FDK MIPF2520D4R7
13 5 FB1,FB2,FB3,FB4,FB5 BEAD Ferrite Beads 0 05 Murata BLM21PG221SN
DIODES
14 1 D1 LED Green LED 0603 Lite-On Inc LTST-C190KGKT
15 1 D2 CMS02 Schottky Diode SMD Toshiba CMS02TE12L,Q
ANTENNA TUNING NETWORK
16 1 Z1,Z2,Z3 TBD Refer to the description in the schematic.
Sample part number for Z1 given here.
Murata GRM1555C1H R2CZ01D
IC'S
17 1 U1 40MHz Crystal Oscillator TXC 7C40000192

Redpine Signals Inc. Proprietary and Confidential Page
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1 1 U2 RS9110-N-11-02 02.11bgn WLAN Module Redpine RS9110-N-11-02
19 1 ANT1 Antenna 2.45GHz SMD Antenna Antenna Factor ANT-2.45-CHP-T
20 1 J1 5X2 Box Header Burg Header
21 1 J2 Microwave Coaxial Connector with switch Murata MM 430-2610RA1
NO POPULATE
22 1 C10 0.1uF CER CHIP C 0.1U 10% X5R 0402 6.3V 0402 Murata GRM155R61A104KA01D
23 1 R 4.7K CHIP RES 4K7 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ472X
24 1 U3 16MBIT Serial Flash WSON SST SST25VF016B-75-4I-QAF-T
2.2 SPI Interface Integration
Item Qty Reference Part
Value
Description Jedec Mfg/ Part No
CAPACITORS
1 1 C5 .2pF CER CHP C .2P +-0.25P C0G 0402 25V LF 0402 Murata GRM1555C1H R2CZ01D
2 4 C3,C ,C11,C13 0.1uF CER CHIP C 0.1U 10% X5R 0402 6.3V 0402 Murata GRM155R61A104KA01D
3 1 C1 2.2uF CER CHIP C 2.2U 20% X5R 0402 4V 0402 Murata GRM155R60G225ME15D
4 1 C6 1uF CAP CER 1.0UF 16V 10% X7R 0 05 0 05 Murata GRM21BR71C105KA01L
5 4 C2,C4,C14 10uF CER CHIP C 10U 20% X5R 0 05 10V 0 05 Murata GRM21BR61A106KE19L
6 1 C7 10uF CAP TANTALUM 10UF 6.3V 10% SMD CASE-B AVX TAJB106K006RNJ
7 1 C12 22uF CAP TANTALUM 22UF 6.3V 20% SMD CASE-B Kemet B45196H1226M209
RESISTORS
2 R1,R25** 33E CHIP RES 33R 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ330X
9 1 R2 3.9K to 4.7K
10 1 R3 20E CHIP RES 20R 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ 21X
11 3 R4,R5,R6 1K RES 1.0K OHM 1/16W 5% 0402 SMD 0402 Yageo RC0402JR-071KL
INDUCTORS

Redpine Signals Inc. Proprietary and Confidential Page 9
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12 1 L1 4.7uH Power Inductor 2520 FDK MIPF2520D4R7
13 5 FB1,FB2,FB3,FB4,FB5 BEAD Ferrite Beads 0 05 Murata BLM21PG221SN
DIODES
14 1 D1 LED Green LED 0603 Lite-On Inc LTST-C190KGKT
15 1 D2 CMS02 Schottky Diode SMD Toshiba CMS02TE12L,Q
ANTENNA TUNING NETWORK
16 1 Z1,Z2,Z3 TBD Refer to the description in the schematic.
Sample part number for Z1 given here.
Murata GRM1555C1H R2CZ01D
IC'S
17 1 U1 40MHz Crystal Oscillator TXC 7C40000192
1 1 U2 RS9110-N-11-02 02.11bgn WLAN Module Redpine RS9110-N-11-02
19 1 ANT1 Antenna 2.45GHz SMD Antenna Antenna Factor ANT-2.45-CHP-T
20 1 J1 5X2 Box Header Burg Header
21 1 J2 Microwave Coaxial Connector with switch Murata MM 430-2610RA1
NO POPULATE
22 2 C9,C10 0.1uF CER CHIP C 0.1U 10% X5R 0402 6.3V 0402 Murata GRM155R61A104KA01D
23 1 R 4.7K CHIP RES 4K7 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ472X
24 1 R7 100K CHIP RES 100K 5% 200PPM 0402 1/10W 0402 Panasonic ERJ-2GEJ104X
25 1 U3 16MBIT Serial Flash WSON SST SST25VF016B-75-4I-QAF-T

Redpine Signals Inc. Proprietary and Confidential Page 10
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3Recommended RS9110-N-11-02 PCB Landing Pattern
Figure 3 PCB Landing Pattern

Redpine Signals Inc. Proprietary and Confidential Page 11
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4Circuit and Layout Guidelines
The following are guidelines for integrating the RS9110-N-11-02 module into a wireless LAN solution.
1. The WLAN module has a central ground pad of size 2.5mm x 2.5mm. An application’s layout must have a provision to
include this.
a. Please provide a 2.7 mm X 2.7 mm Copper pad on the Top side of the application board. Please open the solder
mask in this area so that the Cu is exposed.
b. Please provide a 2.7 mm X 2.7 mm or higher Copper pad on the bottom side of the application board. Please
open the solder mask in this area so that the Cu is exposed.
c. Please provide at least 12 via’s to connect these pads to the Ground plane. We recommend that the via’s should
be at least 10 mil x 1 mil.
2. For RESET one of the two options should be followed
a. The RESET can be Host driven. At the time of Power-on, Please ensure that the reset is held low for at least
20mSec. After this the reset should be driven high.
b. Reset may be driven by an R-C circuit. The recommended value of ‘R’ is 100 Kohms and the recommended
value of ‘C’ is 0.1uF.
3. The reference schematics shown in the previous section include the recommended power supply filtering and
decoupling.
4. The RF trace on RF_OUT should have a characteristic impedance of 50 ohms. They can use any standard 50 RF trace
(Micro strip or Coplanar wave guide). The width of the 50 ohm line depends on their PCB stack like the Dielectric of the
PCB, thickness of Copper , thickness of Dielectric and such other factors. The customer is advised to work with their
fabrication unit to chose the right PCB stack and width.
5. To evaluate transmit and receive performance like Tx Power and EVM, Rx sensitivity etc., a ‘microwave coaxial
connector with switch’ should be placed between RF_OUT and the antenna.
6. CLK_REF is the reference clock to the module and should therefore be routed with minimum trace length and should be
routed away from other switching or sensitive traces.
7. Unused pins may be left open

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. The design of the embedded system should provide for a peak power load of 325mA.

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5C ip Antenna Layout Recommendations
The choice of antenna will depend on the application. However, some recommendations are listed below if an on-chip
antenna is desired to be used:
a. Antenna Factor ANT-2.45-CHP or equivalent.
b. Rainsun AN3216
Please make sure that the Cu is etched out in all the Layers in the Antenna region. The Ground plane should be removed
from under & either sides of the antenna. Please follow the rules listed in the picture below while doing the layout for the
chip Antenna. Removing the ground plane from the underneath the antenna is very important.
Figure 4 Antenna layout
The chosen Chip Antennae are λ/4 antennae and would require external ground plane for proper functioning and the length of
the ground plane behind the antenna (from the feedpoint of antenna to backwards) should be atleast 1 or 2 inches.
Interms of feedtrace which does not have ground underneath (3mm length), it will be resonant part of the antenna and lower
its frequency. This can be a useful tuning method although this kind of short trace should have little effect which can be
observed on a Network Analyzer. It is recommended to characterize the antenna portion using a Network Analyzer.

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Electrical performance of any Chip antenna is influenced by the physical characteristics of the surrounding ground plane, feed
line, other devices, and materials. This can be used as an advantage by manipulating certain parameters to affect resonant
frequency and match:
1. Ground plane configuration
2. Distance from antenna
3. Topology around antenna
4. Feed point transmission line impedance
5. Trace width
6. Trace length
7. Matching Network
. PCB substrate thickness
9. PCB substrate dielectric constant.
5.1 Antenna Matc ing Network
Provision should be given for a pie network as shown in the schematics. The values shown below are just for example. The
values of the pie network components depends on the Antenna part, Customers layout, Gnd plane in the layout & other
components in the system which could affect the radiation pattern of the Antenna. Please use a Network Analyzer to
optimize the values of the match network for the best return loss.

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L=3nHto3.9nH
C=1.5pFto3pF
C=1.5pFto3pF
L=3nHto3.9nH
Ground Plane
RF IN
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Ground Plane
RF IN
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Figure 5 Antenna Matc ing Network
Note: The radiation pattern of the Antenna can be studied in an Anechoic Chamber using a Network Analyzer & a Horn
Standard Gain Antenna

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6Reference Oscillator Specifications
Parameter Specifications Units Comments
Nominal Frequency 40 MHz
Frequency Accuracy ± 20 PPM Over operational
temperature at rated
voltage.
Supply Voltage (VDD) 2. ± 10%
or
3.3 ± 10%
V Power supply should
ideally be locally
regulated, and with
adequate filtering.
Power Supply PSRR > 60 dB
Operational Temperature -40 to + 5 °C For industrial grade
products.
Output Voltage ‘0’ level < 10% of VDD V
Output Voltage ‘1’ level > 90% of VDD V
Output type Square Wave
Duty cycle 45 to 55 %
Rise time/Fall time < 10 ns
Periodic Jitter 30 ps pk-pk ps Typical Spec of the
Oscillator we use
Wake-up time from Standby < 1 ms
Wake-up time from power-on < 5 ms
Standby current < 20 uA

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Active current < 10 mA
Output load > 15 pF
Phase Noise at offset:
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
< - 9
< -121
< -135
< -146
< - 150
dBc/
Hz
Typical Spec of the
Oscillator we use.
6.1 List of Recommended Crystal Oscillators
1. TXC part number 7C40000192 (This part was used for characterizing all our boards)
The following can also be used based on the specifications
2. Ecera part number FD4000113
3. Fox Xpresso part number FXO-HC53 R
4. Kyocera part number KC25200C40C3KE00
5. Tai-Saw Technology part number TW0377E
6. Epson Toyocom SG 150-SCE
7. Epson Toyocom SG 211-SCE
. Golledge GXO-5332L/E 40.0MHz
9. ECS EC-2532HS
Note: Before finalizing the choice of a crystal oscillator, it is advisable to carry out detailed EVM measurements on a prototype
or evaluation board.

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7Recommended Specifications for Sc ottky Diode
• Forward voltage: VFM = 0.40 V (max)
• Average forward current: IF (AV) = 3.0 A
• Repetitive peak reverse voltage: VRRM = 30 V
7.1 Recommended Parts
a) Toshiba part number CMS02
b) NXP part number PMEG3030BEP

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8Sample Layout
This section provides a sample layout of a board that instantiates RS9110-N-11-02. This reference board is an SDIO module with a
standard interface into an SDIO slot.
.1 Top Layer

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8.1 Layer 2
8.2 Layer 3