Redpine Signals RS9113 Quick setup guide

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Redpine Signals, Inc. Proprietary and Confidential Page 1
RS9113
Module Integration Guide
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Ve er rs si io on n 2 2. .2 2
October 2014
Redpine Signals, Inc.
2107 N. First Street, #680
San Jose, CA 95131.
Tel: [phone]
Fax: [phone]
Email: [e-mail]
Website: www.redpinesignals.com

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Disclaimer:
The information in this document pertains to information related to Redpine
Signals, Inc. products. This information is provided as a service to our
customers, and may be used for information purposes only. Redpine assumes
no liabilities or responsibilities for errors or omissions in this document. This
document may be changed at any time at Redpine’s sole discretion without
any prior notice to anyone. Redpine is not committed to updating this
document in the future.
Copyright © 2014 Redpine Signals, Inc. All rights reserved

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About this Document
The RS9113 module is a Wi-Fi, Bluetooth and ZigBee combo module. It is a
dual-band 802.11n single-stream module with built-in MAC/BBP, RF and PA,
and front-end components. It interfaces to a host processor through SDIO,
SPI, UART or USB interfaces. This document provides information that may be
used while integrating the module into an end-to-end solution.
This document includes RS9113 interfacing schematics describing the
supported host interfaces and the other corresponding circuitry, along with the
BOM.

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Table Of Contents
1RS9113 module with integrated antenna...................... 7
1.1 System Block Diagram .................................................. 7
1.2 Reference Schematics and BOM .................................... 8
1.2.1 SDIO mode Interface Schematic (Input supply –1.8V) ............... 9
1.2.1.1 Bill of Materials for SDIO mode (Input supply –1.8V).......... 10
1.2.2 SDIO mode Interface Schematic (Input supply –3.3V) ............. 12
1.2.2.1 Bill of Materials for SDIO mode (Input supply –3.3V).......... 13
1.2.3 SPI mode Interface Schematic ............................................... 15
1.2.3.1 Bill of Materials for SPI mode............................................ 17
1.2.4 USB mode Interface Schematic .............................................. 19
1.2.4.1 Bill of Materials for USB mode........................................... 20
1.2.5 USB CDC mode Interface Schematic ....................................... 22
1.2.5.1 Bill of Materials for USB CDC mode.................................... 23
1.2.6 UART mode Interface Schematic............................................. 25
1.2.6.1 Bill of Materials for UART Mode ......................................... 26
1.3 Recommended PCB Landing Pattern ........................... 28
1.4 Circuit and Layout Guidelines ..................................... 29
1.5 Sample Layout in SDIO mode...................................... 30
1.5.1 Top Layer ............................................................................ 30
1.5.2 Bottom Layer ....................................................................... 31
1.5.3 Component Placement .......................................................... 32
1.6 u.FL Connector for External Antenna ......................... 33
2RS9113 module without integrated antenna............... 35
2.1 System Block Diagram ................................................ 35
2.2 Reference Schematics and BOM .................................. 36
2.2.1 SDIO mode Interface Schematic (Input supply –1.8V) ............. 37
2.2.1.1 Bill of Materials for SDIO mode (Input supply –1.8V).......... 38
2.2.2 SDIO mode Interface Schematic (Input supply –3.3V) ............. 40
2.2.2.1 Bill of Materials for SDIO mode (Input supply –3.3V).......... 41
2.2.3 SPI mode Interface Schematic ............................................... 43
2.2.3.1 Bill of Materials for SPI mode............................................ 44
2.2.4 USB mode Interface Schematic .............................................. 46
2.2.4.1 Bill of Materials for USB mode........................................... 47
2.2.5 USB CDC mode Interface Schematic ....................................... 49
2.2.5.1 Bill of Materials for USB CDC mode.................................... 50
2.2.6 UART mode Interface Schematic............................................. 52
2.2.6.1 Bill of Materials in UART Mode .......................................... 53
2.3 Recommended PCB Landing Pattern ........................... 55
2.4 Circuit and Layout Guidelines ..................................... 56
2.5 Antenna Layout Recommendations............................. 56
2.6 Sample layout in SDIO mode ...................................... 58
2.6.1 Top Layer ............................................................................ 58
2.6.2 Layer2 ................................................................................ 58
2.6.3 Layer3 ................................................................................ 59
2.6.4 Bottom Layer ....................................................................... 59
2.6.5 Component Placement .......................................................... 60

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Table of Figures
Figure 1: RS9113 Module with Integrated Antenna..............................7
Figure 2: SDIO mode Interface Schematic –1.8V ................................9
Figure 3: SDIO mode Interface Schematic –3.3V ..............................12
Figure 4: SPI mode Interface Schematic ............................................15
Figure 5: USB mode Interface Schematic ...........................................19
Figure 6 USB CDC Mode Schematics ...................................................22
Figure 7: UART mode Interface Schematic .........................................25
Figure 8: PCB Landing Pattern for RS9113 Module with Integrated
Antenna ........................................................................................28
Figure 9: Copper Etching Guidelines...................................................29
Figure 10: PCB Top Layer Diagram .....................................................30
Figure 11: PCB Bottom Layer Diagram ...............................................31
Figure 12 : PCB Component Placement Diagram ................................32
Figure 13 : u.FL Connector on module [Part no. Hirose U.FL-R-SMT
(01)] ............................................................................................33
Figure 14: RS9113 Module without Integrated Antenna.....................35
Figure 15: SDIO mode Interface Schematic –1.8V............................38
Figure 16: SDIO mode Interface Schematic –3.3V............................40
Figure 18: USB mode Interface Schematic ........................................47
Figure 19 USB CDC Mode Interface Schematics..................................49
Figure 20: UART mode Interface Schematic .......................................52
Figure 21: PCB Landing Pattern for 9113 Module without Integrated
Antenna ........................................................................................55
Figure 22: Chip Antenna Layout Recommendations ...........................57
Figure 23: PCB Top Layer Diagram .....................................................58
Figure 24: PCB Layer2 Diagram..........................................................58
Figure 25: PCB Layer3 Diagram..........................................................59
Figure 26: PCB Bottom Layer Diagram ...............................................59
Figure 27: PCB Component Placement Diagram .................................60

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Table of Tables
Table 1: Host Interface Selection .........................................................8
Table 2: Bill of Material for SDIO mode (Input supply –1.8V) ...........11
Table 3: Bill of Material for SDIO mode (Input supply –3.3V) ...........14
Table 4: Bill of Material for SPI mode .................................................18
Table 5: Bill of Material for USB mode ................................................21
Table 6 Bill Of Material for USB CDC Mode ..........................................24
Table 7: Bill of Material for UART mode ..............................................27
Table 8: Host Interface Selection .......................................................36
Table 9: Bill of Material for SDIO mode (Input supply –1.8V) ...........39
Table 10: Bill of Material for SDIO mode (Input supply –3.3 V).........42
Table 11: Bill of Material for SPI mode ...............................................45
Table 12: Bill of Material for USB mode ..............................................48
Table 13 Bill of Material for USB CDC Mode ........................................51
Table 14: Bill of Material for UART mode ............................................54

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1RS9113 module with integrated antenna
In The following sections, we present reference circuit schematics,
BOM, Recommended PCB Landing Pattern, Circuit and Layout
Guidelines along with a Sample layout of an Evaluation Board using
the RS9113 based module with an integrated PCB antenna. The
schematics are shown for SDIO, SPI, UART and USB host interface
options. The layout corresponding to this schematic is also shown
in this document as a reference.
1.1 System Block Diagram
Figure 1: RS9113 Module with Integrated Antenna

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Redpine Signals, Inc. Proprietary and Confidential Page 8
1.2 Reference Schematics and BOM
The default values of all the GPIO pins on powering up RS9113 will be set to
HIGH and are configured as Output.
The following table describes the host interface mode selection for
WiSeConnect and Connect-io-n family by using pull resistors on HOST_SEL_1
and HOST_SEL_0 pins. Internally, both the pins are pulled high.
Note: Host select pin configuration as shown in the table below for
UART is applicable for WiSeConnect/Connect-io-n module families.
For n-Link module family, UART shall function in conjunction with
SPI/SDIO/USB irrespective of Host select pins configuration.
Mode
HOST_SEL_1
HOST_SEL_0
UART
0
0
SPI
1
0
USB
0
1
SDIO
1
1
Table 1: Host Interface Selection
1.2.1 Power Supply
It is recommended to have a tightly regulated power supply which is 3.3V
+/- 5% and can handle a continuous current of 500mA. As a general practice
it is always suggested to have a 30% buffer on current rating of the power
supply.

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Redpine Signals, Inc. Proprietary and Confidential Page 9
1.2.2 SDIO mode Interface Schematic (Input supply –1.8V)
VIN_SDIO FB5 BEAD
VOUT_3V3
U3
TPS63001
L1
4L2 2
VIN
5VOUT 1
VINA
8
EN
6PS/SYNC
7
GND
9PGND 3
FB 10
GND
11
L2 2.2uH
C15
10uF(0805)
C16
10uF(0805)
VIN_SDIO
GPIO_16
R10
100K
RESET_N
R23 4.7K(NP)
C13
0.1uF
OPTION-1
R24 4.7K(NP)
RESET_N
C14
8.2nF
R9 1M
U2
MAX6415
VCC 5
SRT 4
RESETn 1
GND
2
RESET IN
3
R12
100K
R11 1M
C12
0.1uF
SW1
1 2
RESET Circuitry
OPTION-2
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module with integrated antenna -SDIO-1.8V
1 1
Rev0.0
VDD_EXT VDD_EXT
R22 4.7K(NP)
Redpine Signals Confidential
Note:
R22 should be mounted when ULPnot USED
RESET_N
C4
10uF(0805)
R25 1K
Y1
MC-146
14
C10 20pF
R26 1K
C24 20pF
R27 1K
C3
2.2uF
NO POPULATE
U1
RS9113 based Module
HOST_SEL_0 36
VIN_MOD
33
GPIO_21
31
GPIO_16
25 GPIO_15
24
USB_VDDP
21
GPIO_18
30 GPIO_17
28
SDIO_DATA2 16
SDIO_CLK 18
SDIO_DATA3 15
SDIO_DATA1 14
SDIO_CMD 17
SDIO_DATA0 13
USB_VDDS
22
USB_VBUS
9
USB_DP
11
USB_ID
12
HOST_SEL_1 35
WURX 1
GPIO_19
32
GPIO_11
7
GPIO_12
41
VRF33
34
GPIO_10
5
GPIO_14
8
GPIO_9
6
GPIO_13
49
XTAL_32Khz_N 4
XTAL_32Khz_P 3
VBATT
52
ULP_ANAGPI 50
RESET_N 51
USB_VDDD
42
JP1 48
JP0 47
BOOTLOAD_EN 27
USB_DN
10
SDIO_VDD_18_33
19
GPIO_8
29
VOUTLDOP3
40
USB_VDDA
43
HOST_BB_EN 39
ULP_GPIO_0 2
AUX_DAC_OUT 38
JP2 45
JNC 46
BOOT_MODE_0 20
AUX_ADC_IN0 44
GPIO_7
23
VOUTLDOP1
37
GPIO_2
26
GND
53
GND
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
GND
64
GND
65
GND
66
GND
67
GND
68
GND
69
GND
70
GND
71
GND
72
GND
73
GND
74
GND 75
GND 76
GND 77
GND 78
GND 79
with integrated antenna
VINMOD
VRF33
SDIO_D3
SDIO_D2
SDIO_D1
SDIO_D0
SDIO_CLK
SDIO_CMD
VIN_SDIO
SDIO_CMD
SDIO_CLK
SDIO_D3
SDIO_D0 SDIO_D1
SDIO_D2
VIN_SDIO
N O T E :
P ul l up re s is to rs s ho uld be pr es e nt on S DI O C M D & S D I O Da ta li ne s a c c ord ing
to th e s e c tio n 6 .6 .5 o f S D ph ys ic a l l ay er s pe c ifi c ati on, v ers i on 2 .0 0
N O T E :
R 1 4 * * v al ue s ho uld be ad jus te d ba s ed
on dri ve r out put im ped anc e a nd P C B
T ra c e I mp eda nc e ,,(3 3 E is N omi nal )
J2
SDIO Interface Connector
CD/DAT3
1CMD 2
VSS1
3VDD 4
CLK
5VSS2 6
DAT0
7DAT1 8
DAT2
9
R14**
C5
10uF(0805)
Power Supply Filter Section
LED Indication
GPIO_16 D1
LED R8 820E
VDD_EXT
FB9 BEAD
BUCK/BOOST SECTION
Note:
R24 should be mounted for USBEnumeration
R24 should not be mounted for USB_CDCEnumeration
H os t M C U may d ire c tly dr ive t he R E SE T _N
pin of the module a s shown belo w.
OPTION-3
HOST MCU
RESET_N
MCUpin
driving
RESET_N R13
10K
Note: Ensure a reset assertion time of 20ms.
Note:
Y1 is used for accurate wakeup time
C11
0.1uF
FB8 BEAD
VDD_EXT
VOUT_3V3
C9
0.1uF
C8
47uF(CASE B)
DVDD33
FB6 BEAD
VRF33
FB7 BEAD
C18
22uF(CASE B)
C17
10uF(0805)
C19
0.1uF
Tantalum
C20
0.1uF
L1
4.7uH
VINMOD
C21
1uF
Figure 2: SDIO mode Interface Schematic –1.8V

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1.2.2.1 Bill of Materials for SDIO mode (Input supply –1.8V)
Item
Qty
Reference
Part
Value
Description
Jedec
Mfg
Part No
CAPACITORS
1
4
C9,C19,C11,C20
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
2
1
C3
2.2uF
CER CHIP C 2.2U 20% X5R 0402 4V
0402
Murata
GRM155R60G225ME15D
4
1
C21
1uF
CAP CER 1UF 10V 10% X5R 0402
0402
Murata
GRM155R61A105KE15D
5
5
C4,C5,C15,C16,C17
10uF
CER CHIP C 10U 20% X5R 0805 10V
0805
Murata
GRM21BR61A106KE19L
6
1
C18
22uF
CAP TANT 22uF 10V 10%
Case B
AVX
TAJB226K006RNJ
7
1
C8
47uF
CAP TANT 47UF 6.3V 10%
Case B
AVX
TAJB476K006RNJ
RESISTORS
8
1
R14**
33E
CHIP RES 33R 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ330X
9
1
R8
820E
CHIP RES 820R 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ821X
10
3
R22,R23,R24
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ472X
11
3
R25,R26,R27
1K
RES 1.0K OHM 1/16W 5% 0402 SMD
0402
Yageo
RC0402JR-071KL
INDUCTORS
12
1
L1
4.7uH
Power Inductor
SMD
FDK
MIPF2520D4R7
13
1
L2
2.2uH
Power Inductor
1212
Murata
LQH3NPN2R2NG0L
14
5
FB5,FB6,FB7,FB8,FB9
BEAD
FILTER CHIP 120 OHM 1.5A 0402
0402
Murata
BLM15EG121SN1D
DIODES
15
1
D1
LED
Green LED
0603
Lite-On Inc
LTST-C190KGKT
IC'S
16
1
U1
B1-301
RS9113-B1-03 Module
Redpine
RS9113-B1-301
17
1
U3
TPS63001
Buck-Boost Regulator
QFN-10
Texas
TPS63001DRC
Miscellaneous
18
1
J2
Con
SDIO Interface Card Edge Connector
SMD
Optional
19
2
C10,C24
20pF
CAP CER 20PF 25V 5% NP0
0402
Murata
GRM1555C1E200JZ01D
20
1
C14
8.2nF
CAP CER 3900PF 50V 10% X7R
0402
Murata
GRM155R71H392KA01D
21
2
C12,C13
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
22
1
R13
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ103X
23
2
R10,R12
100K
CHIP RES 100K 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ104X

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24
2
R9,R11
1M
CHIP RES 1M 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ105X
25
1
SW1
sw
SWITCH TACTILE SPST-NO 0.02A 15V
SMD
ALPS
SKRAAKE010
26
1
U2
Reset
IC MPU/Reset circuit
SOT23-
5
Maxim
MAX6415UK-T
27
1
Y1
Crystal
CRYSTAL 32.768KHZ 9PF SMD
SMD
Epson
MC-146 32.768000kHz
12.5
Table 2: Bill of Material for SDIO mode (Input supply –1.8V)

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1.2.3 SDIO mode Interface Schematic (Input supply –3.3V)
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module with integrated antenna -SDIO-3.3V
1 1
Rev0.0
Note:
R22 should be mounted when ULPnot USED
Note:
R24 should be mounted for USB Enumeration
R24 should not be mounted for USB_CDCEnumeration
Note:
Y1 is used for accurate wakeup time
FB9 BEAD
C11
0.1uF
FB8 BEAD
VDD_EXT
VIN_SDIO
C9
0.1uF
DVDD33
C8
47uF(CASE B)
VRF33
FB6 BEAD
FB7 BEAD
C17
10uF(0805)
C18
22uF(CASE B)
Tantalum
VIN_SDIO
C20
0.1uF
C19
0.1uF
L1
4.7uH
GPIO_16
C21
1uF
VINMOD
R10
100K
Power Supply Filter Section
RESET_N
OPTION-1
R23 4.7K(NP)
C13
0.1uF
R24 4.7K(NP)
RESET_N
C14
8.2nF
R9 1M
R12
100K
U2
MAX6415
VCC 5
SRT 4
RESETn 1
GND
2
RESET IN
3
R11 1M
C12
0.1uF
OPTION-2
SW1
1 2
RESET Circuitry
VDD_EXT VDD_EXT
R22 4.7K(NP)
Redpine Signals Confidential
RESET_N
C4
10uF(0805)
R25 1K
Y1
MC-146
14
C10 20pF
C24 20pF
R26 1K
R27 1K
NO POPULATE
C3
2.2uF
U1
RS9113 based Module
HOST_SEL_0 36
VIN_MOD
33
GPIO_21
31
GPIO_16
25 GPIO_15
24
USB_VDDP
21
GPIO_18
30 GPIO_17
28
SDIO_DATA2 16
SDIO_CLK 18
SDIO_DATA3 15
SDIO_DATA1 14
SDIO_CMD 17
SDIO_DATA0 13
USB_VDDS
22
USB_VBUS
9
USB_DP
11
USB_ID
12
HOST_SEL_1 35
WURX 1
GPIO_19
32
GPIO_11
7
GPIO_12
41
VRF33
34
GPIO_10
5
GPIO_14
8
GPIO_9
6
GPIO_13
49
XTAL_32Khz_N 4
XTAL_32Khz_P 3
VBATT
52
ULP_ANAGPI 50
RESET_N 51
USB_VDDD
42
JP1 48
JP0 47
BOOTLOAD_EN 27
USB_DN
10
SDIO_VDD_18_33
19
GPIO_8
29
VOUTLDOP3
40
USB_VDDA
43
HOST_BB_EN 39
ULP_GPIO_0 2
AUX_DAC_OUT 38
JP2 45
JNC 46
BOOT_MODE_0 20
AUX_ADC_IN0 44
GPIO_7
23
VOUTLDOP1
37
GPIO_2
26
GND
53
GND
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
GND
64
GND
65
GND
66
GND
67
GND
68
GND
69
GND
70
GND
71
GND
72
GND
73
GND
74
GND 75
GND 76
GND 77
GND 78
GND 79
with integrated antenna
VINMOD
VRF33
SDIO_D2
SDIO_D1
SDIO_D0
SDIO_CLK
SDIO_CMD
SDIO_D3
VIN_SDIO
SDIO_CMD
SDIO_CLK
SDIO_D3
SDIO_D0 SDIO_D1
SDIO_D2
VIN_SDIO
N O T E :
P ul l up re s is to rs s ho ul d be pre s en t on S D I O C M D & S DI O D at a
li nes ac c o rdi ng to th e s e c tio n 6 .6 .5 o f S D p hys i c al la ye r
s pe c ific a ti on, v ers io n 2 .0 0
N O T E :
R 1 4 * * va lu e s ho uld be a djus te d ba s ed
on dri ve r out put im ped anc e a nd P C B
T ra c e I mp eda nc e ,,(3 3 E is N omi nal )
J2
SDIO Interface Connector
CD/DAT3
1CMD 2
VSS1
3VDD 4
CLK
5VSS2 6
DAT0
7DAT1 8
DAT2
9C5
10uF(0805)
R14**
LED Indication
GPIO_16 D1
LED
VDD_EXT
R8 820E
MCUpin
driving
RESET_N
H os t M C U may d ire c tly d riv e th e R E SE T _ N
pin of the module a s shown below.
OPTION-3
R13
10K
Note: Ensure a reset assertion time of 20ms.
HOST MCU
RESET_N
Figure 3: SDIO mode Interface Schematic –3.3V

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NOTE: Pull up resistors should be present on SDIO_CMD & SDIO_Data lines according to SDIO physical layer
specification, version 2.00.
1.2.3.1 Bill of Materials for SDIO mode (Input supply –3.3V)
Item
Qty
Reference
Part
Value
Description
Jedec
Mfg
Part No
CAPACITORS
1
4
C9,C19,C11,C20
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
4
1
C21
1uF
CAP CER 1UF 10V 10% X5R 0402
0402
Murata
GRM155R61A105KE15D
2
1
C3
2.2uF
CER CHIP C 2.2U 20% X5R 0402 4V
0402
Murata
GRM155R60G225ME15D
3
3
C4,C5,C17
10uF
CER CHIP C 10U 20% X5R 0805 10V
0805
Murata
GRM21BR61A106KE19L
5
1
C18
22uF
CAP TANT 22uF 10V 10%
Case B
AVX
TAJB226K006RNJ
6
1
C8
47uF
CAP TANT 47UF 6.3V 10%
Case B
AVX
TAJB476K006RNJ
RESISTORS
7
1
R14**
33E
CHIP RES 33R 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ330X
8
1
R8
820E
CHIP RES 820R 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ821X
9
3
R22,R23,R24
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ472X
10
3
R25,R26,R27
1K
RES 1.0K OHM 1/16W 5% 0402 SMD
0402
Yageo
RC0402JR-071KL
INDUCTORS
11
1
L1
4.7uH
Power Inductor
SMD
FDK
MIPF2520D4R7
12
4
FB6,FB7,FB8,FB9
BEAD
FILTER CHIP 120 OHM 1.5A 0402
0402
Murata
BLM15EG121SN1D
DIODES
13
1
D1
LED
Green LED
0603
Lite-On Inc
LTST-C190KGKT
IC'S
14
1
U1
B1-301
RS9113-B1-03 Module
Redpine
RS9113-B1-301
Miscellaneous
15
1
J2
Con
SDIO Interface Card Edge Connector
SMD
Optional
16
2
C10,C24
20pF
CAP CER 20PF 25V 5% NP0
0402
Murata
GRM1555C1E200JZ01D
17
1
C14
3.9nF
CAP CER 3900PF 50V 10% X7R
0402
Murata
GRM155R71H392KA01D
18
2
C12,C13
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
19
1
R13
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ103X

Redpine Signals, Inc. Proprietary and Confidential Page 14
M
Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V
Ve er rs si io on n 2 2. .2 2
20
2
R10,R12
100K
CHIP RES 100K 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ104X
21
2
R9,R11
1M
CHIP RES 1M 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ105X
22
1
SW1
sw
SWITCH TACTILE SPST-NO 0.02A 15V
SMD
ALPS
SKRAAKE010
23
1
U2
Reset
IC MPU/Reset circuit
SOT23-
5
Maxim
MAX6415UK-T
24
1
Y1
Crystal
CRYSTAL 32.768KHZ 9PF SMD
SMD
Epson
MC-146 32.768000kHz
12.5
Table 3: Bill of Material for SDIO mode (Input supply –3.3V)

M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V Ve er rs si io on n 2 2. .1 1
Redpine Signals, Inc. Proprietary and Confidential Page 15
1.2.4 SPI mode Interface Schematic
FB9 BEAD
R25 4.7K
SPI_INTR
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS
LED Indication
VDD_EXT
GPIO_16 D1
LED R8 820E
SPI_INTR
SPI_CS
SPI_CLK
SPI_MOSI SPI_MISO
VIN_33
NOTE:
R6** v alue should be adjusted based
on driver output impedance and PCB
Trace Impedance,,(33E is Nominal)
NOTE:
Based on the Host SPI configuration, during BOOT UP, SPI Master could be
coming up as GPIO pins.In the wake of this possibility , it may be needed to add a
pull up on the SPI_CS and a pull up (CPOL=1)/pull down(CPOL=0) on the
SPI_CLK. The value of pull up/ pull down resistor should f ollow the
recommendations as giv en on the HOST side.
J2
SPI Interface Connector
CD/DAT3
1CMD 2
VSS1
3VDD 4
CLK
5VSS2 6
DAT0
7DAT1 8
DAT2
9
R6**
C10
10uF(0805)
RESET_N
R10
100K
C13
0.1uF
OPTION-1
RESET_N
C14
8.2nF
R9 1M
R12
100K
U2
MAX6415
VCC 5
SRT 4
RESETn 1
GND
2
RESET IN
3
OPTION-2
R11 1M
C12
0.1uF
SW1
1 2
RESET Circuitry
VDD_EXT VDD_EXT
Redpine Signals Confidential
H os t M C U may d ire c tly dr ive t he R E SE T _N
pin of the module a s shown belo w.
OPTION-3
Note: Ensure a reset assertion time of 20ms.
HOST MCU
RESET_N
MCUpin
driving
RESET_N R13
10K
VIN_33
GPIO_16
R23 4.7K(NP)
R24 4.7K(NP)
R22 4.7K(NP)
RESET_N
C4
10uF(0805)
R26 1K
R27 1K
R28 1K
C3
2.2uF
U1
RS9113 based Module
HOST_SEL_0 36
VIN_MOD
33
GPIO_21
31
GPIO_16
25 GPIO_15
24
USB_VDDP
21
GPIO_18
30 GPIO_17
28
SDIO_DATA2 16
SDIO_CLK 18
SDIO_DATA3 15
SDIO_DATA1 14
SDIO_CMD 17
SDIO_DATA0 13
USB_VDDS
22
USB_VBUS
9
USB_DP
11
USB_ID
12
HOST_SEL_1 35
WURX 1
GPIO_19
32
GPIO_11
7
GPIO_12
41
VRF33
34
GPIO_10
5
GPIO_14
8
GPIO_9
6
GPIO_13
49
XTAL_32Khz_N 4
XTAL_32Khz_P 3
VBATT
52
ULP_ANAGPI 50
RESET_N 51
USB_VDDD
42
JP1 48
JP0 47
BOOTLOAD_EN 27
USB_DN
10
SDIO_VDD_18_33
19
GPIO_8
29
VOUTLDOP3
40
USB_VDDA
43
HOST_BB_EN 39
ULP_GPIO_0 2
AUX_DAC_OUT 38
JP2 45
JNC 46
BOOT_MODE_0 20
AUX_ADC_IN0 44
GPIO_7
23
VOUTLDOP1
37
GPIO_2
26
GND
53
GND
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
GND
64
GND
65
GND
66
GND
67
GND
68
GND
69
GND
70
GND
71
GND
72
GND
73
GND
74
GND 75
GND 76
GND 77
GND 78
GND 79
with integrated antenna
VINMOD
VRF33
DVDD33
C15
0.1uF
FB8 BEAD
VDD_EXT
VIN_33
C9
0.1uF
DVDD33
C8
47uF(CASE B)
FB6 BEAD
FB7 BEAD VRF33
C17
10uF(0805)
C18
22uF(CASE B)
Tantalum
C20
0.1uF
L1
4.7uH
C19
0.1uF
C21
1uF
Power Supply Filter Section
VINMOD
Note:
R22 should be mounted when ULPnot USED
Y1
MC-146
14
C11 20pF
C24 20pF
NO POPULATE
Note:
Y1 is used for accurate wakeup time
Note:
R24 should be mounted for USBEnumeration
R24 should not be mounted for USB_CDCEnumeration
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module with integrated antenna -SPI
1 1
Rev0.0
Figure 4: SPI mode Interface Schematic

M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V Ve er rs si io on n 2 2. .1 1
Redpine Signals, Inc. Proprietary and Confidential Page 16
SPI mode interface connection recommendations:
For SPI communication, the host MCU which acts as a Master is connected over
SPI interface to the wireless module which acts as a slave. The following
recommendations describe hardware connections between master and slave for SPI
communication. They have to be implemented on the host MCU.
SPI_CS: The SPI_CS is a chip-select signal driven by the host. The host
should be programmed such that on powering it up, this signal should be
driven HIGH. If not, a pull-up resistor is recommended to be connected
on this line.
SPI_CLK: A clock output from the SPI master component carries the serial
clock to the slave. Based on the configuration of clock polarity (CPOL)
mode in the host MCU, a pull-up (for CPOL=1) or a pull-down (for
CPOL=0) resistor is recommended to be connected on this line.
SPI_INTR: The SPI_INTR is the interrupt signal driven by the RS9113
module to the host MCU .There are two possibilities based on which
pull-up/pull-down is recommended to be connected on this signal.
oActive high/Leading edge interrupt mode: Connect a pull-down
resistor.
oActive low/Trailing edge interrupt mode: Connect a pull-up
resistor.
Pull resistors can be avoided if the following programming sequence
is followed:
oProgram 9113 interrupt mode through bootloader.
oEnable interrupt in host MCU.
The host can be programmed such that the interrupt signal has to be
in disabled state till interrupt mode (active HIGH or LOW) is selected.
Note: Pull resistors on SPI_CS (Chip Select) and SPI_CLK (Serial Clock) can
be avoided if the host executes the following sequence.
oOn power up the RS9113 module is assumed to be in reset
mode. Then, initialize the SPI master on the host MCU.
oRelease the RS9113 module out of reset mode.
Specific values of pull resistors should follow host recommendations.

M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V Ve er rs si io on n 2 2. .1 1
Redpine Signals, Inc. Proprietary and Confidential Page 17
1.2.4.1 Bill of Materials for SPI mode
Item
Qty
Reference
Part
Value
Description
Jedec
Mfg
Part No
CAPACITORS
1
4
C9,C19,C15,C20
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
4
1
C21
1uF
CAP CER 1UF 10V 10% X5R 0402
0402
Murata
GRM155R61A105KE15D
2
1
C3
2.2uF
CER CHIP C 2.2U 20% X5R 0402 4V
0402
Murata
GRM155R60G225ME15D
3
3
C4,C10,C17
10uF
CER CHIP C 10U 20% X5R 0805 10V
0805
Murata
GRM21BR61A106KE19L
5
1
C18
22uF
CAP TANT 22uF 10V 10%
Case B
AVX
TAJB226K006RNJ
6
1
C8
47uF
CAP TANT 47UF 6.3V 10%
Case B
AVX
TAJB476K006RNJ
RESISTORS
7
1
R6**
33E
CHIP RES 33R 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ330X
8
1
R8
820E
CHIP RES 820R 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ821X
9
3
R26,R27.R28
1K
RES 1.0K OHM 1/16W 5% 0402 SMD
0402
Yageo
RC0402JR-071KL
10
3
R22,R23,R24
4.7K
RES 1.0K OHM 1/16W 5% 0402 SMD
0402
Yageo
RC0402JR-071KL
11
1
R25
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ472X
INDUCTORS
12
1
L1
4.7uH
Power Inductor
SMD
FDK
MIPF2520D4R7
13
4
FB6,FB7,FB8,FB9
BEAD
FILTER CHIP 120 OHM 1.5A 0402
0402
Murata
BLM15EG121SN1D
DIODES
14
1
D1
LED
Green LED
0603
Lite-On Inc
LTST-C190KGKT
IC'S
15
1
U1
B1-301
RS9113-B1-301 Module
Redpine
RS9113-B1-301
Miscellaneous
16
1
J2
Header
5X2 Berg Header
DIP
Berg
Optional
17
2
C11,C24
20pF
CAP CER 20PF 25V 5% NP0
0402
Murata
GRM1555C1E200JZ01D
18
1
C14
8.2nF
CAP CER 3900PF 50V 10% X7R
0402
Murata
GRM155R71H392KA01D
19
2
C12,C13
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
20
1
R13
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ103X
21
2
R10,R12
100K
CHIP RES 100K 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ104X

Redpine Signals, Inc. Proprietary and Confidential Page 18
M
Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V
Ve er rs si io on n 2 2. .2 2
22
2
R9,R11
1M
CHIP RES 1M 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ105X
23
1
SW1
sw1
SWITCH TACTILE SPST-NO 0.02A 15V
SMD
ALPS
SKRAAKE010
24
1
U2
Reset
IC MPU/Reset circuit
SOT23-
5
Maxim
MAX6415UK-T
25
1
Y1
Crystal
CRYSTAL 32.768KHZ 9PF SMD
SMD
Epson
MC-146 32.768000kHz
12.5
Table 4: Bill of Material for SPI mode

M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V Ve er rs si io on n 2 2. .1 1
Redpine Signals, Inc. Proprietary and Confidential Page 19
1.2.5 USB mode Interface Schematic
USB_VBUS
VOUTLDOP3
USB_DN
USB_DP D2 0603ESDA
USB_DP
USB_DN
D3 0603ESDA
USB_ID
C20
4.7nF 250V
R21 1M
C21
0.1uF
USB_VBUS
VOUTLDOP3
C22
10uF(0805)
J3
Micro USB
VBUS 1
D- 2
D+ 3
ID 4
GND 5
Device Mode
VOUTLDOP1
FB10
BEAD ANA3V3 C26
1uF
Y1
MC-146
14
Note:
R22 should be mounted when ULPnot USED
C24 20pF
C27 20pF
NO POPULATE
Note:
R24 should be mounted for USBEnumeration
R24 should not be mounted for USB_CDCEnumeration
Note:
Y1 is used for accurate wakeup time
FB9 BEAD
USB_ID
USB_DP
USB_DN
USB_VBUS
R26 4.7K
R25 4.7K
DVDD33
VOUT_3V3
GPIO_16
R23 4.7K(NP)
R24 4.7K
R22 4.7K(NP)
RESET_N
C4
10uF(0805)
R27 1K
ANA3V3
R28 1K
VOUTLDOP1
R29 1K
C3
2.2uF
U1
RS9113 based Module
HOST_SEL_0 36
VIN_MOD
33
GPIO_21
31
GPIO_16
25 GPIO_15
24
USB_VDDP
21
GPIO_18
30 GPIO_17
28
SDIO_DATA2 16
SDIO_CLK 18
SDIO_DATA3 15
SDIO_DATA1 14
SDIO_CMD 17
SDIO_DATA0 13
USB_VDDS
22
USB_VBUS
9
USB_DP
11
USB_ID
12
HOST_SEL_1 35
WURX 1
GPIO_19
32
GPIO_11
7
GPIO_12
41
VRF33
34
GPIO_10
5
GPIO_14
8
GPIO_9
6
GPIO_13
49
XTAL_32Khz_N 4
XTAL_32Khz_P 3
VBATT
52
ULP_ANAGPI 50
RESET_N 51
USB_VDDD
42
JP1 48
JP0 47
BOOTLOAD_EN 27
USB_DN
10
SDIO_VDD_18_33
19
GPIO_8
29
VOUTLDOP3
40
USB_VDDA
43
HOST_BB_EN 39
ULP_GPIO_0 2
AUX_DAC_OUT 38
JP2 45
JNC 46
BOOT_MODE_0 20
AUX_ADC_IN0 44
GPIO_7
23
VOUTLDOP1
37
GPIO_2
26
GND
53
GND
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
GND
64
GND
65
GND
66
GND
67
GND
68
GND
69
GND
70
GND
71
GND
72
GND
73
GND
74
GND 75
GND 76
GND 77
GND 78
GND 79
with integrated antenna
VINMOD
VRF33
DVDD33
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module with integrated antenna -USB
1 1Wednesday, October 22, 2014
Rev0.0
FB5 BEAD
VOUT_3V3
U3
TPS63001
L1
4L2 2
VIN
5VOUT 1
VINA
8
EN
6PS/SYNC
7
GND
9PGND 3
FB 10
GND
11
L2 2.2uH
C15
10uF(0805)
C16
10uF(0805)
Power Supply Filter Section
BUCK/BOOST SECTION
C11
0.1uF
VDD_EXT
FB8 BEAD
VOUT_3V3
C9
0.1uF
DVDD33
C8
47uF(CASE B)
VRF33
FB6 BEAD
C17
2.2uF
FB7 BEAD
C18
22uF(CASE B)
Tantalum
C19
0.1uF
C23
0.1uF
L1
4.7uH
C25
1uF
VINMOD
USB Connector
R10
100K
RESET_N
C13
0.1uF
OPTION-1
RESET_N
C14
8.2nF
R9 1M
U2
MAX6415
VCC 5
SRT 4
RESETn 1
GND
2
RESET IN
3
R12
100K
R11 1M
C12
0.1uF
SW1
1 2
RESET Circuitry
OPTION-2
Redpine Signals Confidential
VDD_EXT VDD_EXT
LED Indication
VDD_EXT
GPIO_16 R8 820E
D1
LED
H os t M C U may d ire c tly dr ive t he R E SE T _N
pin of the module a s shown belo w.
OPTION-3
HOST MCU
RESET_N
MCUpin
driving
RESET_N R13
10K
Note: Ensure a reset assertion time of 20ms.
Figure 5: USB mode Interface Schematic

Redpine Signals, Inc. Proprietary and Confidential Page 20
M
Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
V
Ve er rs si io on n 2 2. .2 2
1.2.5.1 Bill of Materials for USB mode
Item
Qty
Reference
Part
Value
Description
Jedec
Mfg
Part No
CAPACITORS
1
3
C9,C19,C21,C11,C23
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
3
1
C20
4.7nF
250V
CAP CER 4700PF 100V 10% X7R 0805
0805
Murata
GRM219R72A472KA01D
22
2
C25,C26
1uF
CAP CER 1UF 10V 10% X5R 0402
0402
Murata
GRM155R61A105KE15D
2
1
C3,C17
2.2uF
CER CHIP C 2.2U 20% X5R 0402 4V
0402
Murata
GRM155R60G225ME15D
5
4
C4,C15,C16,C22
10uF
CER CHIP C 10U 20% X5R 0805 10V
0805
Murata
GRM21BR61A106KE19L
6
1
C18
22uF
CAP TANT 22uF 10V 10%
Case B
AVX
TAJB226K006RNJ
7
1
C8
47uF
CAP TANT 47UF 6.3V 10%
Case B
AVX
TAJB476K006RNJ
RESISTORS
8
1
R8
820E
CHIP RES 820R 5% 200PPM 0402
1/10W
0402
Panasonic
ERJ-2GEJ821X
9
3
R27,R28,R29
1K
RES 1.0K OHM 1/16W 5% 0402 SMD
0402
Yageo
RC0402JR-071KL
10
4
R22,R23,R24,R25,R26
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ472X
11
1
R21
1M
CHIP RES 1M 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ105X
INDUCTORS
12
1
L1
4.7uH
Power Inductor
SMD
FDK
MIPF2520D4R7
13
1
L2
2.2uH
Power Inductor
1212
Murata
LQH3NPN2R2NG0L
14
3
FB5,FB6,FB7,FB8,FB9,FB10
BEAD
FILTER CHIP 120 OHM 1.5A 0402
0402
Murata
BLM15EG121SN1D
DIODES
15
1
D1
LED
Green LED
0603
Lite-On Inc
LTST-C190KGKT
16
2
D2,D3
0603ESDA
ESD Suppressor
0603
CooperBussmann
0603ESDA-MLP
IC'S
17
1
U1
B1-301
RS9113-B1-301 Module
Redpine
RS9113-B1-031
18
1
U3
TPS63001
Buck-Boost Regulator
QFN-10
Texas
TPS63001DRC
Miscellaneous
19
1
J3
USB
Micro USB
SMD
Molex
54819-0572
20
2
C24,27
20pF
CAP CER 20PF 25V 5% NP0
0402
Murata
GRM1555C1E200JZ01D
Optional
21
1
C14
8.2nF