Renesas RH850 Series Installation and operating instructions

Application Note
R01AN6028EJ0100 Rev.1.0 Page
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RH850 Series
CAN Receive Procedure (CAN FD Mode)
Summary
This document describes an example of a procedure for receiving CAN using the RH850 series. Please refer to the
notes in the latest user's manual hardware edition for the settings of each register.
Operation Confirmed Devices
This document applies to the RH850 series.
The variables described in the text are as follows.
Table 1-1 Target Devices and Variables
Variable
Target MCU
RH850/E2x
RH850/E1M-S2
RH850/P1M-E
RS-CAN FD channel number
m
0~4
0~3
0~2
GAFLIDj, GAFLMj, GAFLP0j,
GAFLP1j Register numbers
j
0~15
0~15
0~15
Transmit/Receive FIFO buffer
number
k
0~14
0~11
0~8
Receive FIFO buffer number
x
0~7
0~7
0~7
Receive buffer number
q
0~79
0~63
0~47
Transmit buffer number
p
0~79
0~63
0~47
RAM test number
r
0~63
0~63
0~63
GAFLCFGi、GTINTSTSi
register number
i
0
0
0
Number of each status register
y
0~2
0,1
0,1
The functions marked with "★" in the text are applicable to cases where 2 or more channels are installed.
In the text, CFD is omitted from the register names.
R01AN6028EJ0100
Rev.1.0

RH850 Series CAN Receive Procedure (CAN FD Mode)
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Contents
1. Receive Function..............................................................................................................3
2. Receive Using Receive Buffers........................................................................................4
3. Receive Using Receive FIFO Buffers...............................................................................7
4. Receive Using Transmit/Receive FIFO Buffers...............................................................12
5. CAN-related Interrupt Processing...................................................................................18
6. Precautions for Processing Flow ....................................................................................19
7. Appendix........................................................................................................................20

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1. Receive Function
The functions that can be used when receiving CAN messages are shown below. For details on each process, refer to
the following chapters.
•・Receive using the receive buffer
•・Receive using the receive FIFO buffer
•・Receive using the transmit / receive FIFO buffer

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2. Receive Using Receive Buffers
Receive buffer q shared by all channels is available. Since the message stored in the receive buffer with the same
number is overwritten, the latest received data can be read.
If it is received in the receive buffer, no interrupt is generated.
When the process of storing the received message in the receive buffer starts, the receive buffer q becomes "new
message" (the RMNSq flag in the RMNDy register becomes "1"). Received data information can be read from the
RMIDq register, RMPTRq register, and RMDFb_q register (b = 0 to 4). The payload size that can be received by the
receive buffer is up to 20 bytes. You must use the receive or transmit / receive FIFO to receive messages exceeding 20
bytes.
For the configuration settings for using the receive buffer, refer to "CAN Configuration Application Note".
Figure 2-1 shows the operation of the receive buffer.
Figure 2-1 Receive Buffer Operation
Msg1
Msg2
Msg3
Msg1
Msg2
Read with
the program
Msg3
CAN Bus
Receive Rule Table
Receive buffer 0
Receive buffer 1
Receive buffer 2
Receive buffer q*
Msg1
Msg2
Msg3
【Note】q：Number of receive buffers (set value of the NRXMB [7: 0] bit of the RMNB register) -1
Receive
Data

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2.1 Receive Buffer Read Procedure
Figure 2-2 shows the procedure for reading the receive buffer.
【Note】
1.
Write “0” for the RMNSq flag in the RMNDy register in global operation mode or global test mode.
2.
To set the RMNSq flag to “0”, write “0” with the program.
3.
To write "0" in the RMNSq flag, use the store instruction to write "0" in the bit you want to set to "0" and "1"
in the other bits.
4.
The RMNSq flag cannot be set to “0”while the message is being stored. The time to store a message depends
on the size of the payload stored in the receive buffer.
5.
For a standard ID, read b10 to b0 of the ID (the RMID [28: 0] bit of the RMIDq register). “0”can be read for
b28 to b11.
START
No
Yes
Is there a receive buffer that received
a new message?
Clear the receive buffer receive completion flag
corresponding to the receive buffer to "0"*1.、2.、3.、4.
No
Yes
Corresponding receive buffer receive complete
Is the flag "0"?*4.
Read messages in the receive buffer
・IDE/RTR/ID*5.
・DLC*6.
・Label information of received data*7.
・Timestamp value
・Received data*8.
No
Yes
Is there overwriting of
the message being read?
(Corresponding receive buffer receive completed
Is the flag "1"? )
User processing when message overwrite is detected
END

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6.
If DLC replacement is enabled after filtering by the reception rule (the DCE bit of the GCFG register is “1”,
DRE bit is “1”), the received message matches the DLC set value in the reception rule table (the
GAFLDLC[3:0] bit of the GAFLP0_j register) that matches the received message is stored. Otherwise, the
DLC value of the received message is stored.
7.
After filtering by the receive rule, the set value of the label of the receive rule table (the GAFLPTR [11: 0] bit
of the GAFLP0_j register) that matches the received message is stored.
8.
If the DLC of the received message (the value of the RMPLC [3: 0] bit of the RMPTRq register) is less than
the payload storage size of the receive buffer, “H'00”can be read for the data byte (RMDFb_q register) for
which no data is set.
Figure 2-2 Receive Buffer Read Procedure

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3. Receive Using Receive FIFO Buffers
There are 8 receive FIFO buffers shared by all channels. Messages can be stored in each receive FIFO buffer for the
number of buffers.
When a received message is stored in the receive FIFO buffer, the value of the corresponding message count display
counter (the RFMC [7: 0] bit of the RFSTSx register) is incremented.
Received messages can be read from the RFIDx register, RFPTRx register, RFFDSTSx register, and RFDFd_x
register (d = 0 to 15). The receive FIFO buffer can be read from the oldest message.
When the value of the message count display counter matches the buffer value of the FIFO buffer (the value set by
the RFCCx register RFDC [2: 0] bit), the receive FIFO buffer becomes full (the RFFLL flag in the RFSTSx register is
“1”). When all messages are read from the receive FIFO buffer, the receive FIFO buffer becomes empty (the RFEMP
flag in the RFSTSx register is “1”).
Refer to the CAN Configuration Application Note for configuration settings to use the receive FIFO buffer.
Figure 3-1 shows the operation of the receive FIFO buffer.
Figure 3-1 Receive FIFO Buffer Operation
Receive
FIFO
interrupt
source
activated
RFIDLm,Hx
RFTSmx
RFPTRx
RFDFx
Msg1
Msg2
Msg3
Msg4
Msg3
Read with the
program
Msg2
Receive FIFO
Buffer x
Msg4
Msg3
Msg2
Mag1
：When the receive FIFO interrupt source reaches “the condition set in (the RFIGCV [2: 0] bit of the
RFCCx register) "
(When the RFIM bit of the RFCCx register is “0”)
：Receive FIFO interrupt source is "every time one message is received"
(When the RFIM bit of the RFCCx register is “1”)
CAN Bus
Msg1
Msg4
Receive Rule Table
※
※：Number of receive FIFO
buffer stages: 4
An interrupt occurs when a
message is stored until 8/8
Received data

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3.1 Receive FIFO Buffer Read Procedure
Figure 3-2 shows the procedure for reading the receive FIFO buffer, and Figure 3-3 and Figure 3-4 show the
procedure for enabling and prohibiting the use of the receive FIFO buffer.
【Note】
1.
If the FIFO message lost interrupt is enabled, execute it in the global error interrupt processing.
2.
For standard ID, read b10-b0 of ID (the RFID [28: 0] bit of the RFIDx register). “0”can be read for b28-b11.
3.
If DLC replacement is enabled after filtering by the reception rule (the DCE bit of the GCFG register is “1”,
DRE bit is “1”), the DLC set value in the reception rule table (the GAFLDLC[3:0] bit of the GAFLP0_j
register) that matches the received message is stored. Otherwise, the DLC value of the received message is
stored.
4.
After filtering by the reception rule, the set value of the receive rule table label (the GAFLPTR [11: 0] bit of
GAFLP0_j) that matches the received message is stored.
START
END
No
Yes
Unread message in the receive
FIFO buffer?*8.
Increment receive FIFO buffer pointer
*6.、7.
Read messages in the receive FIFO buffer
・IDE/RTR/ID*2.
・DLC*3.
・Label information of received data*4.
・Timestamp value
・Received data*5.
No
Yes
User processing when message overwrite is detected*1.
Is there a message lost?*1.
Clear receive FIFO message lost flag*1.

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5.
If the DLC of the received message (value of the RFDLC [3: 0] bit of the RFPTRx register) is less than the
payload storage size of the receive FIFO buffer, "H'00" can be read for the data byte (RFDFb_x register) for
which no data is set.
6.
After reading the messages in the receive FIFO buffer (RFIDx register, RFPTRx register, RFDFb_x register),
increment the pointer (write "H'FF" to the RFCC [7: 0] bit of the RFIDCTRx register).
7.
Increment the pointer when the receive FIFO buffer is used (the RFE bit of the RFCCx register is “1”) and
there are unread messages in the receive FIFO buffer (the RFEMP flag in the RFSTSx register is “0”).
8.
When reading all the unread messages in the receive FIFO buffer, use a loop statement or the like to read
until the buffer is empty.
Figure 3-2 Receive FIFO Buffer Read Procedure (no interrupt used)

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【Note】
1.
Rewrite to enable/disable the receive FIFO buffer (the RFE bit of the RFCCx register) in the global
operation mode or global test mode.
2.
Make the configuration settings for using the receive FIFO buffer, and then enable the use of the receive
FIFO buffer (the RFE bit is "1").
3.
If the number of receive FIFO buffers is set to “0” (“B’000” in the RFDC [2: 0] bit of the RFCCx register),
do not allow the receive FIFO buffer to be used.
Figure 3-3 Procedure to Enable Receive FIFO Buffer Use
【Note】
1.
Rewrite to enable/disable the receive FIFO buffer (the RFE bit of the RFCCx register) in the global
operation mode or global test mode.
2.
Even if the use of the receive FIFO buffer is prohibited (the RFE bit is “0”) while an interrupt request is
generated (the RFIF flag in the RFSTSx register is “1”), the interrupt request flag (RFIF flag) is not
automatically set to “0”. Set the interrupt request flag to "0" with the program.
Figure 3-4 Procedure to Prohibit Receive FIFO Buffer Use
START
Prohibit use of receive FIFO buffer*1.、2.
END
START
No
Yes
Is the receive FIFO buffer empty?
Enable use of receive FIFO buffer*1.、2.、3.
END