Renesas 9FGV100 Series User manual

1©2016 Integrated Device Technology, Inc. November 18, 2016
Register Descriptions
The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the
9FGV100x family of clock generators. Table 1 showcases the products under the 9FGV100x family.
For details of product operation, refer to the product datasheet.
9FGV100x Clock Generator Register Set
The device contains volatile (RAM) 8-bit registers and non-volatile 8-bit registers (Figure 1). The non-volatile registers are One-Time
Programmable (OTP) and will be pre-programmed at the factory with a custom dash-code configuration.
The device operates according to settings in the RAM registers. At power-up a pre-programmed configuration is transferred from OTP to
RAM registers. The device behavior can then be modified by reprogramming the RAM registers through I2C.
The device can start up in “I2C mode” or in “Hardware Select Mode”, depending upon the status of the REF0_SEL_I2C# pin at power up.
Also see the datasheet. I2C access is only possible when the device has started up in I2C mode. Startup in I2C mode is default when no
pull-up is added to the REF0_SEL_I2C# pin. Pre-programming settings determine which of the 4 OTP banks is loaded into RAM registers
at power up in I2C mode. Using I2C commands the configuration can be changed and there are also commands to reload a configuration
from a different OTP bank.
Figure 1. Register Maps
User Configuration Table Selection
At power up, the voltage at REF0_SEL_I2C# pin 23 is latched by the device and used to select the state of the SEL0/SCL and SEL1/SDA
pins (Table 2).
When a weak pull up (10k) is placed on REF0_SEL_I2C#, the SEL0/SCL and SEL1/SDA pins will be configured as hardware select
inputs, SEL0 and SEL1. Connecting SEL0 and SEL1 to VDDD and/or GND selects one of 4 configuration register sets, CFG0 through
CFG3, which is then loaded into the non-volatile configuration registers to configure the clock synthesizer. The CFG0 through CFG3
configurations are preprogrammed at the factory according to customer specifications and assigned a specific (dash) part number.
Table 1. 9FGV100x Family Products
Product Description Package
9FGV1001 2 Ref outputs, 4 Diff outputs with 1 Integer output divider 24pins
9FGV1002 2 Ref outputs, 4 Diff outputs with 1 Fractional output divider 24pins
9FGV1004 2 Ref outputs, 2 Diff outputs with individual Integer output dividers
and 2 Diff outputs with 1 Fractional output divider 24pins
User Guide
9FGV100x Register Descriptions and
Programming Guide

2©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
When a weak pull down is placed on REF0_SEL_I2C# (or when it is left floating to use internal pulldown), the pins SEL0 and SEL1 will be
configured as a I2C interface's SDA and SCL slave bus. Configuration register set CFG0 is commonly loaded into the non-volatile
configuration registers to configure the clock synthesizer but the device can be configured to load any of the other configurations. The
host system can use the I2C bus to update the volatile RAM registers to change the configuration, and to read status registers.
I2C Interface and Register Access
When poweredup in I2C mode, the device allows access to internal RAM registers. The default device address is 0xD0 for 8 bits or 0x68
for 7 bits. The device can be preprogrammed for addresses in the range 0xD0-D2-D4-D6 for 8 bits or 0x68-69-6A-6B for 7 bits. The
device acts as a slave device on the I2C bus using one of the four I2C addresses to allow multiple devices to be used in the system. The
interface accepts byte-oriented block write and block read operations. Two address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most
significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not
be moved into the registers until the STOP signal is received, at which point, all data received in the block write will be written
simultaneously in the registers.
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 100ktypical.
Figure 2. I2C Interface and Register Access
Table 2. Power-Up Setting of Hardware Select Pin vs I2C Mode, and Default OTP Configuration Register
REF0_SEL_I2C# Strap
at Power Up SEL1/SDA pin SEL0/SCL pin Function
10kpullup
0 0 OTPbankCFG0 used to initializeRAMconfigurationregisters
0 1 OTPbank CFG1 used to initializeRAMconfigurationregisters
1 0 OTPbank CFG2 used to initializeRAMconfigurationregisters
1 1 OTPbank CFG3 used to initializeRAMconfigurationregisters
10kpulldown or
floating SDA SCL I2C bus enabled to accessregisters
OTPbank CFG0 used to initializeRAMconfigurationregisters

3©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
Table 3. RAM Overview
Register
Address Function Explanation
0x00 Device / I2C settings
0x01 REF Outputs settings
0x02 OUT3 output settings0x03
0x04
0x05 OUT2 output settings0x06
0x07
0x08 OUT1 output settings0x09
0x0A
0x0B OUT0 output settings0x0C
0x0D
0x0E Crystal Oscillator settings
0x0F
0x10 FOD Spread Spectrum settings
0x11
0x12 FOD Integer Value
0x13 FOD Fractional Value
0x14
0x15 FOD Spread Spectrum settings
0x16
0x17 FOD Miscellaneous0x18
0x19
0x1A PLL Miscellaneous
0x1B
0x1C PLL Loop Filter settings0x1D
0x1E
0x1F PLL Feedback Divider Value
0x20 Integer Output Divider Values0x21
0x22
0x23 Reserved
0x24 Spread Spectrum Jitter Attenuator settings
0x25 Miscellaneous Device settings

4©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
RAM Register Map
Note1: To be able to read this info you already need to know the device address.
Note 2: These two bits show the configuration number 0~3 that will be loaded from OTP into registers at power up. When changing these
bits through I2C you instruct the chip to load another configuration from OTP. This is useful for switching between OTP configurations
when in I2C mode. This method is also used to step through each configuration for reading back OTP contents.
Table 4. RAM Register Map
Register Address Register Bit Function Explanation
Decimal Hex
00 0x00 7 Device preprogrammed? 0 = No , 1 = Yes
[6..5] I2C Device address. 00=0xD0 / 0x68, 01=0xD2 / 0x69, 10=0xD4 / 0x6A, 11=0xD6 / 0x6B (1)
[4..2] Reserved
[1..0] Load Configuration number at power up. (2)
01 0x01 [7..6] Enable REF outputs: 0x = Both REF0 and REF1 disabled (unused)
10 = REF0 enabled, REF1 disabled (unused)
11 = Both REF0 and REF1 enabled
5 Reserved
4 Behavior when REF is unused: 0 = Logic “0”, 1 = High Impedance (Tri-State)
[3..2] REF outputs Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0] Reserved
02 0x02 7 Enable OUT3: 0 = Disabled (unused) , 1 = Enabled
[6..4] OUT3 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2] OUT3 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0] Reserved
03 0x03 7 Reserved
6 Behavior when OUT3 is unused: 0 = Logic “0”, 1 = High Impedance (Tri-State)
5 OUT3 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4 OUT3 LPHCSL Impedance Control: 0 = 85Differential , 1 = 100Differential
[3..0] OUT3 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
04 0x04 7 Reserved
[6..4] OUT3 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3 Reserved
[2..0] OUT3 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111

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9FGV100x Register Descriptions and Programming Guide User Guide
05 0x05 7 Enable OUT2: 0 = Disabled (unused) , 1 = Enabled
[6..4] OUT2 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2] OUT2 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0] Reserved
06 0x06 7 Reserved
6 Behavior when OUT2 is unused: 0 = Logic “0”, 1 = High Impedance (Tri-State)
5 OUT2 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4 OUT2 LPHCSL Impedance Control: 0 = 85Differential , 1 = 100Differential
[3..0] OUT2 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
07 0x07 7 Reserved
[6..4] OUT2 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3 Reserved
[2..0] OUT2 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111
08 0x08 7 Enable OUT1: 0 = Disabled (unused) , 1 = Enabled
[6..4] OUT1 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2] OUT1 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0] Reserved
09 0x09 7 Reserved
6 Behavior when OUT1 is unused: 0 = Logic “0”, 1 = High Impedance (Tri-State)
5 OUT1 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4 OUT1 LPHCSL Impedance Control: 0 = 85Differential , 1 = 100Differential
[3..0] OUT1 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
10 0x0A 7 Reserved
[6..4] OUT1 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3 Reserved
[2..0] OUT1 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111
Register Address Register Bit Function Explanation
Decimal Hex

6©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
11 0x0B 7 Enable OUT0: 0 = Disabled (unused) , 1 = Enabled
[6..4] OUT0 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2] OUT0 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0] Reserved
12 0x0C 7 Reserved
6 Behavior when OUT0 is unused: 0 = Logic “0”, 1 = High Impedance (Tri-State)
5 OUT0 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4 OUT0 LPHCSL Impedance Control: 0 = 85Differential , 1 = 100Differential
[3..0] OUT0 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
13 0x0D 7 Reserved
[6..4] OUT0 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3 Reserved
[2..0] OUT0 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111
14 0x0E 7 Crystal Oscillator LDO: 0 = Disabled , 1 = Enabled
6 Reserved
[5..0] Crystal Oscillator X1 pin capacitance: Cap (pF) = 10 + 0.44 * Bits[4..0] + 7.04 * Bit[5]
Appendix 3: Crystal Load Capacitance Registers for Crystal Oscillator Load Capacitance
configuration.
15 0x0F 7 Crystal Oscillator Circuit: 0 = Disabled , 1 = Enabled
6 Reserved
[5..0] Crystal Oscillator X2 pin capacitance: Cap (pF) = 10 + 0.44 * Bits[4..0] + 7.04 * Bit[5]
16 0x10 7 FOD Spread Spectrum: 0 = Disabled , 1 = Enabled
[6..4] Reserved
[3..0] FOD Spread Spectrum Period, bits [11..8]. See Appendix 2 for Spread Spectrum configuration
17 0x11 [7..0] FOD Spread Spectrum Period, bits [7..0]
18 0x12 [7..0] FOD Integer Value. See Appendix 1 for Fractional Divider configuration
19 0x13 [7..0] FOD Fractional Value, bits [15..8]
20 0x14 [7..0] FOD Fractional Value, bits [7..0]
21 0x15 [7..0] FOD Spread Spectrum Step, bits [15..8]
22 0x16 [7..0] FOD Spread Spectrum Step, bits [7..0]
23 0x17 [7..0] Reserved
Register Address Register Bit Function Explanation
Decimal Hex

7©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
24 0x18 7 FOD Reset-B: 0 = Hold FOD in Reset Mode , 1 = Release FOD.
Toggle to 0 and back to 1 to apply a reset or restart of the FOD.
[6..2] Reserved
1 FOD Integer Mode: 0 = Use fractional settings for a fractional output divider value.
1 = Run output divider in Integer Mode in case the output division is an integer, for the best
performance.
0 Enable FOD: 0 = FOD is Disabled , 1 = FOD is Enabled.
25 0x19 [7..0] Reserved
26 0x1A 7 PLL, VCO Band Calibration Start. Toggle to 0 and back to 1 to trigger a calibration.
The calibration engages at the moment the bit moves from 0 to 1. The calibration finds the
optimum VCO band for the current VCO frequency.
6 Override VCO Band: 0 = Use Calibrated VCO Band , 1 = Use VCO Band value in bits [5..0].
[5..0] VCO Band Value. See bit 6.
27 0x1B 7 Enable VCO: 0 = VCO Disabled , 1 = VCO Enabled
6 Enable Charge Pump: 0 = CP Disabled , 1 = CP Enabled.
5 Enable PLL Bias: 0 = PLL Bias Disabled , 1 = PLL Bias Enabled
4 Bypass 3rd Pole in Loop Filter: 0 = Use 3rd Pole , 1 = 3rd Pole Bypassed
[3..0] Reserved
28 0x1C [7..4] Loop Filter R-zero value
[3..0] Reserved
29 0x1D [7..0] Reserved
30 0x1E [7..4] Reserved
[3..0] Charge Pump Current
31 0x1F [7..0] PLL Feedback Divider Value.
32 0x20 [7..0] Integer Divider value for OUT3, bits [7..0]
33 0x21 [7..0] Integer Divider value for OUT2, bits [7..0]
34 0x22 [7..4] Integer Divider value for OUT2, bits [11..8]
[3..0] Integer Divider value for OUT3, bits [11..8]
35 0x23 [7..0] Reserved
36 0x24 [7..3] Reserved
2 Spread Spectrum Jitter Attenuator: 0 = Disabled , 1 = Enabled
[1..0] SS Jitter Attenuator configuration. See Appendix 2: Fractional Output Divider and Spread
Spectrum.
Register Address Register Bit Function Explanation
Decimal Hex

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9FGV100x Register Descriptions and Programming Guide User Guide
37 0x25 7 Reserved
6 Enable Integer Output Dividers: 0 = Disabled , 1 = Enabled
5 Enable Crystal Frequency Doubler: 0 = Disabled , 1 = Enabled
4 Reserved
3 OUT3 Integer Divider Enable: 0 = Disabled , 1 = Enabled
2 OUT2 Integer Divider Enable: 0 = Disabled , 1 = Enabled
[1..0] Reserved
Register Address Register Bit Function Explanation
Decimal Hex

9©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
Block Diagrams
Figure 3. 9FGV1004 Block Diagram
Figure 4. 9FGV1002 Block Diagram
Figure 5. 9FGV1001 Block Diagram
Equations
FVCO = FCRYSTAL × Feedback Divider (see register 0x1F)
9FGV1004: FOUT3 = FVCO / Integer Divider 1 (see registers 0x20 and 0x22)
FOUT2 = FVCO / Integer Divider 2 (see registers 0x21 and 0x22)
FOUT0 = FOUT1 = FVCO × JA Multiplier / (2 × FOD) (see registers 0x10 ~ 0x18 and 0x24)
9FGV1002: FOUT0 = FOUT1 = FOUT2 = FOUT3 = FVCO × JA Multiplier / (2 × FOD) (see registers 0x10 ~ 0x18 and 0x24)
9FGV1001: FOUT0 = FOUT1 = FOUT2 = FOUT3 = FVCO / Integer Divider 1 (see registers 0x20 and 0x22)
Limits
FCRYSTAL: 10MHz ~ 40MHz
FVCO: 2300MHz ~ 2600MHz
Integer Divider 1 and 2: 8 ~ 4095
FOD: 4 ~ 255

10©2016 Integrated Device Technology, Inc. November 18, 2016
9FGV100x Register Descriptions and Programming Guide User Guide
Appendix 1: Fractional Output Divider Configuration
The Fractional Output Divider (FOD) is composed of an 8 bit integer portion (address 0x12) and a 16 bit fractional portion (addresses
0x13 and 0x14).
FOD value P = INT(P) + FRAC(P) = FVCO / (2 × FOUT) (1)
FOD Integer [7..0] = DEC2HEX(INT(P)) (2)
The FOD divides the VCO frequency FVCO down to the desired output frequency FOUT. Please note the additional /2 between the VCO
and the FOD.
Convert FRAC(P) to hex with Eq.2 where ROUND2INT means to round to the nearest integer. The round-off error of P in ppm is the
output frequency error in ppm.
FOD Fraction [15..0] = DEC2HEX(ROUND2INT(216×FRAC(P))) (3)
Example: If the VCO is 2500MHz and the desired output frequency is 148.5MHz, the FOD value is 2500/(2×148.5)=8.4175084.
The integer portion is 8 so address 0x12 will be 08-hex.
The fractional portion is 0.4175084.
FOD Fraction [15..0] = DEC2HEX(ROUND2INT(216×0.4175084) = DEC2HEX(ROUND2INT(27361.83))
= DEC2HEX(27362) = 6A E2
Address 0x13 = 6A-hex and address 0x14 = E2-hex.
There is a small error from the rounding. The actual FOD value is 8 + 27362 / 216 = 8.4175110.
The rounding error is 8.4175110 / 8.4175084 - 1 = 0.31ppm.