Renesas RH850/F1K Installation and operating instructions

APPLICATION NOTE
R01AN2911EJ0100 Rev. 1.00 Page 1 of 46
Aug 04, 2016
RH850/F1K Series
Hardware Design Guide
Introduction
This application note is intended to provide RH850/F1K series specific information and recommendations on the device
usage. It should be used in conjunction with the corresponding RH850/F1K series user manual (includes the electrical
characteristics).
Target Device
RH850/F1K Group
RH850/F1K ECO Line
176 pin
144 pin
RH850/F1K ADVANCED line
176 pin
144 pin
100 pin
RH850/F1K PREMIUM Line
176 pin
144 pin
100 pin
R01AN2911EJ0100
Rev. 1.00
Aug 04, 2016

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Table of Contents
1. Power Supply..................................................................................................................6
1.1 Power Supply Overview of RH850/F1K Group ......................................................................... 6
1.1.1 Power Supply Pin Overview of RH850/F1K Group................................................................. 6
1.1.2 Power Supply Pin Configuration of RH850/F1K Group .......................................................... 6
1.1.3 Power Supply Pin Architecture of RH850/F1K Group ............................................................ 6
1.1.4 Power Supply Timing of RH850/F1K Group ......................................................................... 10
1.2 Principle Capacitor Placement at REGVCC of RH850/F1K Group ....................................... 11
2. Minimum External Components..................................................................................12
2.1 Minimum External Components of RH850/F1K Group.......................................................... 12
3. Oscillator.......................................................................................................................15
3.1 Recommended Oscillator Circuit ............................................................................................ 15
3.1.1 Main Oscillator ...................................................................................................................... 15
3.1.2 Sub Oscillator........................................................................................................................ 16
3.2 Recommended Oscillator Layout ............................................................................................ 16
4. Device Pins ...................................................................................................................17
4.1 RESET ........................................................................................................................................ 17
4.1.1 Minimum RESET Circuit ....................................................................................................... 17
4.1.2 RESET Input Characteristics ................................................................................................ 18
4.2 General Purpose I/O.................................................................................................................. 19
4.2.1 RESET State of General Purpose I/O .................................................................................. 19
4.2.2 JP0_4/_DCUTRST................................................................................................................ 19
4.2.3 P8_6/_RESETOUT/NMI/CSIH0CSS4/PWGA38O/RTCAOUT/ADCA0I8S .......................... 19
4.2.4 Analog Filter Function ........................................................................................................... 21
4.2.5 Behavior during Low Power Mode ........................................................................................ 22
4.3 Recommended Connection of unused Pins........................................................................... 23
4.3.1 Recommended Connection of unused Pins for RH850/F1K Group ..................................... 23
4.4 Pin Assignment Differences .................................................................................................... 25
4.5 Injected Current......................................................................................................................... 26
5. A/D-Converter ...............................................................................................................27
5.1 Conversion Time ....................................................................................................................... 27
5.2 External Multiplexer Wait Time................................................................................................ 27
5.3 Equivalent Input Circuit ............................................................................................................ 28
5.4 External Circuit on ADC Input.................................................................................................. 29
6. Development and Test Tool Interface .........................................................................31
6.1 Development Tool Interface of RH850/F1K Group................................................................. 32
6.1.1 Debug Interface Connection of RH850/F1K Group .............................................................. 32
6.1.2 Flash Programming Interface Connection of RH850/F1K Group ......................................... 36

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6.1.3 Combined Debug and Flash Programming Interface Connection of RH850/F1K Group ..... 39
6.1.4 Debug and Flash Programming Interface Connection of RH850/F1K Group when the
internal HSOSC is used as Clock Supply ............................................................................. 40
6.1.5 Debug Considerations when Hot Plug-in is used ................................................................. 42
6.2 Boundary Scan Mode Interface of RH850/F1K Group ........................................................... 43
7. Reference Documents..................................................................................................44
8. Abbreviations ...............................................................................................................45
Website and Support...........................................................................................................46
Revision History ....................................................................................................................1
General Precautions in the Handling of MPU/MCU Products .............................................2

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Table of Figures
Figure 1 RH850/F1K Power supply architecture ............................................................................................... 7
Figure 2 RH850/F1K Power up/down timing ................................................................................................... 10
Figure 3 Principle capacitor placement at REGVCC for EMI at data flash operation ..................................... 11
Figure 4 Minimum external components for RH850/F1K (176pin) for normal operation mode ...................... 12
Figure 5 Recommended main oscillator circuit ............................................................................................... 15
Figure 6 Recommended sub oscillator circuit.................................................................................................. 16
Figure 7 Minimum RESET circuit .................................................................................................................... 17
Figure 8 External RESET timing...................................................................................................................... 18
Figure 9 RESETOUT pin behavior at OPBT0[9] = 1 ....................................................................................... 20
Figure 10 RESETOUT pin behavior at OPBT0[9] = 0 ..................................................................................... 20
Figure 11 Analog Filter Function ..................................................................................................................... 21
Figure 12 ADC conversion time....................................................................................................................... 27
Figure 13 ADC equivalent input circuit ............................................................................................................ 28
Figure 14 ADC external circuit on analog input ............................................................................................... 29
Figure 15 RH850/F1K 1pin Low-pin debug interface connection.................................................................... 32
Figure 16 RH850/F1K 4pin Low-pin debug interface connection.................................................................... 33
Figure 17 RH850/F1K Nexus, 4pin LPD and 1pin LPD debug interface connection ...................................... 34
Figure 18 RH850/F1K PG-FP5 flash programming interface connection ....................................................... 37
Figure 19 RH850/F1K E1 flash programming interface connection ................................................................ 38
Figure 20 RH850/F1K Combined debug and flash programming interface connections ................................ 39
Figure 21 RH850/F1K Debug and flash programming interface connections when the HSOSC is used as
clock supply ..................................................................................................................................................... 40
Figure 22 Circuit configuration for hot plug-in.................................................................................................. 42
Figure 23 Boundary scan connection of RH850/F1K ...................................................................................... 43

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Table of Tables
Table 1 Power supply pin overview ................................................................................................................... 6
Table 2 Power supply architecture RH850/F1K with single supply 5V ............................................................. 7
Table 3 Power supply architecture RH850/F1K with single supply 3.3V .......................................................... 7
Table 4 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V ................................................. 8
Table 5 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V ................................................. 8
Table 6 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V ................................................. 9
Table 7 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V ................................................. 9
Table 8 Minimum external components for RH850/F1K (176pin) ................................................................... 13
Table 9 Guidance values of the main oscillator circuit .................................................................................... 15
Table 10 Guidance values of the sub oscillator circuit .................................................................................... 16
Table 11 Guidance values for the minimum RESET circuit ............................................................................ 17
Table 12 Behavior during low power mode ..................................................................................................... 22
Table 13 Recommended Connection of unused Pins for RH850/F1K Group................................................. 23
Table 14 Basic pin assignment differences ..................................................................................................... 25
Table 15 ADC conversion time overview......................................................................................................... 27
Table 16 Equivalent input circuit of ADCA0..................................................................................................... 28
Table 17 Equivalent input circuit of ADCA1..................................................................................................... 28
Table 18 Basic external ADC input circuit ....................................................................................................... 29
Table 19 Operation mode overview................................................................................................................. 31
Table 20 Operation mode description ............................................................................................................. 31
Table 21 Debug interface signal connection of RH850/F1K ........................................................................... 35
Table 22 Basic flash programming connection of RH850/F1K........................................................................ 36
Table 23 PG-FP5 Flash programming signal connection of RH850/F1K........................................................ 37
Table 24 E1 Flash programming signal connection of RH850/F1K ................................................................ 38

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1. Power Supply
1.1 Power Supply Overview of RH850/F1K Group
1.1.1 Power Supply Pin Overview of RH850/F1K Group
The devices of the RH850/F1K group have the following power supply pins.
Table 1 Power supply pin overview
Device
Power Supply Pins
RH850/F1K (176pin)
REGVCC
EVCC, EVSS
AnVREF, AnVSS (n = 0, 1)
RH850/F1K (144pin)
REGVCC
EVCC, EVSS
AnVREF, AnVSS (n = 0, 1)
RH850/F1K (100pin)
REGVCC
EVCC, EVSS
A0VREF, A0VSS
The pins AWOVCL, AWOVSS and ISOVCL, ISOVSS are available on all devices to connect external capacitors.
1.1.2 Power Supply Pin Configuration of RH850/F1K Group
Depending on the device, the following power supply pin configuration applies:
The EVCC supply pins are internally connected.
1.1.3 Power Supply Pin Architecture of RH850/F1K Group
The RH850/F1K group supports different power supply architectures. The power supply architecture depends on the
chosen RH850/F1K group device, application requirements and the use case.
Some common conditions apply to the supply of the RH850/F1K group:
REGVCC = EVCC = VPOC to 5.5V
A0VREF = 3.0V to 5.5V
A1VREF = 3.0V to 5.5V
AWOVSS = ISOVSS = EVSS = A0VSS = A1VSS = 0V
The following figure and the different cases describe the impact to the ADC ports and the ports with analog/digital
function depending on the power supply architecture. In addition, it describes the limitations to these ports.

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Figure 1 RH850/F1K Power supply architecture
Table 2 Power supply architecture RH850/F1K with single supply 5V
Case 1 –Single Supply 5V
Condition
REGVCC = 5V
EVCC = 5V
A0VREF = 5V
A1VREF = 5V
Port Function
AP0 –Port usable with analog or digital function
P8 –Port usable with analog or digital function
P9 –Port usable with analog or digital function
AP1 –Port usable with analog or digital function
P18 –Port usable with analog or digital function
Limitation
No limitation applies

Operation permitted
Table 3 Power supply architecture RH850/F1K with single supply 3.3V
Case 2 –Single Supply 3.3V
Condition
REGVCC = 3.3V
EVCC = 3.3V
A0VREF = 3.3V
A1VREF = 3.3V
Port Function
AP0 –Port usable with analog or digital function
P8 –Port usable with analog or digital function
P9 –Port usable with analog or digital function
AP1 –Port usable with analog or digital function
P18 –Port usable with analog or digital function
Limitation
No limitation applies

Operation permitted
RH850/F1K Group
AWO-Area ISO-Area
AP0
P8
P9
AP1
P18
REGVCC
A0VREF
EVCC
EVCC
A1VREF
EVCC

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Table 4 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V
Case 3 –Mixed Supply 5V & 3.3V
Condition
REGVCC = 5V
EVCC = 3.3V
A0VREF = 5V
A1VREF = 5V
Port Function
AP0 –Port usable with analog or digital function
P8 –Port usable with analog or digital function
P9 –Port usable with analog or digital function
AP1 –Port usable with analog or digital function
P18 –Port usable with analog or digital function
Limitation
Common condition REGVCC = EVCC not met

Operation not permitted
Table 5 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V
Case 4 –Mixed Supply 5V & 3.3V
Condition
REGVCC = 3.3V
EVCC = 3.3V
A0VREF = 5V
A1VREF = 5V
Port Function
AP0 –Port usable with analog or digital function
P8 –Port usable with analog or digital function, analog input voltage
limited to max. 3.3V, reduced AD conversion range between 0V to 3.3V
P9 –Port usable with analog or digital function, analog input voltage
limited to max. 3.3V, reduced AD conversion range between 0V to 3.3V
AP1 –Port usable with analog or digital function
P18 –Port usable with analog or digital function, analog input voltage
limited to max. 3.3V, reduced AD conversion range between 0V to 3.3V
Limitation
Analog port function limitation applies to P8, P9 and P18

Operation permitted
3FFh
0V
3.3V
5V
2A3h
0V
3.3V
5V
Note: Conversion range example based on 10-bit ADC resolution
Analog input channel on AP0,
AP1
Analog input channel on P8, P9,
P18
Reduced AD conversion range

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Table 6 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V
Case 5 –Mixed Supply 5V & 3.3V
Condition
REGVCC = 3.3V
EVCC = 3.3V
A0VREF = 5V
A1VREF = 5V
Port Function
AP0 –Port usable with analog or digital function
P8 –Port usable with digital function only
P9 –Port usable with digital function only
AP1 –Port usable with analog or digital function
P18 –Port usable with digital function only
Limitation
No limitation applies to P8, P9 and P18 when these ports are used as
digital port only.

Operation permitted
Table 7 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V
Case 6 –Mixed Supply 5V & 3.3V
Condition
REGVCC = 5V
EVCC = 5V
A0VREF = 3.3V
A1VREF = 3.3V
Port Function
AP0 –Port usable with analog or digital function
P8 –Port usable with analog or digital function, analog input voltage
limited to max. 3.3V
P9 –Port usable with analog or digital function, analog input voltage
limited to max. 3.3V
AP1 –Port usable with analog or digital function
P18 –Port usable with analog or digital function, analog input voltage
limited to max. 3.3V
Limitation
Analog port function limitation applies to P8, P9 and P18.

Operation permitted

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1.1.4 Power Supply Timing of RH850/F1K Group
The RH850/F1K group has a recommended power supply timing.
The voltage slope of the different power supply pins is defined with min. 0.02V/ms and max. 500V/ms.
For details on the electrical characteristics, please refer to the corresponding device RH850/F1K hardware user’s
manual.
Figure 2 RH850/F1K Power up/down timing
Note: tVS is the timing of the voltage slope
REGVCC/EVCC
2.7V 2.7V
A0VREF
A1VREF
3.0V
3.0V 3.0V
3.0V
0V
0V
0V
0V
0V
0V
tr3 = min. 0µs, max. 60µs
tr4 = min. 0µs, max. 60µs
tf3 = max. 0.5/tVS
tf4 = max. 0.5/tVS

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1.2 Principle Capacitor Placement at REGVCC of RH850/F1K Group
When the data flash of the RH850/F1K group will be used in the application it should be considered to add an
additional capacitor to the REGVCC pin and to use a close component placement to the supply pin in order to optimize
the EMI noise behavior during the program and erase operation of the data flash.
The following recommendations shall be considered for the capacitor placement of the additional capacitor for EMI
optimization during data flash operation at the REGVCC pin:
Capacitor: 4.7µF to 10µF
Pin: REGVCC
Layout/distance: Capacitor within 10mm from mounting pad
Figure 3 Principle capacitor placement at REGVCC for EMI at data flash operation
Mounting pad
AWOVSS
AWOVCL
REGVCC
0.1µF
for
AWOVCL
4.7µF to 10µF
for REGVCC to
optimize noise
during Data
Flash P/W
max. 4mm
max. 10mm
0.1µF
for
REGVCC
...
...

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2. Minimum External Components
The RH850/F1K series requires a certain number of external connections and components for a proper operation in
normal operation mode. The components are shown in different categories depending on the device operation and the
use case.
2.1 Minimum External Components of RH850/F1K Group
Figure 4 Minimum external components for RH850/F1K (176pin) for normal operation mode
Note: The debug interface connections shown covers Nexus, LPD 1pin and LPD 4pin. For details of the single debug
connection, please refer to the corresponding debug interface connection chapter. For details of other external
components, refer to their related chapters.
Port
EVCC EVCC
ADCA1
AD1
Port
EVCC ISOVCL
Port
EVCCREGVCC AWOVCL
ADCA0
AD0
A0VREF
C5
EVCC
C6 C7
C8
A1VREF
C10C11
REGVCC
C9C14 C13
X1
X2
IP0_0
XT 1
RESET
FLMD0
P10_8/FLMD1
DCUTRST
DCUTDI
DCUTDO
DCUCLK
DCURDY
DCUTMS
EVCC
C12
EVCC
Debug
VDD
REG
Logic
Logic Flash
REG
REG
C1
Q1
Q2
C2
C3
C4
R1
R2
R3
R4
R5
Core
C15
R6
EVTO
EVCC
R7
R8

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Table 8 Minimum external components for RH850/F1K (176pin)
Component
Value
Category
Min.
Typ.
Max.
Q1
16MHz
-
24MHz
Typical
Q2
-
32.768kHz
-
Typical
R1
-
100kΩNote 1
-
Typical
R2
1kΩNote 3
4.7kΩNote 3
6.6kΩNote 3
Required
R3
86kΩNote 6
100kΩNote 7
105kΩNote 6
Required
R4
-
10kΩNote 5, 7
-
Typical
R5
-
1k to 4.7kΩNote 4, 7, 8
-
Typical
R6
10kΩNote 9
-
100kΩNote 9
Required
R7
-
0ΩNote 1
-
Typical
R8
-
OptionalNote 10
-
Typical
C1, C2
-
10pFNote 1
-
Typical
C3, C4
-
12pFNote 1
-
Typical
C5, C6, C7, C8,
C10, C11, C12,
C14
-
100nFNote 2
-
Recommended
C9, C13
70nF
ESR: max. 40 [mΩ]
100nF
ESR: max. 40 [mΩ]
130nF
ESR: max. 40 [mΩ]
Required
C15
-
1nF to 10nFNote 3
-
Recommended
Notes 1.
The shown values for reference only.
The final values must be evaluated (with the resonator manufacturer).
2.
The shown values are for reference only.
It must be ensured (by the schematic/PCB designer) that the voltage levels at the device pins always
remain within the specified range of the electrical characteristics (described in the RH850/F1K hardware
user’s manual).
3.
See chapter RESET for details.
4.
For values much smaller than the typical values, the connected devices might not be able to apply a low
level to the signal. Additionally higher currents will flow through the resistor / device.
5.
A low level must be applied to FLMD1 in case FLMD0 becomes ‘1’ for external flash programming.
As a minimum value, a direct connection to VSS can be applied. But in case the related port (P10_8) is
switched to output ‘1’, it will damage the port/device.
6.
In case of smaller values than the min. value, the typically connected device (E1) is not able to apply a
high (‘1’) signal.
7.
For values much higher than the typical value, the required signal timings might not be achieved due to
the weaker currents. Additionally environmental effects (e.g. moisture and dirt) might generate other
weak currents and therefore influence the signal.
8.
See chapter Development and Test Tool Interface for details.
9.
See chapter JP0_4/_DCUTRST and chapter Recommended Connection of Unused Pins for details.
10.
The resistor is only required when the JTAG/Nexus interface is used for debugging and depends on the
specification of the 3rd party development tool specification. See chapter Development and Test Tool
Interface for details.
The definition of components categories is as follows:
•Required component
Component that must be implemented as part of the device specification.

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•Recommended component
Component that is not required by the device specification, but is provided in order to secure the device
operating conditions. The component value depends on the application requirements and must be evaluated
with best engineering practice.
•Typical component
Component that is not required by the device specification, but typically is provided in order to fulfil a use case.
The component value depends on the application requirements and must be evaluated with best engineering
practice.
In order to improve the electromagnetic interference and susceptibility it is recommended to add a capacitor of typ.
4.7µF to 10µF in parallel to the capacitor C15 at REGVCC. The value and PCB placement of the parallel capacitor
depends on the application requirements.

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3. Oscillator
3.1 Recommended Oscillator Circuit
3.1.1 Main Oscillator
A crystal or ceramic resonator can be connected to the main clock input pins as shown below.
Figure 5 Recommended main oscillator circuit
General guidance values of the main oscillator circuit:
Table 9 Guidance values of the main oscillator circuit
Component
Value
MOSC
16MHz, 20MHz, 24MHz
C1
10pF
C2
10pF
Rd
0Ω
Caution
Values of C1, C2 and Rd depend on the use of ceramic or crystal resonator and must be specified in cooperation
with ceramic or crystal resonator manufacturer.
X1 X2
MOSC
C2C1
Rd
internal
external
X1 X2
MOSC
C2
C1
Rd
internal
external

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3.1.2 Sub Oscillator
A crystal resonator can be connected to the sub clock input pins as shown below.
Figure 6 Recommended sub oscillator circuit
General guidance values of the sub oscillator circuit:
Table 10 Guidance values of the sub oscillator circuit
Component
Value
SOSC
32.768kHz
C1S
12pF
C2S
12pF
RdS
100kΩ
Caution
Values of C1S, C2S and RdS depend on the crystal resonator used and must be specified in cooperation with a
crystal resonator manufacturer.
3.2 Recommended Oscillator Layout
General guidance for PCB layout:
•Keep the wiring length as short as possible
•Do not cross the wiring with other signal lines
•Do not route this circuit close to a signal line with high fluctuating current flow
•Always make the ground point of the oscillator capacitor the same potential as AWOVSS
•Do not ground the capacitor to a ground pattern with high current flow
•Do not tap signals from the oscillator
For further layout, related recommendations please refer to the application note “PCB-Design for Improved EMC”
(R01AN0733EDxxxx).
RdS
XT1 IP0_0
SOSC
C2SC1S
internal
external

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4. Device Pins
4.1 RESET
4.1.1 Minimum RESET Circuit
The RH850/F1K series has an on-chip Power-on Clear (POC) circuit. Therefore, a specific external RESET circuit is
not required and the minimum requirement of the RESET circuit is a resistor to EVCC for start-up of the device. The
resistor should be dimensioned large enough to allow a RESET signal generated by development tool or flash
programmer to control the RESET pin.
In addition, a capacitor should be added as protection against surges.
Figure 7 Minimum RESET circuit
General guidance values of the minimum RESET circuit:
Table 11 Guidance values for the minimum RESET circuit
Component
Value
R1
1 to 10kΩ
R2
100Ω
C1
1 to 10nF
The series resistor R2 is optional to suppress external signals from EMC point of view and depends on the application
requirements.
The capacitor C1 can be adopted to a different value when the AC specification of the RESET (terminal) timing, the AC
specification of the serial programmer setup timing and the EMC requirements of the ECU are fulfilled.
For further layout, related recommendations please refer to the application note “PCB-Design for Improved EMC”
(R01AN0733EDxxxx).
RESET
EVCC
RH850/F1x
Development Tool,
Flash Programmer
R1
C1
R2

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4.1.2 RESET Input Characteristics
The RESET is passed through an internal analog noise filter to prevent erroneous resets due to spikes.
The following figure shows the timing when an external reset is performed. It explains the effect of the noise
elimination.
Figure 8 External RESET timing
The analog filter generates the analog delay. The filter regards pulses up to a certain width as noise and suppresses them.
For the minimum RESET pulse width and the minimum RESET pulse rejection, refer to the electrical characteristics
described in the RH850/F1K hardware user’s manual.
System RESET
RESET
Analog delay Analog
delay
Analog delay Analog
delay

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4.2 General Purpose I/O
4.2.1 RESET State of General Purpose I/O
During RESET state, all general-purpose I/O pins are in input mode with high-Z behavior except the pin
P8_6/_RESETOUT.
4.2.2 JP0_4/_DCUTRST
During power-on, RESET the pin JP0_4 should not be driven externally to high-level. Therefore, JP0_4/_DCUTRST
has to be connected in all device operation modes to EVSS via a resistor.
4.2.3 P8_6/_RESETOUT/NMI/CSIH0CSS4/PWGA38O/RTCAOUT/ADCA0I8S
When the _RESETOUT signal is selected for the P8_6 pin the output on the pin is at low level during a reset and after
release from the reset state depending on the option byte setting (OPBT0[9] register).
P8_6 with alternate function
When P8_6 shall be used with an alternate function (e.g. NMI/CSIH0CSS4/PWGA38O/RTCAOUT, etc.), it has to be
considered that the pin P8_6 is on low level after a Power-on RESET or any other device RESET source until it is
released by the application software.
P8_6 and RESETOUT function
The pin P8_6 has an emulated RESETOUT function as default function. By this function, this pin can drive an output to
low-level during and after reset, e.g. to reset an external ASIC. In addition, that RESETOUT function can be disabled
that the pin P8_6 behaves like other pins with high-z during RESET state.
For further details, please refer to the chapter “P8_6: RESETOUT” of the RH850/F1K hardware user’s manual.

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Aug 04, 2016
Figure 9 RESETOUT pin behavior at OPBT0[9] = 1
Figure 10 RESETOUT pin behavior at OPBT0[9] = 0
Caution
Until being disabled by register settings, the pin P8_6 drives an output low-level or high-z after any kind of reset.
To avoid a data collision, the outside circuit connected to the P8_6 pin must not drive high-level.
EVCC/REGVCC
RESET
P8_6
Execution of
user application
starts
P8_6 set to 1
RESET is
asserted
P8_6 changed to output
low level by any RESET
Flash operation Flash sequence Flash sequence
RESETOUT I/O RESETOUT
RESETOUT
enable
RESETOUT
enable
Data transfer of
option byte
(OPBT0[9])
EVCC/REGVCC
RESET
P8_6
Execution of
user application
starts
P8_6 set to 1
RESET is
asserted
P8_6 changed to output
low level by any RESET
Flash operation Flash sequence Flash sequence
RESETOUT I/O RESETOUT
RESETOUT
enable
RESETOUT
enable
Data transfer of
option byte
(OPBT0[9])
High-z