Rohm LAPIS ML22594 MB Series User manual

FEDL22594-06
Issue Date: Oct. 16. 2017
ML22594-xxxMB
4-Channel Mixing Speech Synthesis LSI with Built-in MASK ROM for Automotive
1/73
GENERAL DESCRIPTION
The ML22594-xxx is 4-channel mixing speech synthesis LSIs with built-in MASK ROM for voice data. These
LSIs incorporate into them an HQ-ADPCM decoder that enables high sound quality, 16-bit D/A converter,
low-pass filter, 1.0 W monaural speaker amplifier for driving speakers , and over-current detectible function for
Speaker Pins. And the high quality and a long time sound regeneration is possible by using the voice
regeneration which the outside ROM was used for.
Since functions necessary for voice output are all integrated into a single chip, a system can be upgraded with
audio features by only using one of these LSIs.
•Capacity of internal memory and the maximum voice production time (when HQ-ADPCM※1method used)
Product name ROM capacity Maximum voice production time (sec)
fsam = 8.0 kHz fsam = 16.0 kHz fsam = 32.0 kHz
ML22594- xxx 6 Mbits(Internal) 243 121 60
128 Mbits(Exteranal) 5240 2620 1310
FEATURES
•ROM capacity: Internal 6Mbits, External 128Mbits (Max)
•Speech synthesis method: Can be specified for each phrase.
HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
•Sampling frequency: Can be specified for each phrase.
12.0/24.0/48.0 kHz, 8.0/16.0/32.0 kHz, 6.4/12.8/25.6 kHz
•Built-in low-pass filter and 16-bit D/A converter
•Built-in speaker driver amplifier: 1.0 W, 8Ω(at DVDD = 5 V)
(with over-current detectible function for Speaker pins)
•External analog voice input (built-in analog mixing function)
•CPU command interface: Clock synchronous serial interface
•Maximum number of phrases: 1024 phrases, from 000h to 3FFh
•Edit ROM
•Volume control: CVOL command: Adjustable through 32 levels (including OFF)
AVOL command: Adjustable through 50 levels (including OFF)
•Repeat function: LOOP command
•Channeｌmixing function: 4 channels
•Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the
OFF setting)
•Source oscillation frequency: 4.096 MHz
•Power supply voltage: 4.5 to 5.5 V
•Operating temperature range: –40°C to +105°C※2
•Package: heat sink type 30-pin plastic SSOP(P-SSOP30-56-0.65-Z6K)
•Product name: ML22594-xxxMB (“xxx” denotes ROM code number)
※1
HQ-ADPCM is a high sound quality audio compression technology of "Ky's".
“Ｋｙ’ｓ” is a Registered trademark of National Universities corporate Kyushu
Institute of Technology
※2
The limitation on the operation time changes by the using condition.
(Refer to "LIMITATION ON THE OPERATION TIME (PLAY-BACK TIME)")

FEDL22594-06
ML22594-XXX
The table below summarizes the differences between the exsisting speech synthesis LSIs (ML225XG and
ML22Q573) and the ML22594.
Item
ML22Q573
ML2257X
ML22Q553
ML22594
CPU interface
Serial
Serial
← ←
ROM type
FLASH
MASK
FLASH
MASK
ROM capacity
4 Mbits
2/4 Mbits
4 Mbits
6 Mbits
External ROM
interface
No ←←Serial
Playback method
HQ-ADPCM
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
←←←
Maximum number of
phrases 1024 ←←1024
(Internal512 /
External512)
Sampling frequency
(kHz)
6.4/8.0/12.0/
12.8/16.0/24.0/
25.6/32.0/48.0 ←←←
Clock frequency 4.096 MHz (has a
crystal oscillator
circuit built-in)
←←←
D/A converter
16-bit voltage-type
←
←
←
Low-pass filter
FIR interpolation
filter
(High-pass
interpolation)
←←←
Speaker driving
amplifier
Built-in
1.0 W
(8Ω, DVDD = 5 V) ←←←
Over-current
detectible function
for Speaker Pins
No ←Yes ←
Simultaneous sound
production function
(mixing function) 4-channel ←←←
Edit ROM
Yes
← ← ←
Volume control
32 levels
←
←
←
Silence insertion 20 to 1024 ms
(4 ms steps)
←←←
Repeat function
Yes
←
←
←
External analog
input
Yes ←←←
External speech
data input No ←←←
Interval at which a
seam is silent during
continuous playback
(*1)
No ←←←
Power supply
voltage 2.7 V to 5.5 V ←4.5 V to 5.5 V ←
Ambient
temperature
-40゜C to 105゜C ← ←←
Package
30-pin SSOP
←
←
←

FEDL22594-06
ML22594-XXX
3/73
*1: Continuous playback as shown below is possible.
(Playback method: 8-bit straight PCM, 8-bit non-linear PCM, 16-bit straight PCM)
1 phrase
1 phrase
No silence interval

FEDL22594-06
ML22594-XXX
4/73
BLOCK DIAGRAM
The block diagrams of the ML22594-xxx are shown below.
Block Diagram of ML22594-xxx
Timing
Controller
I/O
Interface
Address Controller
SPM
RESETB
CSB
SCK
SI
SO
CBUSYB
STATUS
ERR
DIPH
OSC
XTB
XT
SPV
DD
SPGND
PLL
PCM Synthesizer
LPF(CVOL)
16bit DAC
SP-AMP
(AVOL)
SPP
AIN
DV
DD
DGND
V
DDL
SG
TESTI1
Cmd Analyzer
6Mbits MASKROM
Serial ROM Interface
ESCK
ESO
ESI
IOV
DD
ECSB
FLW

FEDL22594-06
ML22594-XXX
5/73
PIN CONFIGURATION (TOP VIEW)
●ML22594-xxx
30-Pin Plastic SSOP
NC：Unused pin
AIN
SG
NC
DV
DD
DGND
V
DDL
DIPH
STATUS
ERR
CSB
SCK
SI
SO
CBUSYB
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SPV
DD
SPGND
SPP
SPM
ESI
ESO
ESCK
ECSB
TESTI1
FLW
RESETB
IOVDD
DV
DD
XT
XTB
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

FEDL22594-06
ML22594-XXX
6/73
PIN DESCRIPTION (1)
Pin Symbol I/O Attribute Description Attribute
Initial
value
(*1)
1 AIN I —
Speaker amplifier input pin.
analog 0
2 SG O —
Built-in speaker amplifier’s reference voltage output pin.
Connect a capacitor of 0.1 µF or more between this pin and
DGND. analog 0
3 NC — — NC(Unused) pin analog 0
4,18 DVDD — — Digital power supply pin. Connect a bypass capacitor of 10µF or more between this
pin and DGND.
power —
5,15
DGND
—
—
Digital ground pin
gnd
—
6 VDDL O — 2.5 V regulator output pin. Acts as an internal power supply (for logic). Connect a
capacitor of 10
µ
F or more between this pin and DGND.
power 0
7 DIPH I Positive
Serial interface switching pin.
Pin for choosing between rising edges and falling edges as
to the edges of the SCK pulses used for shifting serial data
input to the SI pin into the inside of the LSI.
When this pin is at a “L” level, SI input data is shifted into the
LSI on the rising edges of the SCK clock pulses and a status
signal is output from the SO pin on the falling edges of the
SCK clock pulses.
When this pin is at a “H” level, SI input data is shifted into the
LSI on the falling edges of the SCK clock pulses and a status
signal is output from the SO pin on the rising edges of the
SCK clock pulses.
digital 0
8 STATUS O Positive Channel status output pin.
Outputs the BUSYB or NCR signal for each channel by
inputting the OUTSTAT command. digital 1
9 ERR O Positive Error output pin.
Outputs a “H” level if an error occurs.
digital 0
10 CSB I Negative
Chip select pin.
A “L” level on this pin accepts the SCK or SI inputs. When
this pin is at a “H” level, neither the SCK nor SI signal is input
to the LSI.
digital 1
11
SCK
I
Positive
Synchronous serial clock input pin.
clk
0
12 SI I —
Synchronous serial data input pin.
When the DIPH pin is at a “L” level, data is shifted in on the
rising edges of the SCK clock pulses.
When the DIPH pin is at a “H” level, data is shifted in on the
falling edges of the SCK clock pulses.
digital 0
13 SO O Positive
Channel status serial output pin.
Outputs a status signal on the falling edges of the SCK clock
pulses when the DIPH pin is at a ”L” level; outputs a status
signal on the rising edges of the SCK clock pulses when the
DIPH pin is at a ”H” level.
When the CSB pin is at a ”L” level, the status of each channel
is output serially in sync with the SCK clock. When the CSB
pin is at a ”H” level, this pin goes into a high impedance state.
digital Hi-Z

FEDL22594-06
ML22594-XXX
7/73
PIN DESCRIPTION (2)
Pin Symbol I/O Attribute Description Attribute
Initial
value(*1)
14 CBUSYB O Negative
Command processing status signal output pin.
This pin outputs a “L” level during command processing.
Be sure to enter commands with the CBUSYB pin driven
at a “H” level.
digital (*2)
16 XTB O Negative
Connects to a crystal or a ceramic resonator.
When using an external clock, leave this pin open.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
clk 1
17 XT I Positive
Connects to a crystal or a ceramic resonator.
A feedback resistor of around 1 MΩis built in between this
XT pin and the XTB pin. When using an external clock,
input the clock from this pin.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
clk 0
19 IOVDD I —
External ROM interface power supply pin.
Use the power supply which is the same as the external
ROM.
Connect a bypass capacitor of 0.1µF or more between
this pin and DGND.
analog 0
20 RESETB I Negative
Reset input pin.
At “L” level input, the LSI enters the initial state. After a
reset input, the entire circuit is stopped and enters a
power down state. Upon power-on, input a “L” level to
this pin. After the power supply voltage is stabilized,
drive this pin at a “H” level.
This pin has a pull-up resistor built in.
digital 0
21 FLW I Positive
External ROM interface disenable pin.
When a “H” level is inputted, the external ROM interface is
disenable. “L” level is inputted, the external ROM interface
is enable. Has a pull-down resistor built in.
digital 0
22 TESTI1 I Negative
Used as either an input pin for testing or a reset input pin
for Flash rewriting. Has a pull-down resistor built in.
digital 0
23 ECSB O Negative
External ROM interface chip select pin.
A “L” level is external ROM access. digital 1
24 ESCK O Positive External ROM interface serial clock output pin. digital 1
25 ESO O Positive External ROM interface serial data output pin. digital 1
26 ESI I Positive External ROM interface serial data input pin.
Has a pull-down resistor built in. digital 0
27
SPM
O
—
Output pin of the built-in speaker amplifier.
analog
Hi-Z
28 SPP O — Output pin of the built-in speaker amplifier.
Can be configured as an AOUT amplifier output by
command setting.
analog 0
29 SPGND — — Speaker amplifier ground pin. gnd —
30 SPVDD — — Speaker amplifier power supply pin. Connect a bypass capacitor of 10µF or more between this
pin and SPGND.
power —
*1: Indicates the initial value at reset input or during power down.
*2: When ML22594 is reset, this pin is "L" level, when ML22594 is power-down, this pin is "H" level.

FEDL22594-06
ML22594-XXX
8/73
ABSOLUTE MAXIMUM RATINGS DGND = SPGND = 0 V, Ta = 25°C
Parameter Symbol Condition Rating Unit
Power supply voltage DVDD
SPVDD
— −0.3 to +7.0 V
Input voltage VIN — −0.3 to DVDD+0.3 V
Power dissipation PDWhen the LSI is mounted on
JEDEC 4-layer board.
When SPVDD = 5V
1000 mW
Output short-circuit current IOS
Applies to all pins except
SPM, SPP, VDDL, and VDDR.
10 mA
Applies to SPM and SPP pins.
500
mA
Applies to VDDL and VDDR pins.
50
mA
Storage temperature
TSTG
—
−
55 to +150
°C
RECOMMENDED OPERATING CONDITIONS DGND = SPGND = 0 V
Parameter
Symbol
Condition
Range
Unit
DVDD, SPVDD
Power supply voltage DVDD SPVDD — 4.5 to 5.5 V
IOVDD
Power supply voltage IOVDD — 2.7 to 5.5 *1 V
Operating temperature
Top
—
−
40 to +105
°C
Master clock frequency fOSC —
Min.
Typ.
Max.
MHz
3.5
4.096
4.5
*1 : When External ROM interface does not be used, IOVDD can be set in 0V.

FEDL22594-06
ML22594-XXX
9/73
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD = SPVDD = 4.5 to 5.5 V, IOVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
“H” input voltage1(*1)
VIH1
—
0.8
×
DVDD
—
DVDD
V
“H” input voltage2(*2)
V
IH2
—
0.8×IOV
DD
—
IOV
DD
V
“L” input voltage1(*1)
VIL1
—
0
—
0.2
×
DVDD
V
“L” input voltage2(*2)
V
IL2
—
0
—
0.2×IOV
DD
V
“H” output voltage 1 (*3)
VOH1
IOH =
−
1 mA
DVDD
−
0.4
—
—
V
“H” output voltage 2 (*4)
V
OH2
I
OH
= −50 µA
DV
DD
−0.4
—
—
V
“H” output voltage 3 (*5)
VOH3
IOH =
−
1 mA
IOVDD
−
0.4
—
—
V
“L” output voltage 1 (*3)
V
OL1
I
OL
= 2 mA
—
—
0.4
V
“L” output voltage 2 (*4)
VOL2
IOL = 50 µA
—
—
0.4
V
“L” output voltage 3 (*5)
V
OL3
I
OL
= 2 mA
—
—
0.4
V
Output leakage current1
(*6) IOOH VOH = DVDD (CSB=“H”) — — 10 µA
IOOL VOL = DGND (CSB=“H”) −10 — — µA
Output leakage current2
(*7) IOOH VOH = IOVDD (FLW=“H”) — — 10 µA
IOOL VOL = DGND (FLW=“H”) −10 — — µA
“H” input current 1 (*8)
IIH1
VIH = DVDD
—
—
10
µA
“H” input current 2 (*9)
IIH2
VIH = DVDD
0.8
5.0
20
µA
“H” input current 3 (*10)
IIH3
VIH = DVDD
20
100
400
µA
“H” input current 4 (*11)
IIH4
VIH = IOVDD
2
100
400
µA
“L” input current 1 (*12)
IIL1
VIL = DGND
–10
—
—
µA
“L” input current 2 (*9)
IIL2
VIL = DGND
–20
−
5.0
−
0.8
µA
“L” input current 3 (*13)
IIL3
VIL = DGND
–400
–100
–20
µA
Supply current during
playback 1 IDD1
fOSC = 4.096 MHz
fs=48kHz, f=1kHz,
When 16bitPCM Playback
No output load
— — 54(*15) mA
— — 1(*16)
Supply current during
playback 2 (*14) IDD2
f
OSC
= 4.096 MHz
fs=48kHz, f=1kHz,
When 16bitPCM Playback
using External ROM
No output load
— — 50(*15) mA
— — 5(*16)
Supply current during
playback 3 IDD3 fOSC = 4.096 MHz
During silence playback
No output load
— — 47(*15) mA
— — 1(*16)
Power-down supply
current
IDDS1
Ta = −40 to +55°C
—
—
10(*17)
µA
Ta =
−
40 to +105°C
—
—
20(*17)
µA
(*1)Applies to the DIPH, CSB, SCK, SI, RESETB, TESTI1 and XT pins.
(*2)Applies to the FLW, ESI pins.
(*3)Applies to the STATUS, ERR, SO and CBUSYB pins.
(*4)Applies to the XTB pin.
(*5)Applies to the ECSB, ESCK and ESO pins.
(*6)Applies to the SO pin.
(*7)Applies to the ECSB, ESCK and ESO pins
(*8) Applies to the DIPH, CSB, SCK, SI and RESETB pins.
(*9) Applies to the XT pin.
(*10) Applies to the TESTI1 pin.
(*11) Applies to the FLW and ESI pins. (Typ. Is 5.0V condition)
(*12) Applies to the DIPH, CSB, SCK, SI, TESTI1, FLW and ESI pins.
(*13) Applies to the RESETB pin.
(*14) ECSB, ESCK and ESO pins load capacitance = 45pF(max)
(*15) Supply current which added DVDD and SPVDD.
(*16) Supply current which applies IOVDD.
(*17) Supply current which added DVDD, SPVDD and IOVDD.

FEDL22594-06
ML22594-XXX
10/73
Analog Section Characteristics
DVDD = SPVDD = 4.5 to 5.5 V, IOVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
AIN input resistance
RAIN
Input gain: 0 dB
10
20
30
k
Ω
AIN input voltage range VAIN — — SPVDD×
2/3 Vp-p
Line output resistance
RLA
At 1/2SPVDD output
—
—
100
Ω
LINE output load
resistance RLA At SPGND10kΩ load 10 — — kΩ
LINE output voltage range VAO At SPGND10kΩ load SPVDD /6 — SPVDD×
5/6
V
SG output voltage
VSG — 0.95x
SPVDD /2 SPVDD /2 1.05x SPVDD /2 V
SG output resistance
RSG
—
57
96
135
k
Ω
SPM, SPP output load
resistance RLSP — 6 8 — Ω
Speaker amplifier output
power PSPO SPVDD = 5.0V, f = 1 kHz
RSPO = 8
Ω
, THD
≦
10%
800 1000 — mW
Output offset voltage
between SPM and SPP
with no signal present VOF SPIN–SPM gain = 0 dB
With a load of 8Ω−50 — +50 mV
Regulator output voltage VDDL
VDDR
Output load current =
−
35 mA
2.25 2.5 2.75 V

FEDL22594-06
ML22594-XXX
11/73
AC Characteristics (1)
DVDD = SPVDD = 4.5 to 5.5 V, IOVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C
Parameter Symbol Condition Min. Typ. Max. Unit
Master clock duty cycle
fduty
—
40
50
60
%
RESETB input pulse width tRST — 10 — — µs
Reset noise rejection pulse width
tNRST
RESETB pin
—
—
0.1
µ
s
Noise rejection pulse width tNINP CSB, SCK, and SI pins — — 5 ns
Command input interval time1 tINT
fOSC = 4.096 MHz
At STOP/SLOOP/CLOOP/
VOL command input
After status read
10 — — µs
Command input interval time2 tINTC
fOSC = 4.096 MHz
After input first command at
two-time command input
mode
0 — — µs
Command input enable time tcm fOSC = 4.096 MHz
During continuous playback
At SLOOP input
— — 10 ms
At PUP command input
CBUSYB “L” level output time tPUP 4.096 MHz
At external clock input — — 4 ms
At AMODE command input
CBUSYB “L” level output time（*3）tPUPA1
4.096 MHz
At external clock input
POP = “0”
DAEN = “0”→”1”
or SPEN = “0”
→
”1”
39 41 43 ms
At AMODE command input
CBUSYB “L” level output time tPUPA2
4.096 MHz
At external clock input
POP = “1”
DAEN = “0”→”1”
(SPEN = “0”)
72 74 76 ms
At AMODE command input
CBUSYB “L” level output time tPUPA3
4.096 MHz
At external clock input
POP = “0”
DAEN = “0”→”1”
(SPEN = “0”)
32 34 36 ms
At PDWN command input
CBUSYB “L” level output time tPD fOSC = 4.096 MHz — — 10 µs
At AMODE command input
CBUSYB “L” level output time（*3）tPDA1
4.096 MHz
At external clock input
POP = “0”
DAEN = “1”→”0”
or SPEN = “1”
→
”0”
106 108 110 ms
At AMODE command input
CBUSYB “L” level output time tPDA2
4.096 MHz
At external clock input
POP = “1”
DAEN = “1”→”0”
(SPEN = “0”)
143 145 147 ms
At AMODE command input
CBUSYB “L” level output time tPDA3
4.096 MHz
At external clock input
POP = “0”
DAEN = “1”→”0”
(SPEN = “0”)
103 105 107 ms

FEDL22594-06
ML22594-XXX
12/73
CBUSYB “L” level output time 1 (*1) tCB1 fOSC = 4.096 MHz — — 10 µs
CBUSYB “L” level output time 2 (*2)
tCB2
fOSC = 4.096 MHz
—
—
3
ms
CBUSYB “L” level output time 3 (*4) tCB3fOSC = 4.096 MHz — — 200 µs
Note: Output pin load capacitance = 45 pF (Max.)
*1: Applies to cases where a command is input, except after the PUP, PDWN, PLAY, START or AMODE
command input.
*2: Applies to cases where the PLAY or START command is input.
*3: When FAD3-0 is initial value (8h)
*4: Applies to cases where the STOP command is input

FEDL22594-06
ML22594-XXX
13/73
AC Characteristics (2) CPU serial interface
DVDD = SPVDD = 4.5 to 5.5 V, IOVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C
Parameter Symbol Condition Min. Typ. Max. Unit
SCK input enable time from CSB fall
tESCK
—
100
—
—
ns
SCK hold time from CSB rise tCSH — 100 — — ns
Data floating time from CSB rise
tDOZ
R
L
= 3 k
Ω
—
—
100
ns
Data setup time from SCK rise tDIS1 DIPH = “L” 50 — — ns
Data hold time from SCK rise
tDIH1
DIPH = “L”
50
—
—
ns
Data output delay time from SCK fall tDOD1 DIPH = “L” — — 90 ns
Data setup time from SCK fall
tDIS2
DIPH = “H”
50
—
—
ns
Data hold time from SCK fall tDIH2 DIPH = “H” 50 — — ns
Data output delay time from SCK rise
tDOD2
DIPH = “H”
—
—
90
ns
SCK “H” level pulse width tSCKH — 100 — — ns
SCK “L” level pulse width
tSCKL
—
100
—
—
ns
CBUSYB output delay time from SCK rise tDBSY1 DIPH = “L” — — 90 ns
CBUSYB output delay time from SCK fall
tDBSY2
DIPH = “H”
—
—
90
ns
Note: Output pin load capacitance = 45 pF (Max.)
AC Characteristics (3) External ROM serial interface
DVDD = SPVDD = 4.5 to 5.5 V, IOVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ESCK input enable time from ECSB fall edge tECSS fOSC = 4.096 MHz 50 — — ns
ESCK input hold time from ECSB rise edge
tECSH
fOSC = 4.096 MHz
50
—
—
ns
Data setup time from ESCK rise edge tEDIS fOSC = 4.096 MHz 10 — — ns
Data hold time from ESCK rise edge
tEDIH
fOSC = 4.096 MHz
10
—
—
ns
Data output delay time from ESCK rise edge tEDOD fOSC = 4.096 MHz — — 5 ns
ESCK clock frequency
tESCKF
fOSC = 4.096 MHz
16.0
16.384
16.5
MHz
ESCK “H” level pulse width tESCKH fOSC = 4.096 MHz 26 — — ns
ESCK “L” level pulse width
tESCKL
fOSC = 4.096 MHz
26
—
—
ns
Data output delay time from FLW rise edge. tEFLH — — — 1 ms
Data output delay time from FLW fall edge.
tEFHL
—
—
—
1
ms
Note: Output pin load capacitance = 45 pF (Max.)

FEDL22594-06
ML22594-XXX
14/73
TIMING DIAGRAMS
CPU Serial Interface Data Timing (When DIPH = “L”)
CPU Serial Interface Data Timing (When DIPH = “H”)
External ROM Serial Interface Data Timing
CSB
SCK
SI
VIH
VIL
VIL
VIH
VIL
VIH
tESCK
tDIS1
tDIH1
tSCKH
tSCKL
tCSH
CBUSYB
tDBSY1
VOL
VOH
SO
VIL
VIH
tDOZ
tDOD1
CSB
SCK
SI
VIH
VIL
VIL
VIH
VIL
VIH
t
ESCK
t
DIS2
t
DIH2
t
SCKL
t
SCKH
t
CSH
CBUSYB
t
DBSY2
VOL
VOH
SO
VIL
VIH
t
DOZ
ECSB
ESCK
ESI
VIH
VIL
VIL
VIH
VIL
VIH
t
ECSS
t
EDIS
t
EDIH
t
ESCKH
t
ESCKL
t
ECSH
ESO
t
EDOD
VOL
VOH
t
ESCKF

FEDL22594-06
ML22594-XXX
15/73
Power-On Timing
Power Shut-down Timing
SPV
DD
VIH
VIL
t
RST
5V
RESETB
Status
Power down
Oscillation is stopped after power-on.
Be sure to power-on IOVDD after DVDD/SPVDD.
When IOVDD isn't used, it is possible that it is fixed in 0V.
Be sure to set “L”level the RESETB pin before the first command input.
DV
DD
5V
IOV
DD
3.3V
10%
90%
90%
SPV
DD
IOV
DD
Status
Be sure to power shut-down DVDD/SPVDD after IOVDD.
When IOVDD isn't used, it is possible that it is fixed in 0V.
DV
DD
5V
Power down
3.3V
5V

FEDL22594-06
ML22594-XXX
16/73
Reset Input Timing
Note: The same timing applies in cases where the Reset signal is input during waiting for command.
tRST
RESETB
Status
Power down
Playing
XTXTB
Oscillating
Oscillation stopped
VDDLSG
GND
SPM
GND
SPP
Hi-Z

FEDL22594-06
ML22594-XXX
17/73
Power-Up Timing
Power-Down Timing
VOH
VOL
t
PUP
CSB
Status
Oscillation stabilized
Performing reset
processing
SCK
SI
NCRn
BUSYBn
Power down
XTXTB
Oscillating
Oscillation stopped
VOH
VOL
Awaiting command
(internal)
(internal)
VOH
VOL
CBUSYB
VOH
VOL
CSB
Status
Command is being
processed
Power down
SCK
SI
NCRn
BUSYBn
Awaiting command
XTXTB
Oscillating
Oscillation
stopped
VOH
VOL
(internal)
(internal)
VOH
VOL
t
PD
CBUSYB

FEDL22594-06
ML22594-XXX
18/73
Playback Start Timing by the PLAY Command
*1: Length of the “L” interval of BUSYBn is = tCB2 + voice production time length.
Playback Stop Timing
VOH
VOL
CSB
Status
Command is being processed
Playing
SCK
SI
NCRn
BUSYBn
Command standby
SPM
1/2VDD
SPP
1/2VDD
VOH
VOL
Address is being
controlled
Awaiting command
Awaiting command
(*1)
PLAY command
1st byte
PLAY command
2nd byte
(internal)
(internal)
VOH
VOL
CBUSYB
t
CB1
t
CB2
VOH
VOL
CSB
Status
Awaiting command
SCK
SI
NCRn
BUSYBn
SPM
1/2VDD
SPP
1/2VDD
VOH
VOL
Playing
STOP command
(internal)
(internal)
VOH
VOL
CBUSYB
t
CB3
Command is being processed

FEDL22594-06
ML22594-XXX
19/73
Continuous Playback Timing by the PLAY Command
Silence Insertion Timing by the MUON Command
*1: The “L” level period of the NCR pin during playback or silence insertion operation varies depending on the
timing at which the MUON command is input.
VOH
VOL
CSB
Status
Playing phrase 1
SCK
SI
NCRn
BUSYBn
SPM
1/2VDD
SPP
1/2VDD
Address is being
controlled
Awaiting command
Playing phrase 2
t
CB1
t
cm
(internal)
(internal)
VOH
VOL
CBUSYB
t
CB2
t
CB1
PLAY command
1st byte
PLAY command
2nd byte
PLAY command
2nd byte
VOH
VOL
CSB
Status
Playing
SCK
SI
NCRn
BUSYBn
SPM
1/2VDD
SPP
1/2VDD
Address is being
controlled
Awaiting command
Silence is being inserted
t
CB1
Playing
Waiting for silence insertion to be finished
t
CB1
t
cm
VOH
VOL
CBUSYB
t
CB2
(*1)
(*1)
(internal)
(internal)
t
CB1
t
CB1
MUON command
1
st
byte
PLAY command
2
nd
byte
MUON command
2
nd
byte
PLAY command
1
st
byte
PLAY command
2
nd
byte
t
cm

FEDL22594-06
ML22594-XXX
20/73
Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands
Timing of Volume Change by the CVOL Command
VOH
VOL
CSB
Status
Playing
SCK
SI
NCRn
BUSYBn
SPM
1/2VDD
SPP
1/2VDD
Address is being
controlled
Awaiting command
Awaiting command
PLAY command
2
nd
byte
SLOOP command
Playing
Address is being
controlled
CLOOP command
t
INT
Command is being processed
VIH
VIL
VOH
VOL
CBUSYB
t
CB2
t
cm
(internal)
(internal)
VOH
VOL
CSB
Status
Awaiting command
SCK
SI
NCRn
BUSYBn
Command is being
processed
t
CB1
Awaiting command
CVOL command
1
st
byte
VOH
VOL
VOH
VOL
CBUSYB
(internal)
(internal)
t
CB1
Command is being
processed
Awaiting command
CVOL command
2
nd
byte