S3 Incorporated Trio64V+ User manual

S3 Incorporated
Trio64V+ Integrated Graphics/Video Accelerator
Trio64V+
Integrated
Graphics/Video
Accelerator
July 1995
S3 Incorporated
2770 San Tomas Expressway
Santa Clara, CA 95051-0968

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
NOTATIONAL CONVENTIONS
The following notational conventions are used in this data book:
Signal names are shown in all uppercase letters. For example, XD.
A bar over a signal name indicates an active low signal. For example, DE.
n·m indicates a bit field from bit n to bit m. For example, 7-0 specifies bits 7 through 0, inclusive.
nom indicates a signal (pin) range from n to m. For example D[7:0[ specifies data lines 7 through 0, inclusive
Use
of a trailing letter H indicates a hexadecimal number. For example, 7AH is a hexadecimal number.
Use of a trailing letter b indicates a binary number. For example, 010b is a binary number.
When numerical modifiers such as K or M are used, they refer to binary rather than decimal form. Thus, for example, 1 KByte would be
equivalentto 1024, not 1,000 bytes.
NOTICES
© Copyright 1995 S3 Incorporated. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form
or by any means, electronic, mechanical, photocopying, or otherwise, without the prior written consent of S3
Incorporated, 2770 San Tomas Expwy., Santa Clara CA 95051-0968. The S3 Corporate Logo, S3 on Board, S3 on Board design, Vision64,
Vision864, Vision868, Vision964, Vision968, Trio, Tri032, Tri064, Tri064V+, Streams Processor, MIC, Galileo,
SDAC, Scenic/MX1,
Scenic/MX2, Sonic/AD, Native-MPEG, No Compromise Integration, No Compromise Acceleration and Innovations in Acceleration are
trademarks
of S31ncorporated and S3 and True Acceleration are registered trademarks of S3 Incorporated. Othertrademarks referenced
in this documentare owned
by theirrespective companies. The material in this document is for information only and is subjectto change
without notice. 53 Incorporated reserves the right to make changes in the product design without resentation and 'vvithout notice to its
users.
Additional information may be obtained from:
S3lncorporated, Literature Department, 2770 San Tomas Expressway, Santa Clara, CA 95051-0968.
Telephone: [phone], Fax: [phone]

II·
Tri064V+ Integrated Graphics/Video Accelerator
S3 Incorporated
Table of Contents
List of Figures vi
List of Tables. . viii
Section 1: Introduction . 1-1
1.1 OVERViEW............. 1-2
1.2 S3 STREAMS PROCESSOR . . .. 1-2
1.3 S3 SCENIC HIGHWAY . . . . . .. 1-3
1.4 Trio64V+ CHANGES FROM THE
Trio64 . . . . . . . . . . . . . . .. 1-3
Section 2: Mechanical Data . . .. 2-1
2.1 THERMAL SPECIFICATIONS. 2-1
2.2 MECHANICAL DIMENSIONS .,. 2-1
Section 3: Pins . . . . . . . . . .. 3-1
3.1 PINOUT DIAGRAMS ........ 3-1
3.2 PIN DESCRIPTIONS ........ 3-4
3.3
PIN LISTS .............. 3-12
Section 4: Electrical Data ..... 4-1
4.1 MAXIMUM RATINGS ....... 4-1
4.2 DC SPECIFICATIONS. . . . . . . . 4-1
4.3 AC SPECIFICATIONS . . . . . . . . 4-3
4.3.1 RAMDAC AC Specifications . . 4-3
4.3.2 Clock Timing . . . . . . . . .. 4-4
4.3.3 Input/Output Timing . . . . . .
4-5
Section 5: Reset and Initialization 5-1
Section 6: System Bus Interfaces. 6-1
6.1 PCI BUS INTERFACE . . . 6-1
6.1.1 PCICONFIGURATION ..... 6-1
6.1.2 PCI Bus Cycles . . . . . . . .. 6-1
6.2 VL-BUS INTERFACE . . . . . . . . 6-6
6.2.1 VL-Bus Cycles. . . . . . . . . . 6-6
6.2.2
SRDY Generation. . . . . . .. 6-6
Section 7: Display Memory .... 7-1
7.1 DISPLAY MEMORY
CONFIGURATIONS
......... 7-1
7.2 DISPLAY MEMORY REFRESH ... 7-4
7.3 DISPLAY MEMORY FUNCTIONAL
TIMING
...... . . . . . . .. 7-4
7.4
1-CYCLE EDO DRAM SUPPORT. 7-9
7.5 DISPLAY MEMORY
ACCESS
CONTROL. . . . . . . . . . . .. 7-11
Section 8: RAMDAC Functionality 8-1
8.1 OPERATING MODES ........ 8-1
8.2 COLOR MODES . . . . . . . . . . . 8-2
8.2.1 8 Bits/Pixel -Mode 0 . . . . . . 8-2
8.2.2 Output-doubled 8 Bits/Pixel -
Mode 8
............. 8-2
8.2.3 15/16-Bits/Pixel -Modes 9
and
10 .............. 8-3
8.2.4 Packed 24 Bits/Pixel -Mode 12. 8-3
8.2.5 24 Bits/Pixel -Mode
13 . . . . . 8-3
8.3 RAMDAC REGISTER ACCESS . . . 8-3
8.4 RAMDAC SNOOPING. . . . . . . . 8-3
8.5
SENSE GENERATION ....... 8-3
8.6
POWER CONTROL . . . . . . .. 8-3
Section 9: Clock Synthesis and
Control ............... 9-1
9.1 CLOCK SYNTHESIS ......... 9-1
9.2 CLOCK REPROGRAMMING .... 9-2
9.3
DCLK CONTROL .......... 9-3
Section 10: Streams Processor . 10-1
10.1 INPUT STREAMS. . . . . . . .. 10-1
10.1.1 Primary Stream Input .... , 10-2
10.1.2 Secondary Stream Input
.. , 10-2
10.1.3 Hardware Cursor Generation 10-2
10.1.4 Frame Buffer Organization/
Double Buffering ...... , 10-2
iii

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
10.2 INPUT PROCESSING ........ 10-4
10.2.1 Primary Stream Processing
.. 10-4
10.2.2 Secondary Stream Processing. 10-5
10.3 COMPOSITION/OUTPUT
...... 10-5
10.3.1 Opaque Rectangular Overlaying10-6
10.3.2 Blending
........ . 10-7
10.3.3 Color/Chroma
Keying. . 10-8
10.3.4
Window Location. . . . . 10-8
10.4 STREAMS FIFO CONTROL. . 10-8
Section 11: Local Peripheral Bus 11-1
11.1 Scenic/MX2 INTERFACE ...... 11-2
11.1.1 Scenic/MX2 Register/Memory
Access
.............. 11-2
11.1.2 Scenic/MX2 Compressed Data
Transfer . . . . . . . . .
.. . 11-4
11.1.3 Scenic/MX2 Video Capture
.. 11-5
11.2 DIGITIZER INTERFACE
.. .11-7
11.2.1 1
2C Register
Interface. .11-7
11.2.2 SAA7110Videolnput. .11-8
11.3 CL-480INTERFACE... .11-9
11.4 HOST PASS-THROUGH 11-10
11.5 LPB-ENABLED PIN
ASSIGNMENTS. . . . . 11-10
Section 12: Miscellaneous
Functions ............. 12-1
12.1 VIDEO BIOS ROM INTERFACE ... 12-1
12.1.1 Disabling BIOS ROM Accesses 12-1
12.1.2 BIOS ROM Hardware Interface 12-1
12.1.3 BIOS ROM Read Functional
Timing .............. 12-2
12.1.4 BIOS ROM Address
Mapping . 12-2
12.2 GREEN
PC SUPPORT. . . . 12-4
12.3 GENERAL INPUT
PORT . . 12-4
12.4 GENERAL OUTPUT PORT . 12-5
12.5 FEATURE CONNECTOR
INTERFACE . . . . . . . . . 12-7
12.6 SERIAL COMMUNICATIONS
PORT . . . . . . . . . . . . .
12-11
12.7 INTERRUPT GENERATION. . 12-11
Section 13: Basic Software
Functions . . . . . . . . . .
13-1
13.1 CHIP WAKEUP ........... 13-1
13.2 REGISTER ACCESS ......... 13-2
13.2.1
Unlocking the S3 Registers . 13-2
13.2.2 Locking
the S3 Registers. . 13-3
13.2.3 Unlocking/Locking Other
Registers ............ 13-3
iv
13.3 TESTING FOR THE PRESENCE
OF A Trio64V+ CHIP ... 13-4
13.4 GRAPHICS MODE SETUP
... 13-4
Section 14: VGA Compatibility
Support ............ 14-1
14.1 VGACOMPATIBILITY. . . . . 14-1
14.2 VESA SUPER VGA SUPPORT 14-2
Section 15: Enhanced Mode
Programming .......... 15-1
15.1 LINEAR ADDRESSING FOR DIRECT
VIDEO MEMORY
CPU ACCESSES 15-1
15.2 VIDEO MEMORY ACCESS THROUGH
THE GRAPHICS ENGINE . . . .. 15-2
15.3 MEMORY MAPPING
OF
REGISTERS ........... .
15.3.1 Backward-Compatible
MMIO
15.3.2 New MMIO ....... .
15.4 PROGRAMMING
..... .
15.4.1 Notational Conventions
15.4.2 Initial Setup ...... .
15.4.3
Programming Examples
15.4.3.1 Solid Line
..... .
15.4.3.2 Textured Line
... .
15.4.3.3 Rectangle Fill Solid .
15.4.3.4 Image
Transfer-Through
15-4
15-4
15-6
15-7
15-7
15-8
15-8
15-9
15-10
15-12
the Plane
.......... 15-13
15.4.3.5 mage
Transfer-Across
the Plane .......... 15-15
15.4.3.6
BitBLT-Through the Plane 15-17
15.4.3.7 BitBLT
-Across the Plane . 15-18
15.4.3.8 PatBLT-Pattern Fiii
Through the Plane ..... 15-20
15.4.3.9 PatBLT-Pattern Fill Across
the Plane . . . . . . .
.. 15-21
15.4.3.10 Short Stroke Vectors
.. 15-22
15.4.3.11 Programmable Hardware
Cursor . . . . . . . . 15-23
15.5 RECOMMENDED READING
.. 15-24
Section 16: VGA Standard Register
Descriptions
........... 16-1
16.1
16.2
16.3
16.4
16.5
GENERAL REGISTERS .... .
SEQUENCER REGISTERS .. .
CRT CONTROLLER REGISTERS
GRAPHICS CONTROLLER
REGISTERS
.......... .
ATTRIBUTE CONTROLLER
REGISTERS
........... .
", .
IU-I
16-5
16-21
16-36
16-43

II·
Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
16.6 RAMDAC REGISTERS ...... 16-49
Section 17: S3 VGA Register
Descriptions . . . . . . .. ., 17-1
Section 18: System Control
Register Descriptions . .. . 18-1
Section 19: System Extension
Register Descriptions . . . . . . 19-1
Section 20: Enhanced Commands
Register Descriptions ...... 20-1
Section 21: Streams Processor
Register Descriptions . . . 21-1
Section 22: LPB Register
Descriptions . . . . .. . ... 22-1
Section 23: PCI Register
Descriptions . . . . . . 23-1
Appendix A: Register Reference A-l
A.1 VGA REGISTERS ........... A-2
A.2 S3 VGA REGISTERS
........ A-11
A.3 SYSTEM CONTROL REGISTERS . A-13
A.4 SYSTEM EXTENSION REGISTERS A-15
A.5 ENHANCED COMMANDS
REGISTERS
............ A-19
A.6 STREAMS PROCESSOR
REGISTERS
............ A-23
A.7
LPB REGISTERS .......... A-27
A.8
PCI CONFIGURATION SPACE
REGISTERS
............ A-30
Index ................ 1-1
v

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
#
2-1
3-1
3-2
4-1
4-2
4-3
4-4
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
9-1
10-1
10-2
11-1
11-2
vi
List of Figures
Title Page
208-pin PQFP Mechanical
Dimensions . . . . . . . .
2-2
Trio64V+ PCI Bus Pinout-
LPB Mode . . . . . . . . . 3-2
Trio64V+ VL-Bus Pinout -
LPB Mode . . . . . . . . 3-3
Clock Waveform Timing 4-4
Input Timing .. . . 4-5
Output Timing . . . . 4-7
ResetTiming . . . . . .4-10
Basic PCI Read Cycle . 6-2
Basic
PCI Write Cycle. 6-2
PCI Disconnect Example A . 6-3
PCI Disconnect Example B . 6-3
PCI Configuration Write Cycle 6-4
PCI Configuration Read Cycle 6-4
Read Parity Operation . . . . 6-5
VL-Bus Read Cycle . . . . . . 6-7
1Wait-state VL-Bus Write Cycle. 6-8
1- or 2-MByte DRAM
Configuration . . . . . . . .
.. 7-2
4-MByte DRAM
Configuration. 7-3
Fast Page Mode Read Cycle
.. 7-4
Fast Page Mode
Write Cycle .. 7-5
Fast Page Mode Read/Modify/
Write Cycle . . . . . . . . . .. 7-6
EDO Mode Read Cycle . . . .. 7-7
EDO Mode Read/Modify/Write
Cycle ............. " 7-8
1-Cycle
EDO Mode Read/Write 7-9
1-cycle EDO Read/Modify/Write
Cycle ................ 7-10
Internal RAMDAC Block Diagram
8-1
PLL Block Diagram . . . . . . 9-2
Streams Processor . . . .
.. . 10-1
Screen Definition Parameters . 10-5
LPB Internal Block Diagram . 11-1
Trio64V+ to Scenic/MX2
Hardware Interface
.... , . 11-2
#
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
Title Page
Scenic/MX2 Write
(Scenic/MX2 Ready) 11-3
Scenic/MX2 Write
(Scenic/MX2
Not Ready) 11-3
Scenic/MX2
Read
(Scenic/MX2 Ready) .. 11-3
Scenic/MX2
Read
(Scenic/MX2 Not Ready) 11-3
Scenic/MX2 Compressed
Transfer (Ready)
.... 11-4
Scenic/MX2 Stopping a
Compressed Xfer . . . . 11-5
Scenic/MX2 VSYNC and
HSYNC Protocols . . . . 11-5
Scenic/MX2 Video
Input
(Trio64V+ Ready) . . . . 11-6
Scenic/MX2 Video
Input
(Trio64V+ Not Ready) . . 11-6
Tri064V+ to SAA7110 Digitizer
Interface . . . . . . . . 11-7
16-
to 8-bit Video Data
Conversion
...... 11-8
Video 81n or
16 Mode Input 11-8
Video 8 In or
16 Mode Input 11-9
BIOS ROM PCI Configuration
Interface. . . . . . . . . . .. 12-1
BIOS ROM VL-Bus Configuration
Interface . . . . . . . . . . . 12-2
BIOS ROM Read Functional
Timing - PCI . . . . . . . . . 12-3
General Input Port Interface
(VL-Bus) . . . . . . . . . . . 12-4
General Input Port Timing
(VL-Bus) . . . . . . . . . . . 12-5
General I/O Port Timing (PCI) 12-5
General Output Port Interface
(VL-Bus) . . . . . . . . . . . 12-6
General Output Port Timing
(VL-Bus) . . . . . . . . . . . 12-6

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
# Title Page
12-9 VAFC
Implementation
(32-bit PO Bus)
....
· 12-8
12-10 VAFC
Implementation
(64-bit PO Bus)
....
· 12-8
12-11 Pass-Thru Feature Connector
(32-bit
PO) . . . . . . . . . . . · 12-9
12-12 Pass-Thru Feature Connector
(64-bit
PO) ........
· 12-9
15-1 Pixel Update Flowchart ...
· 15-3
vii

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
#
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
5-1
6-1
7-1
8-1
9-1
viii
List of Tables
Title
Pin Descriptions - LPB Mode.
Alphabetical Pin Listing .. .
Numerical Pin Listing .... .
Absolute Maximum Ratings.
RAMDAC/Clock Synthesizer DC
Page
3-4
. 3-12
. 3-15
4-1
Specifications . . . . . . . . 4-1
RAMDAC Characteristics. . 4-1
Digital DC Specifications . . 4-2
RAMDAC AC Specifications 4-3
Clock Waveform Timing . . 4-4
SCLK-Referenced Input Timing 4-5
LCLK-Referenced
Input Timing 4-6
MCLK-Referenced
Input Timing 4-6
SCLK-Referenced Output Timing 4-7
LCLK-Referenced
Output Timing 4-8
MCLK-Referenced
Output Timing 4-8
CL-480 Timings -Tri064V+ Driving
Host
Interface. . . . . . . . . . . 4-8
Feature
Connector Timing - Output
from Tri064V+ to Feature
Connector . . . . . . . . . . . .. 4-8
Feature
Connector Timing -
Output from Feature Connector to
Tri064V+. . . . . . . . . . . . . . 4-9
Reset
Timing ........... 4-10
Definition of PD[28:0) at the Rising
Edge
of the Reset Signal . . . .. 5-2
VL-Bus
Upper Address Decoding 6-6
Memory Size/Chip Count
Configurations ...... .
Tri064V+
Color Modes .. .
PLL R Parameter
Decoding.
7-1
8-2
9-1
#
10-1
10-2
11-1
12-1
12-2
12-3
13-1
14-1
15-1
15-2
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
Title Page
Register Fields Used For
Specifying
Frame Buffer Organization and
Double Buffering . . . . . . .. 10-3
Register Fields Used For Scaling
Up the Secondary Stream . .. 10-6
LPB-Enabled Pin
Assignments. 11-11
Tri064-compatible Feature
Connector
Configuration 12-7
LPB Feature Connector
Configuration (VL-Bus) . 12-10
LPB Feature Connector
Configuration (PCI) . . . 12-10
VGA Register Access Control
Extensions. . . . . . . . . .. 13-3
Standard VGA Registers
Modified
or Extended in the Tri064V+ 14-1
Enhanced Registers Memory
Mapping. . . . . . . . 15-5
New MMIO Addresses 15-6
VGA Registers .... . A-2
S3 VGA Registers A-11
System Control Registers A-13
System Extension Registers A-15
Enhanced
Commands Registers A-19
Streams Processor Registers. A-23
LPB Registers . . . . . . A-27
PCI Configuration Space
Registers. . . . . . . . . A-30

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
Section 1: Introduction
High-Performance Integrated Graphics/Video
Accelerator
High-performance DRAM-based 64-bit
graphics engine
• Integrated 24-bit RAMDAC with 135 MHz
output pixel rate and programmable
dual-clock synthesizer
• Unique S3 Streams Processor for hard-
ware-assisted video playback
S3 Scenic Highway for direct interface to
live video and MPEG-1 peripherals
S3
Trio64-compatible Mode Option
S3 Streams Processor Features
• Supports on-the-fly stretching and blend-
ing of primary RGB stream and RGB or
YUV
(video) secondary stream
• Each stream can have different color
depths
YUV data is
color space converted
Advanced Playback Capabilities
•
High-quality hardware-assisted video
playback (up to 1024x758x16 bits/pixel)
Support for India, Cinepak, and software-
accelerated MPEG-1 video playback
Game and Presentation Effects.
Hardware
double-buffering support for
high-quality tear-free playback
• 2-D scrolling and sprite plane support
• Color and chroma keying for overlaying
of graphics onto video and video onto
graphics
• Arithmetic blending of two pixel
streams
for fade-in/fade-out transition
effects
S3 Scenic Highway Interface
• Philips SAA7110/SAA7111 video
digitizers
S3 Scenic/MX2 MPEG-1 audio/video
decoder, C-Cube CL-480 MPEG-1 de-
coder
High Non-Interlaced Screen Resolution
Support
• 1280x1024x256 colors at 75 Hz refresh
• 1024x768x64K colors at 75 Hz refresh
• 800x600x16.7M colors at 75 Hz refresh
High-Performance
Memory Interface
• 54-bit DRAM
memory interface
Supports 1-. 2-, or 4-MByte frame buffer
• Supports standard fast page mode and
EDO DRAMs (50 MHz) and 1-cycle EDO
DRAMs (50 MHz)
Supports CPUs with Big or Little Endian Byte
Ordering
Industry-Standard Local Bus Support
Glueless PCI bus support (fully compli-
ant with Revision 2.0)
• Glueless VESA® VL-Bus
support
INTRODUCTION 1-1

Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
Multimedia Support Hooks
• Glueless 16-bit VESA Advanced Feature
Connector
(VAFC)
• 8-bit bidirectional feature connector
• S3 Scenic Highway
• 1
2C bus
Full
Software Support
• Drivers for Windows® 3.11, Windows®
NT, Windows® 95, OS/2® 2.1 and 3.0
(WarpTM), SCO®UNIX®
Green PC/Monitor Plug and Play Support
• Full hardware and BIOS support for
VESA Display Power Management Sig-
naling (DPMS) monitor power savings
modes
• DDC monitor communications support
Extensive Static/Dynamic Power Management
Industry-Standard 20S-pin
PQFP package
1.1 OVERVIEW
The S3® Tri064V+TM integrated graphics/video
accelerator (hereinafter referred to as the
Tri064V+) combines high-performance graphics
and high-qualityvideo acceleration features
with
the capability to directly interface to live video
and
MPEG-1 peripherais. it incorporates an en-
hanced version of the 64-bit graphics accelerator
core and high-performance
135 MHz true-color
RAMDAC that
are found in S3's Tri064™ accel-
erator. All display applications that require high-
quality video playback (from a CD-ROM or hard
drive), or live video
input capability, can take
advantage
of the Tri064V+'s new features. The
Tri064V+ accelerates and enhances software
MPEG-1/lndeo™ /Cinepak™ video playback by
providing arbitrary scaling
with high-quality lin-
ear interpolation and color space conversion
(RGB to YUV). By performingthese tasks in hard-
ware and relieving the CPU of a substantial over-
head, the Tri064V+ offers high-quality video
playback
with window sizes of upto 1024x768x16
bits/pixel at high frame rates. The Tri064V+ has
an S3 Scenic HighwayTM interface that provides
adirectinterface to
MPEG-1 audio/video decoder
1-2 INTRODUCTION
devices and live video digitizers to attain full-mo-
tion video.
1.2 S3 STREAMS PROCESSOR
The S3 Streams Processor™ allows the mixing
of three separate display streams. The primary
stream
can be RGB data of any color depth. The
secondary stream
can be RGB or YUV (video)
data
of any color depth. YUV data is color space
converted
to RGB. The third stream, the hard-
ware cursor, overlays the other two streams.
Arithmetic blending
of aprimarygraphics stream
and secondary graphics/video enables dramatic
transition effects
for game applications. Color
and chroma keying allow opaque
or transparent
overlays
of one stream on the other. Hardware-
assisted double buffering of both primary and
secondary data streams is also provided to en-
able high-quality "tear-free" playback.
The Tri064V+ also enhances game acceleration,
with support for a sprite plane where sprites are
actually rendered into a sprite plane memory.
Sprites can be overlaid onto the background
without saving and restoring the background.
The Streams Processor is located in the pixel
datapath between the display
memory and the
RAMDACthatdrivesthe
RGB signals to the moni-
tor. One of the key advantages of this architec-
ture is that it permits processing of pixel streams
on the
fly atdisplayrefresh rates. This eliminates
the need to first write back processed (scaled
or
color-space-converted) data intothe frame buffer
before sending
it to the RAMDAC. This saves
memory storage and memory bandwidth.
The Streams Processor also enables simultane-
ous display
of graphics and video of different
color depths. For example,
it is possible to dis-
play 24 bits/pixel-equivalent video on top of an
8-bit graphics background. This also saves mem-
ory bandwidth and storage capacity while per-
mitting higher frame rates because of reduced
bandwidth requirements.
In addition, if an opaque rectangular window of
one stream is overlaid onto another background
window of a second stream, it is not necessary

Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
to fetch and refresh the hidden pixels. This pro-
vides additional
memory bandwidth savings.
1.3 S3 SCENIC HIGHWAY
The S3 Scenic Highway interface directly con-
nects
to MPEG-1 audio/video decoders.such as
the S3 Scenic/MX2™ MPEG-1 audio/Video de-
coder and the C-Cube® CL-4S0 as well as video
digitizers such as the Philips® 7110n111. This
provideseasy implementation of MPEG-1 ordigi-
tal video daughtercards that directly plug intothe
Scenic Highway connector or, alternately, ISA
cards, where a ribbon cable is also necessary.
The Streams Processor and Scenic Highway
are
tightly coupled to provide optimal live video
playback. The hardware automatically switches
capture and display buffers
without software in-
tervention.
1.4 Trio64V+ CHANGES FROM THE
Trio64
The Tri064V+ comes in two configurations, se-
lectable by power-on strapping.
• Compatible Mode (compatibility with
Tri064)
• Local Peripheral Bus
(LPB) Mode
In compatible mode, the Tri064V+ can be in-
stalled in a Tri064 socket. Some software modi-
fications are required to operate the chip. The
pinout changes significantly for LPB mode. This
means that compatible mode and LPB mode are
not compatible. That is, a given design must be
based one or the other. Once the chip is enabled
in one mode, it must not be switched tothe other.
This data book describes only how the Tri064V+
operates in
LPB mode. In compatible mode, the
physical and functional characteristics of the
Tri064V+ are the same as described fortheTri064
in the Trio32/Trio64 Graphics Accelerators Data
Book(DB014-A).
A major functional difference available in either
mode is the S3 Streams Processor described
earlier in this section. In addition to the Streams
Processor, the following new features are pro-
vided in either compatible
or LPB mode:
• All registers addresses relocatable for
plug and play support
• Big and little endian addressing support
(PowerPCTM /Intel®)
• 50 MHz single-cycle EDO memory sup-
port
• Power down input signal to power down
the DAC RGB output
• Packed 24 bits/pixel (unaccelerated)
mode
Pass-through mode allowing decimation
of 32-bit CPU writes to the frame buffer
The following new features are provided only in
LPB mode:
Bi-directional Scenic/MX2 Scenic High-
way interface in either VL-BuS™ or PCI
bus configuration
• In PCI configurations, input only or bi-di-
rectional CL-4S0 Scenic Highway inter-
face
• In PCI configurations, 16-bitdigitizer
data Scenic Highway interface
• Serial Communications Port (i
2C and
DDC2 monitor communications)
• Serial port can optionally be accessed
via I/O ports E2 or ES to allow use when
the Tri064V+ is disabled
• S-bit bi-directional (VL-Bus or PCI) or 16-
bit
VAFC (PCI bus) feature connector sup-
port that is not restricted to 1-MByte
video modes as with the Tri064 and
which requires no external glue logic
• Support for 4 MBytes of EDO memory in
PCI configurations
• General Input/Output Port support via
the LPB data bus
INTRODUCTION 1-3

Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
The following Trio64features are not available in
LPB mode:
• Genlocking
• Shared
frame buffer support
Direct decoding of the VL-Bus SA[31 :23]
lines. Two SAUP inputs provide indirect
decoding via external logic
4 MBytes of fast page memory in VL-
Bus configurations
1-4 INTRODUCTION

Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
Section 2: Mechanical Data
2.1 THERMAL SPECIFICATIONS
Parameter Min Typ
Max Unit
Thermal Resistance 0JC
5 °C/W
Thermal Resistance
0JA (Still Air)
24
°C/W
Junction Temperature 125 °C
2.2 MECHANICAL DIMENSIONS
The Trio64V+ comes in a 208-pin PQFP package. The mechanical dimensions are given in Figure 2-1.
MECHANICAL DATA 2-1

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
30.60,.0.30
29.60,.0.20
28.80
0.50,.0.10
LINEAR DIMENSIONS
ARE IN MILLIMETERS
0.20,.0.08.11.
0.50,.0.20
Figure 2-1. 20S-pin PQFP Mechanical Dimensions
2-2 MECHANICAL DATA
mechdim
o
'"
~
.,;
'"

Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
Section 3: Pins
3.1 PINOUT DIAGRAMS
The Tri064V+ comes in a208-pin PQFP package. Ithas two primary operating modes with significantly
different pin definitions. These modes are selected according to the strapping of the PD24 pin at
power-on reset.
If PD24 isstrapped low at reset, the Trio64V+ powers up in Local Peripheral Bus (LPB) mode. This mode
is not pin compatible with the Tri064 but offers additional functions. The pinout for this mode for a PCI
configuration is shown in Figure 3-1. The pinout for this mode for a VL-Bus configuration is shown in
Figure 3-2.
PINS 3-1

Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
XOUT POOIGAO'
CLKAVDD1 PD141GA14'
AVSS PD1fGA,'
CLKAVDD2 PDl3/GA13'
AVSS PD2fGA2'
VREF VSS
AVSS PDl2fGA12'
AVOC POOIGA3'
PDOWN' VOO
RSET PD11IGA 11'
AVSS P04lGA4'
AR PD10IGA10'
AVDD PDSlGAS'
AVOD PD9/GA9'
AG PD6/GAS'
AB P08!GAs'
AVSS P07/GA7'
LD4IPA4' vss
LOS/PAS' CASO
HSELO' CAS1
HSEl,' RASO
HSEL2' CAS2
~. CAS3
1Wi' Trio64V+ (PCI) voo
'DffiK. MAS
CF~;~~~: LPB MODE ~::
lD81~=~: TOP VIEW ::!
LD9JPA9IH01' MA2
LD101PA101HD2' MAS
LD111PA111HD3' MA3
LOl21PA121HD4' MA4
~GOP1' vss
iCANK* POOt
von PDl6lGOO'
FiEill PD30
SClK PD17/GD,'
VSS PD29
velKI' PDt8/GOZ'
RESERVE[) FOR PCI GN,... PD28
RESERVED FOR PCI REa< PD19JGD3'
LDt3lPA131HOS' von
LDl41PA141H06' POO7
LDl5/PA1SJHD7' VSS
LD7IPA7' PD20IG04'
~RDY/HSlEVlDEO' PD26
CREQlCRDYNS/EVCLK' PD21IGOS'
SPCLK' POlS
gPO' PD22IG06'
AOOl POl4
AD30 -"'M'TIM'TIM'TIM'TIM'TIM'TIM'TIM'TIrTI'rTI'rTI'rTI'rTI'rTI'rTI'rTI'rTI'mmmmmmmmmmmmmmmmm-f"- P023/G07'
KVPCIPIN
•=Pin functions changed from Compatible Mode
Figure 3-1, Trio64V+ PCI Bus Pinout - LPB Mode
3-2 PINS

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
XOUT POO
CLKAVOD1 PD14
AYSS PD1
CLKAVDD2 P013
AVSS PD2
VREF YSS
AVSS P012
AVOO PD3
~ VOO
RSET PDtt
AVSS PD4
AA ~
AVOD POS
AVDD POG
~ ~
~ ~
AVSS P07
LD4IPM* vss
LD5JP AS· CAsii
SA2 CASi
SAl nm
SA4 ~
~ Trio64V+ (VL-BUS) ~~~'
SA7 MA8
= LPB MODE ::~
L~~; TOP VIEW :~:
SA11 MA2
SA12 MAS
SA13 MA3
SA14 MA4
SAlS VSS
SAt6 P031
VOO PDt6
SRrSH' P030
SClK PDt7
VSS P029
SAt7 POtS
SAtS P02S
SA11 POtl
SA20 VDD
SA2t P027
SA22 VSS
lD71PA7' PD20
V"'REOivRDYIHSJEVIOEO' P026
C""REciicRDYNSJEVCLK' PD21
SPCLKlESYNC* P02S
SPDnlrANR' PD22
SOOt PD24
so,. -"lnTTTTTTTTTT'I'TT'I'TI'TTI'TTI'TT~~I'm~m-,m-,TTTTTTTTTTTTT'I'Tl'TTl'TTl'TTl'TTl'mlTl'rml'mm-,m-,'TTI'TTITTTTTT"'--- PD2'
KVVLP1NS
Figure 3-2. Trio64V+ VL-Bus Pinout - LPB Mode
PINS 3-3

II·
Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
3.2 PIN DESCRIPTIONS
The following table provides a brief description of each pin on the Trio64V+ for its PCI bus and VL-Bus
configurations in LPB mode. The following abbreviations are used for pin types.
I - Input signal
o - Output signal
B -Bidirectional signal
Some pins have mUltiple names. This either reflects the different functions performed by those pins
depending on the bus configuration selected by power-on-strapping
or multiplexed pins whose
functions are selected via a register bit setting. The pin definitions and functions are given for each
possible case.
Table 3-1. Pin Descriptions -
LPB Mode
Symbol Type Pin Numberls) Description
BUS INTERFACES
Address and Data
AD[31
:0]
B 207-208,
1-6, (PCI) Multiplexed Address/Data Bus. A bus transaction
10-11. 13-18,
(cycle) consists of an address phase followed by one
28-31,33-36, or more data phases.
39-46
SD[31 :0]
B
(VL) System Data Bus.
SA[22:2] I 201-196,191- (VL) System Address Bus Lines 22:2.
185, 183-176
SAUP1 (VL)
I 25
(VL) Upper Address Decode 1. In conjunction with
SAUP2 this input tells the Trio64V+ when to respond
when its memory/register address space
has been
relocated above 4 MBytes. Specifically,
SAUPI =
0, SAUP2 =1- register/port address access
SAUPl = 1, SAUP2 =0 - video memory access
The other
two combinations are ignored.
SAUP2 (VL)
I 50
(VL) Upper Address Decode 2. See definition for
SAUP1.
C/BE[3:0] I
7,19,27,38
(PCI) Bus Command/Data Byte Enables. These signals
carry the
bus command during the address phase and
the byte enables during the data phase.
SBE[3:0] (VL) Data Byte Enables.
Bus Control
SCLK I 194
(PCI) PCI System Clock.
SCLK I
(VL) CPU System Clock
INTA 0
152
(PCI) Interrupt Request.
SINTR
(VL) Interrupt Request.
3-4 PINS

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
Table 3-1. Pin Descriptions - LPB Mode (Continued)
Symbol Type Pin Number(s) Description
IRDY I 21
(PCI) Initiator Ready. A bus data phase is completed
when both IRDY and TRDY are asserted on the same
cycle.
RDYIN
(VL) Local Bus Cycle End Acknowledge. The Tri064V+
holds read data valid on the system data bus until this
input
is asserted.
TRDY 0
23
(PCI) Target Ready. A bus data phase is completed
when both IRDY and TRDY are asserted on the same
cycle.
SRDY
(VL) Local Bus Cycle End.
DEVSEL 0 24
(PCI) Device Select. The Tri064V+ drives this signal
active when it decodes its address
as the target of the
current access.
LOCA
(VL) Local Bus Access Cycle Indicator. This signal is
output during local bus cycles to allow system logic
chip sets
to prevent concurrent EISA/ISA cycle
generation.
IDSEL I 8
(PCI) Initialization Device Select. This input is the chip
select for
PCI configuration register reads/writes.
SM/IO I
(VL) Memory/I/O Cycle Indicator. This signal is high for
a memory cycle and
low for an I/O cycle.
RESET I 193
(PCI) System Reset. Asserting this signal forces the
registers and state machines to a known state.
SRESET
(VL) ~stem Reset.
FRAME I
20
(PCI) Cycle Frame. This signal is asserted by the bus
master
to indicate the beginning of a bus transaction.
It is deasserted during the final data phase of a bus
transaction.
SADS
(VL) System Address Strobe.
PAR 0 26
(PCI) Parity. The Tri064V+ asserts this signal to verify
even parity during reads.
SW/R I
(VL) Write/Read Cycle Indicator. This signal is high for
a write and low for a read.
PINS 3-5