ARM Cortex A9 Product manual

Copyright © 2008-2012 ARM. All rights reserved.
ARM DDI 0388I (ID073015)
Cortex™-A9
Revision: r4p1
Technical Reference Manual

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Cortex-A9
Technical Reference Manual
Copyright © 2008-2012 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
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Web Address
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Change history
Date Issue Confidentiality Change
31 March 2008 A Non-Confidential First release for r0p0
08 July 2008 B Non-Confidential Restricted Access First release for r0p1
17 December 2008 C Non-Confidential Restricted Access First release for r1p0
30 September 2009 D Non-Confidential Restricted Access First release for r2p0
27 November 2009 E Non-Confidential Second release for r2p0
30 April 2010 F Non-Confidential First release for r2p2
19 July 2011 G Non-Confidential First release for r3p0
22 March 2012 H Non-Confidential First release for r4p0
15 June 2012 I Non-Confidential First release for r4p1

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Contents
Cortex-A9 Technical Reference Manual
Preface
About this book .......................................................................................................... vii
Feedback .................................................................................................................... xi
Chapter 1 Introduction
1.1 About the Cortex-A9 processor ............................................................................... 1-2
1.2 Cortex-A9 variants ................................................................................................... 1-4
1.3 Compliance .............................................................................................................. 1-5
1.4 Features ................................................................................................................... 1-6
1.5 Interfaces ................................................................................................................. 1-7
1.6 Configurable options ................................................................................................ 1-8
1.7 Test features ............................................................................................................ 1-9
1.8 Product documentation and design flow ................................................................ 1-10
1.9 Product revisions ................................................................................................... 1-12
Chapter 2 Functional Description
2.1 About the functions .................................................................................................. 2-2
2.2 Interfaces ................................................................................................................. 2-4
2.3 Clocking and resets ................................................................................................. 2-6
2.4 Power management ............................................................................................... 2-10
2.5 Constraints and limitations of use .......................................................................... 2-15
Chapter 3 Programmers Model
3.1 About the programmers model ................................................................................ 3-2
3.2 ThumbEE architecture ............................................................................................. 3-3
3.3 The Jazelle Extension .............................................................................................. 3-4
3.4 Advanced SIMD architecture ................................................................................... 3-5
3.5 Security Extensions architecture ............................................................................. 3-6
3.6 Multiprocessing Extensions ..................................................................................... 3-7

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3.7 Modes of operation and execution ........................................................................... 3-8
3.8 Memory model ......................................................................................................... 3-9
3.9 Addresses in the Cortex-A9 processor ................................................................. 3-10
Chapter 4 System Control
4.1 About system control .............................................................................................. 4-2
4.2 Register summary .................................................................................................... 4-3
4.3 Register descriptions ............................................................................................. 4-18
Chapter 5 Jazelle DBX registers
5.1 About coprocessor CP14 ......................................................................................... 5-2
5.2 CP14 Jazelle register summary ............................................................................... 5-3
5.3 CP14 Jazelle register descriptions .......................................................................... 5-4
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................................ 6-2
6.2 TLB Organization ..................................................................................................... 6-4
6.3 Memory access sequence ....................................................................................... 6-6
6.4 MMU enabling or disabling ...................................................................................... 6-7
6.5 External aborts ......................................................................................................... 6-8
Chapter 7 Level 1 Memory System
7.1 About the L1 memory system .................................................................................. 7-2
7.2 Security Extensions support .................................................................................... 7-4
7.3 About the L1 instruction side memory system ......................................................... 7-5
7.4 About the L1 data side memory system .................................................................. 7-8
7.5 About DSB ............................................................................................................. 7-10
7.6 Data prefetching .................................................................................................... 7-11
7.7 Parity error support ................................................................................................ 7-12
Chapter 8 Level 2 Memory Interface
8.1 About the Cortex-A9 L2 interface ............................................................................ 8-2
8.2 Optimized accesses to the L2 memory interface ..................................................... 8-7
8.3 STRT instructions .................................................................................................... 8-9
Chapter 9 Preload Engine
9.1 About the Preload Engine ........................................................................................ 9-2
9.2 PLE control register descriptions ............................................................................ 9-3
9.3 PLE operations ........................................................................................................ 9-4
Chapter 10 Debug
10.1 Debug Systems ..................................................................................................... 10-2
10.2 About the Cortex-A9 debug interface .................................................................... 10-3
10.3 Debug register features ......................................................................................... 10-4
10.4 Debug register summary ....................................................................................... 10-5
10.5 Debug register descriptions ................................................................................... 10-7
10.6 Debug management registers ............................................................................. 10-13
10.7 Debug events ....................................................................................................... 10-15
10.8 External debug interface ...................................................................................... 10-16
Chapter 11 Performance Monitoring Unit
11.1 About the Performance Monitoring Unit ................................................................. 11-2
11.2 PMU register summary .......................................................................................... 11-3
11.3 PMU management registers .................................................................................. 11-5
11.4 Performance monitoring events ............................................................................. 11-7
Appendix A Signal Descriptions
A.1 Clock signals ............................................................................................................ A-2

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A.2 Reset signals ........................................................................................................... A-3
A.3 Interrupts ................................................................................................................. A-4
A.4 Configuration signals ............................................................................................... A-5
A.5 WFE and WFI standby signals ................................................................................ A-6
A.6 Power management signals .................................................................................... A-7
A.7 AXI interfaces .......................................................................................................... A-8
A.8 Performance monitoring signals ............................................................................ A-14
A.9 Exception flags signal ............................................................................................ A-17
A.10 Parity signal ........................................................................................................... A-18
A.11 MBIST interface ..................................................................................................... A-19
A.12 Scan test signal ..................................................................................................... A-20
A.13 External Debug interface ....................................................................................... A-21
A.14 PTM interface signals ............................................................................................ A-24
Appendix B Cycle Timings and Interlock Behavior
B.1 About instruction cycle timing .................................................................................. B-2
B.2 Data-processing instructions ................................................................................... B-3
B.3 Load and store instructions ...................................................................................... B-4
B.4 Multiplication instructions ......................................................................................... B-7
B.5 Branch instructions .................................................................................................. B-8
B.6 Serializing instructions ............................................................................................. B-9
Appendix C Revisions

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Preface
This preface introduces the Cortex-A9 Technical Reference Manual (TRM). It contains the
following sections:
•About this book on page vii
•Feedback on page xi.

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About this book
This book is for the Cortex-A9 processor.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this book, where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This book is written for hardware and software engineers implementing Cortex-A9 system
designs. It provides information that enables designers to integrate the processor into a target
system.
Note
• The Cortex-A9 processor is a single core processor.
• The multiprocessor variant, the Cortex-A9 MPCore™processor, consists of between one
and four Cortex-A9 processors and a Snoop Control Unit (SCU). See the Cortex-A9
MPCore Technical Reference Manual for a description.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the Cortex-A9 processor and its features.
Chapter 2 Functional Description
Read this for a description of the functionality of the Cortex-A9 processor.
Chapter 3 Programmers Model
Read this for a description of the Cortex-A9 registers and programming
information.
Chapter 4 System Control
Read this for a description of the Cortex-A9 system control registers, their
structure, operation, and how to use them.
Chapter 5 Jazelle DBX registers
Read this for a description of the CP14 coprocessor and its non-debug use for
Jazelle DBX.
Chapter 6 Memory Management Unit
Read this for a description of the Cortex-A9 Memory Management Unit (MMU).
Chapter 7 Level 1 Memory System
Read this for a description of the Cortex-A9 level one memory system, including
caches, Translation Lookaside Buffers (TLB), and store buffer.

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Chapter 8 Level 2 Memory Interface
Read this for a description of the Cortex-A9 level two memory interface, the AXI
interface attributes, and information about
STRT instructions.
Chapter 9 Preload Engine
Read this for a description of the Preload Engine (PLE) and its operations.
Chapter 10 Debug
Read this for a description of the Cortex-A9 support for debug.
Chapter 11 Performance Monitoring Unit
Read this for a description of the Cortex-A9 Performance Monitoring Unit
(PMU) and associated events.
Appendix A Signal Descriptions
Read this for a summary of the Cortex-A9 signals.
Appendix B Cycle Timings and Interlock Behavior
Read this for a description of the Cortex-A9 instruction cycle timing.
Appendix C Revisions
Read this for a description of technical changes between released issues of this
book.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for
those terms. The ARM Glossary does not contain terms that are industry standard unless the
ARM meaning differs from the generally accepted meaning.
See ARM Glossary,
http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html .
Conventions
This book uses the conventions that are described in:
•Typographical conventions
•Timing diagrams on page ix
•Signals on page ix.
Typographical conventions
The typographical conventions are:
italic Introduces special terminology, denotes cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You can enter
the underlined text instead of the full command or option name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.

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monospace bold Denotes language keywords when used outside example code.
< and > Enclose replaceable terms for assembler syntax where they appear in code
or code fragments. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS Applies when the relevant term is used in body text. For example:
IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC,
UNKNOWN, and UNPREDICTABLE.
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
Key to timing diagram conventions
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and
they look similar to the bus change shown in Key to timing diagram conventions. If a timing
diagram shows a single-bit signal in this way then its value does not affect the accompanying
description.
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals
• LOW for active-LOW signals.
Lower-case n At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This section lists publications by ARM and by third parties.
See Infocenter,
http://infocenter.arm.com , for access to ARM documentation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

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ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
•ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406)
•Cortex-A9 MPCore Technical Reference Manual (ARM DDI 0407)
•Cortex-A9 Floating-Point Unit (FPU) Technical Reference Manual (ARM DDI 0408)
•Cortex-A9 NEON®Media Processing Engine Technical Reference Manual
(ARM DDI 0409)
•Cortex-A9 Configuration and Sign-Off Guide (ARM DII 00146)
•Cortex-A9 MBIST Controller Technical Reference Manual (ARM DDI 0414)
•CoreSight™PTM-A9 Technical Reference Manual (ARM DDI 0401)
•CoreSight PTM-A9 Integration Manual (ARM DII 0162)
•CoreSight Program Flow Trace Architecture Specification,v1.0 (ARM IHI 0035)
•CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual (ARM DDI
0246)
•AMBA AXI Protocol Specification (ARM IHI 0022)
•ARM Generic Interrupt Controller Architecture Specification (ARM IHI 0048)
•PrimeCell®Generic Interrupt Controller (PL390) Technical Reference Manual (ARM
DDI 0416)
•RealView®ICE User Guide (ARM DUI 0155)
•CoreSight Architecture Specification (ARM IHI 0029)
•CoreSight Technology System Design Guide (ARM DGI 0012)
•ARM Debug Interface v5 Architecture Specification (ARM IHI 0031)
Other publications
•ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic
•IEEE Std 1500-2005, IEEE Standard Testability Method for Embedded Core-based
Integrated Circuits.

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Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and
diagnostic procedures if appropriate.
Feedback on content
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[email protected] . Give:
• the title
• the number, ARM DDI 0388I
• the page numbers to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
Note
ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the
quality of the represented document when used with any other PDF reader.

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Chapter 1
Introduction
This chapter introduces the Cortex-A9 processor and its features. It contains the following
sections:
•About the Cortex-A9 processor on page 1-2
•Cortex-A9 variants on page 1-4
•Compliance on page 1-5
•Features on page 1-6
•Interfaces on page 1-7
•Configurable options on page 1-8
•Test feature s on page 1-9
•Product documentation and design flow on page 1-10
•Product revisions on page 1-12.

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1.1 About the Cortex-A9 processor
The Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache
subsystem that provides full virtual memory capabilities. The Cortex-A9 processor implements
the ARMv7-A architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb
instructions, and 8-bit Java bytecodes in Jazelle state.
Figure 1-1 shows a Cortex-A9 uniprocessor in a design with a PL390 Interrupt Controller and
an L2C-310 L2 Cache Controller,
Figure 1-1 Cortex-A9 uniprocessor system
1.1.1 Data engine
The design can include a data engine. The following sections describe the data engine options:
•Media Processing Engine
•Floating-Point Unit.
Media Processing Engine
The optional NEON Media Processing Engine (MPE) is the ARM Advanced Single Instruction
Multiple Data (SIMD) media processing engine extension to the ARMv7-A architecture. It
provides support for integer and floating-point vector operations. NEON MPE can accelerate
the performance of multimedia applications such as 3-D graphics and image processing.
When implemented, the NEON MPE option extends the processor functionality to provide
support for the ARMv7 Advanced SIMD and VFPv3 D-32 instruction sets.
See the Cortex-A9 NEON Media Processing Engine Technical Reference Manual.
Floating-Point Unit
When the design does not include the optional MPE, you can include the optional ARMv7
VFPv3-D16 FPU, without the Advanced SIMD extensions. It provides trapless execution and
is optimized for scalar operation. The Cortex-A9 FPU hardware does not support the deprecated
VFP short vector feature. Attempts to execute VFP data-processing instructions when the
Cortex-A9
uniprocessor
Debug
interface
Performance
Monitor Unit
(PMU)
Generic
Interrupt
Controller
(GIC)
Data Engine
(optional)
Either MPE
or FPU
Program
Trace
interface
CoreLink Level 2 Cache Controller (L2C-310) CoreSight
trace delivery infrastructure
nFIQ
nIRQ
Instruction
interface
Data
interface
APB
Preload
Engine
(optional)
Events

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FPSCR.LEN field is non-zero result in the FPSCR.DEX bit being set and a synchronous
Undefined Instruction exception being taken. You can use software to emulate the short vector
feature, if required.
See the Cortex-A9 Floating-Point Unit Technical Reference Manual.
1.1.2 System design components
This section describes the PrimeCell components in:
•PrimeCell Generic Interrupt Controller
•CoreLink Level 2 Cache Controller (L2C-310).
PrimeCell Generic Interrupt Controller
A generic interrupt controller such as the PrimeCell Generic Interrupt Controller (PL390) can
be attached to the Cortex-A9 uniprocessor. The Cortex-A9 MPCore contains an integrated
interrupt controller that shares the same programmers model as the PL390 although there are
implementation-specific differences.
See the Cortex-A9 MPCore Technical Reference Manual for a description of the Cortex-A9
MPCore Interrupt Controller.
CoreLink Level 2 Cache Controller (L2C-310)
The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a
recognized method of improving the performance of ARM-based systems when significant
memory traffic is generated by the processor. The CoreLink Level 2 Cache Controller reduces
the number of external memory accesses and has been optimized for use with Cortex-A9
processors and Cortex-A9 MPCore processors.

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1.2 Cortex-A9 variants
Cortex-A9 processors can be used in both a uniprocessor configuration and multiprocessor
configurations.
In the multiprocessor configuration, up to four Cortex-A9 processors are available in a
cache-coherent cluster, under the control of a Snoop Control Unit (SCU), that maintains L1 data
cache coherency.
The Cortex-A9 MPCore multiprocessor has:
• up to four Cortex-A9 processors
• an SCU responsible for:
— maintaining coherency among L1 data caches
—Accelerator Coherency Port (ACP) coherency operations
— routing transactions on Cortex-A9 MPCore AXI master interfaces
— Cortex-A9 uniprocessor accesses to private memory regions.
•anInterrupt Controller (IC) with support for legacy ARM interrupts
• a private timer and a private watchdog per processor
• a global timer
• AXI high-speed Advanced Microprocessor Bus Architecture version 3 (AMBA 3) L2
interfaces.
•anAccelerator Coherency Port (ACP), that is, an optional AXI 64-bit slave port that can
be connected to a DMA engine or a noncached peripheral.
See the Cortex-A9 MPCore Technical Reference Manual for more information.
The following system registers have Cortex-A9 MPCore uses:
•Multiprocessor Affinity Register on page 4-19
•Auxiliary Control Register on page 4-27
•Configuration Base Address Register on page 4-42.
Some PMU event signals have Cortex-A9 MPCore uses. See Performance monitoring signals
on page A-14.

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1.3 Compliance
The Cortex-A9 processor complies with, or implements, the specifications described in:
•ARM architecture
•Advanced Microcontroller Bus Architecture
•Program Flow Trace architecture
•Debug architecture
•Generic Interrupt Controller architecture
This TRM complements architecture reference manuals, architecture specifications, protocol
specifications, and relevant external standards. It does not duplicate information from these
sources.
1.3.1 ARM architecture
The Cortex-A9 processor implements the ARMv7-A architecture profile that includes the
following architecture extensions:
• Advanced Single Instruction Multiple Data (SIMD) architecture extension for integer and
floating-point vector operations
•Vector Floating-Point version 3 (VFPv3) architecture extension for floating-point
computation that is fully compliant with the IEEE 754 standard
• Security Extensions for enhanced security
• Multiprocessing Extensions for multiprocessing functionality.
See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition.
1.3.2 Advanced Microcontroller Bus Architecture
The Cortex-A9 processor complies with the AMBA 3 protocol. See the AMBA AXI Protocol
Specification.
1.3.3 Program Flow Trace architecture
The Cortex-A9 processor implements the Program Trace Macrocell (PTM) based on the
Program Flow Trace (PFT) v1.0 architecture. See the CoreSight Program Flow Trace
Architecture Specification.
1.3.4 Debug architecture
The Cortex-A9 processor implements the ARMv7 Debug architecture that includes support for
Security Extensions and CoreSight. See the CoreSight Architecture Specification.
1.3.5 Generic Interrupt Controller architecture
The Cortex-A9 processor implements the ARM Generic Interrupt Controller (GIC) v1.0
architecture.

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1.4 Features
The Cortex-A9 processor includes the following features:
• superscalar, variable length, out-of-order pipeline with dynamic branch prediction
• full implementation of the ARM architecture v7-A instruction set
• Security Extensions
• Harvard level 1 memory system with Memory Management Unit (MMU).
• two 64-bit AXI master interfaces with Master 0 for the data side bus and Master 1 for the
instruction side bus
• ARMv7 Debug architecture
• support for trace with the Program Trace Macrocell (PTM) interface
• support for advanced power management with up to three power domains
• optional Preload Engine
• optional Jazelle hardware acceleration
• optional data engine with MPE and VFPv3.

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1.5 Interfaces
The processor has the following external interfaces:
• AMBA AXI interfaces
• Debug v7 compliant interface, including a debug APBv3 external debug interface
•DFT.
For more information on these interfaces see:
•AMBA AXI Protocol Specification
•CoreSight Architecture Specification
•Cortex-A9 MBIST Controller Technical Reference Manual

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1.6 Configurable options
Table 1-1 shows the configurable options for the Cortex-A9 processor.
The MBIST solution must be configured to match the chosen Cortex-A9 cache sizes. In
addition, the form of the MBIST solution for the RAM blocks in the Cortex-A9 design must be
determined when the processor is implemented.
See the Cortex-A9 MBIST Controller Technical Reference Manual for more information.
Table 1-1 Configurable options for the Cortex-A9 processor
Feature Range of options
Instruction cache size 16KB, 32KB, or 64KB
Data cache size 16KB, 32KB, or 64KB
TLB entries 64, 128, 256 or 512 entries
BTAC entries 512, 1024, 2048 or 4096 entries
GHB descriptors 1024, 2048, 4096, 8192 or 16384 descriptors
Instruction micro TLB 32 or 64 entries
Jazelle Architecture Extension Full or trivial
Media Processing Engine with NEON technology Included or nota
a. The MPE and FPU RTL options are mutually exclusive. If you choose the MPE option, the MPE is
included along with its VFPv3-D32 FPU, and the FPU RTL option is not available in this case. When
the MPE RTL option is not implemented, you can implement the VFPv3-D16 FPU by choosing the
FPU RTL option.
FPU Included or nota
PTM interface Included or not
Wrappers for power off and dormant modes Included or not
Support for parity error detectionb
b. The Cortex A9 processor does not support Parity error detection on the GHB RAMs, for GHB
configurations of 8192 and 16384 entries.
-
Preload Engine Included or not
Preload Engine FIFO sizec
c. Only when the design includes the Preload Engine.
16, 8, or 4 entries
ARM_BIST Included or not
USE DESIGNWARE Use or not

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1.7 Test features
The Cortex-A9 processor provides test signals that enable the use of both ATPG and MBIST to
test the Cortex-A9 processor and its memory arrays. See Appendix A Signal Descriptions and
the Cortex-A9 MBIST Controller Technical Reference Manual.